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clk: stm32mp1: correctly handle Clock Spreading Generator
To activate the csg option, the driver need to set the bit2 of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator of PLLn enable. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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e74b74c528
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bbd108a082
2 changed files with 12 additions and 6 deletions
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@ -132,15 +132,15 @@ Optional Properties:
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frac = < 0x810 >;
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};
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st,pll@1 {
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cfg = < 1 43 1 0 0 PQR(0,1,1)>;
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csg = <10 20 1>;
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cfg = < 1 43 1 0 0 PQR(0,1,1) >;
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csg = < 10 20 1 >;
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};
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st,pll@2 {
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cfg = < 2 85 3 13 3 0>;
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csg = <10 20 SSCG_MODE_CENTER_SPREAD>;
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cfg = < 2 85 3 13 3 0 >;
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csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
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};
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st,pll@3 {
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cfg = < 2 78 4 7 9 3>;
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cfg = < 2 78 4 7 9 3 >;
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};
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st,pkcs = <
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CLK_STGEN_HSE
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@ -165,6 +165,7 @@
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/* used for ALL PLLNCR registers */
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#define RCC_PLLNCR_PLLON BIT(0)
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#define RCC_PLLNCR_PLLRDY BIT(1)
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#define RCC_PLLNCR_SSCG_CTRL BIT(2)
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#define RCC_PLLNCR_DIVPEN BIT(4)
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#define RCC_PLLNCR_DIVQEN BIT(5)
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#define RCC_PLLNCR_DIVREN BIT(6)
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@ -1319,7 +1320,10 @@ static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
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{
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const struct stm32mp1_clk_pll *pll = priv->data->pll;
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writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
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clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
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RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
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RCC_PLLNCR_DIVREN,
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RCC_PLLNCR_PLLON);
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}
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static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
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@ -1438,6 +1442,8 @@ static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
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RCC_PLLNCSGR_SSCG_MODE_MASK);
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writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
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setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
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}
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static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
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