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ARM: dts: k3-am64-main: Add CPSW DT nodes
AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same (based on kernel DT). Disable second port as its by default set to ICSS usage on EVM. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Vignesh Raghavendra
Lokesh Vutla
parent
845e1060d3
commit
bc17fccbd0
4 changed files with 185 additions and 0 deletions
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@ -178,6 +178,12 @@
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compatible = "ti,am654-chipid";
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reg = <0x00000014 0x4>;
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};
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phy_gmii_sel: phy@4044 {
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compatible = "ti,am654-phy-gmii-sel";
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reg = <0x4044 0x8>;
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#phy-cells = <1>;
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};
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};
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main_uart0: serial@2800000 {
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@ -403,6 +409,74 @@
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ti,clkbuf-sel = <0x7>;
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};
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cpsw3g: ethernet@8000000 {
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compatible = "ti,am642-cpsw-nuss";
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#address-cells = <2>;
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#size-cells = <2>;
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reg = <0x0 0x8000000 0x0 0x200000>;
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reg-names = "cpsw_nuss";
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ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
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clocks = <&k3_clks 13 0>;
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assigned-clocks = <&k3_clks 13 1>;
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assigned-clock-parents = <&k3_clks 13 9>;
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clock-names = "fck";
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power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
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dmas = <&main_pktdma 0xC500 15>,
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<&main_pktdma 0xC501 15>,
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<&main_pktdma 0xC502 15>,
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<&main_pktdma 0xC503 15>,
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<&main_pktdma 0xC504 15>,
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<&main_pktdma 0xC505 15>,
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<&main_pktdma 0xC506 15>,
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<&main_pktdma 0xC507 15>,
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<&main_pktdma 0x4500 15>;
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dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
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"tx7", "rx";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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cpsw_port1: port@1 {
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reg = <1>;
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ti,mac-only;
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label = "port1";
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phys = <&phy_gmii_sel 1>;
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mac-address = [00 00 de ad be ef];
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};
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cpsw_port2: port@2 {
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reg = <2>;
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ti,mac-only;
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label = "port2";
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phys = <&phy_gmii_sel 2>;
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mac-address = [00 01 de ad be ef];
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};
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};
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cpsw3g_mdio: mdio@f00 {
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compatible = "ti,cpsw-mdio","ti,davinci_mdio";
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reg = <0x0 0xf00 0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&k3_clks 13 0>;
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clock-names = "fck";
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bus_freq = <1000000>;
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};
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cpts@3d000 {
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compatible = "ti,j721e-cpts";
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reg = <0x0 0x3d000 0x0 0x400>;
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clocks = <&k3_clks 13 1>;
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clock-names = "cpts";
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interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cpts";
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ti,cpts-ext-ts-inputs = <4>;
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ti,cpts-periodic-outputs = <2>;
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};
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};
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main_gpio0: gpio@600000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x00 0x00600000 0x00 0x100>;
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@ -30,6 +30,8 @@
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serial8 = &main_uart6;
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i2c0 = &main_i2c0;
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i2c1 = &main_i2c1;
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ethernet0 = &cpsw_port1;
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ethernet1 = &cpsw_port2;
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};
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chosen { };
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@ -81,3 +81,19 @@
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&sdhci1 {
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u-boot,dm-spl;
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};
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&cpsw3g {
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reg = <0x0 0x8000000 0x0 0x200000>,
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<0x0 0x43000200 0x0 0x8>;
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reg-names = "cpsw_nuss", "mac_efuse";
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/delete-property/ ranges;
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cpsw-phy-sel@04044 {
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compatible = "ti,am64-phy-gmii-sel";
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reg = <0x0 0x43004044 0x0 0x8>;
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};
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};
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&cpsw_port2 {
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status = "disabled";
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};
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@ -6,6 +6,8 @@
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/dts-v1/;
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include "k3-am642.dtsi"
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/ {
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@ -101,6 +103,31 @@
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default-state = "off";
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};
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};
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mdio_mux: mux-controller {
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compatible = "gpio-mux";
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#mux-control-cells = <0>;
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mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
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};
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mdio-mux-1 {
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compatible = "mdio-mux-multiplexer";
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mux-controls = <&mdio_mux>;
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mdio-parent-bus = <&cpsw3g_mdio>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@1 {
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reg = <0x1>;
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#address-cells = <1>;
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#size-cells = <0>;
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cpsw3g_phy3: ethernet-phy@3 {
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reg = <3>;
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};
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};
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};
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};
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&main_pmx0 {
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@ -133,6 +160,47 @@
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AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
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>;
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};
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mdio1_pins_default: mdio1-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
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AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
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>;
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};
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rgmii1_pins_default: rgmii1-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
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AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
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AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
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AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
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AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
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AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
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AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
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AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
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AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
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AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
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AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
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AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
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>;
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};
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rgmii2_pins_default: rgmii2-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
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AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
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AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
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AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
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AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
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AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
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AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
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AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
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AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
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AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
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AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
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AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
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>;
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};
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};
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&main_uart0 {
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@ -227,6 +295,31 @@
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status = "disabled";
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};
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&cpsw3g {
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pinctrl-names = "default";
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pinctrl-0 = <&mdio1_pins_default
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&rgmii1_pins_default
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&rgmii2_pins_default>;
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};
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&cpsw_port1 {
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phy-mode = "rgmii-rxid";
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phy-handle = <&cpsw3g_phy0>;
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};
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&cpsw_port2 {
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phy-mode = "rgmii-rxid";
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phy-handle = <&cpsw3g_phy3>;
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};
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&cpsw3g_mdio {
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cpsw3g_phy0: ethernet-phy@0 {
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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};
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&sdhci0 {
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/* emmc */
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bus-width = <8>;
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