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ARM: uniphier: set up charge pump current for MPLL of LD11 SoC

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Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2017-02-21 23:00:35 +09:00
parent 9d35873161
commit bc64795804
3 changed files with 24 additions and 0 deletions
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21
arch/arm/mach-uniphier/clk/pll-base-ld20.c
View file

@ -18,6 +18,8 @@
#define SC_PLLCTRL_SSC_EN BIT(31) #define SC_PLLCTRL_SSC_EN BIT(31)
#define SC_PLLCTRL2_NRSTDS BIT(28) #define SC_PLLCTRL2_NRSTDS BIT(28)
#define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0) #define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0)
#define SC_PLLCTRL3_REGI_SHIFT 16
#define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16)
/* PLL type: VPLL27 */ /* PLL type: VPLL27 */
#define SC_VPLL27CTRL_WP BIT(0) #define SC_VPLL27CTRL_WP BIT(0)
@ -77,6 +79,25 @@ int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
return 0; return 0;
} }
int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
{
void __iomem *base;
u32 tmp;
base = ioremap(reg_base, SZ_16);
if (!base)
return -ENOMEM;
tmp = readl(base + 8); /* SSCPLLCTRL */
tmp &= ~SC_PLLCTRL3_REGI_MASK;
tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
writel(tmp, base + 8);
iounmap(base);
return 0;
}
int uniphier_ld20_vpll27_init(unsigned long reg_base) int uniphier_ld20_vpll27_init(unsigned long reg_base)
{ {
void __iomem *base; void __iomem *base;

2
arch/arm/mach-uniphier/clk/pll-ld11.c
View file

@ -18,6 +18,8 @@ void uniphier_ld11_pll_init(void)
uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2); /* 1500MHz -> 1600MHz */ uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2); /* 1500MHz -> 1600MHz */
uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
uniphier_ld20_sscpll_set_regi(SC_MPLLCTRL, 5);
mdelay(1); mdelay(1);
uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL); uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);

1
arch/arm/mach-uniphier/clk/pll.h
View file

@ -15,6 +15,7 @@ void uniphier_ld4_dpll_ssc_en(void);
int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
unsigned int ssc_rate, unsigned int divn); unsigned int ssc_rate, unsigned int divn);
int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base); int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi);
int uniphier_ld20_vpll27_init(unsigned long reg_base); int uniphier_ld20_vpll27_init(unsigned long reg_base);
int uniphier_ld20_dspll_init(unsigned long reg_base); int uniphier_ld20_dspll_init(unsigned long reg_base);