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net: tsec: Fix offset of MDIO registers for DM_ETH

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By convention, the eTSEC MDIO controller nodes are defined in DT at
0x2d24000 and 0x2d50000, but actually U-Boot does not touch the
interrupt portion of the register map (MDIO_IEVENTM, MDIO_IMASKM,
MDIO_EMAPM).

That leaves only the MDIO bus registers (MDIO_MIIMCFG, MDIO_MIIMCOM,
MDIO_MIIMADD, MDIO_MIIMADD, MDIO_MIIMCON, MDIO_MIIMSTAT) which start at
the 0x520 offset.

So shift the DT-defined register map by the offset of MDIO_MIIMCFG when
mapping the MDIO bus registers.

Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Vladimir Oltean 2019-07-19 00:29:54 +03:00 • committed by Joe Hershberger
parent 29db3107a5
commit bca686a4f9
2 changed files with 10 additions and 7 deletions
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13
drivers/net/tsec.c
View file

@ -801,6 +801,7 @@ int tsec_probe(struct udevice *dev)
u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE; u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
ofnode parent; ofnode parent;
const char *phy_mode; const char *phy_mode;
fdt_addr_t reg;
int ret; int ret;
pdata->iobase = (phys_addr_t)dev_read_addr(dev); pdata->iobase = (phys_addr_t)dev_read_addr(dev);
@ -817,15 +818,15 @@ int tsec_probe(struct udevice *dev)
} }
parent = ofnode_get_parent(phandle_args.node); parent = ofnode_get_parent(phandle_args.node);
if (ofnode_valid(parent)) { if (!ofnode_valid(parent)) {
int reg = ofnode_get_addr_index(parent, 0); printf("No parent node for PHY?\n");
priv->phyregs_sgmii = (struct tsec_mii_mng *)reg;
} else {
debug("No parent node for PHY?\n");
return -ENOENT; return -ENOENT;
} }
reg = ofnode_get_addr_index(parent, 0);
priv->phyregs_sgmii = (struct tsec_mii_mng *)
(reg + TSEC_MDIO_REGS_OFFSET);
ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0, ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
&phandle_args); &phandle_args);
if (ret == 0) if (ret == 0)

4
include/tsec.h
View file

@ -17,6 +17,8 @@
#include <config.h> #include <config.h>
#include <phy.h> #include <phy.h>
#define TSEC_MDIO_REGS_OFFSET 0x520
#ifndef CONFIG_DM_ETH #ifndef CONFIG_DM_ETH
#ifdef CONFIG_ARCH_LS1021A #ifdef CONFIG_ARCH_LS1021A
@ -27,7 +29,7 @@
#define TSEC_MDIO_OFFSET 0x01000 #define TSEC_MDIO_OFFSET 0x01000
#endif #endif
#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520) #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + TSEC_MDIO_REGS_OFFSET)
#define TSEC_GET_REGS(num, offset) \ #define TSEC_GET_REGS(num, offset) \
(struct tsec __iomem *)\ (struct tsec __iomem *)\