From 7ce6c8ae58d22085598007ec954d254ad4a50bf5 Mon Sep 17 00:00:00 2001
From: Vignesh Raghavendra <vigneshr@ti.com>
Date: Thu, 13 Aug 2020 14:56:15 +0530
Subject: [PATCH 01/26] arm: mach-k3: Add HyperFlash boot mode support

HBMC controller on TI K3 SoC provides MMIO access to HyperFlash similar
to legacy Parallel CFI NOR flashes. Therefore alias HyperFlash bootmode
to NOR boot to enable SPL to load next stage using NOR boot flow.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 arch/arm/mach-k3/include/mach/j721e_spl.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h
index 3fa85ca3b6..e8947917a6 100644
--- a/arch/arm/mach-k3/include/mach/j721e_spl.h
+++ b/arch/arm/mach-k3/include/mach/j721e_spl.h
@@ -15,6 +15,7 @@
 #define BOOT_DEVICE_ETHERNET		0x04
 #define BOOT_DEVICE_I2C			0x06
 #define BOOT_DEVICE_UART		0x07
+#define BOOT_DEVICE_NOR			BOOT_DEVICE_HYPERFLASH
 
 /* With BootMode B = 1 */
 #define BOOT_DEVICE_MMC2		0x10

From e85382fc53cbcd3a348815016b71af7e7542f18e Mon Sep 17 00:00:00 2001
From: Vignesh Raghavendra <vigneshr@ti.com>
Date: Thu, 13 Aug 2020 14:56:16 +0530
Subject: [PATCH 02/26] board: ti: j721e: Add support for HyperFlash detection

On J7200 SoC OSPI and HypeFlash are muxed at HW level and only one of
them can be used at any time. J7200 EVM has both HyperFlash and OSPI
flash on board. There is a user switch (SW3.1) that can be toggled to
select OSPI flash vs HyperFlash.
Read the state of this switch via wkup_gpio0_6 line and fixup the DT
nodes to select OSPI vs HyperFlash

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 board/ti/j721e/evm.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index ebaa6faa93..7925b76ab7 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -117,6 +117,13 @@ static void __maybe_unused detect_enable_hyperflash(void *blob)
 }
 #endif
 
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TARGET_J7200_A72_EVM)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	detect_enable_hyperflash(spl_image->fdt_addr);
+}
+#endif
+
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, struct bd_info *bd)
 {

From c07d06855ec32c4a4bdce4d2854bf3eb4ff49d5c Mon Sep 17 00:00:00 2001
From: Vignesh Raghavendra <vigneshr@ti.com>
Date: Thu, 13 Aug 2020 14:56:17 +0530
Subject: [PATCH 03/26] ARM: dts: k3-j7200-r5-common-proc-board: Enable
 HyperFlash

Enable HyperBus and HyperFlash to support HyperFlash boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 .../k3-j7200-common-proc-board-u-boot.dtsi    | 28 +++++++++++++
 .../arm/dts/k3-j7200-r5-common-proc-board.dts | 40 +++++++++++++++++++
 2 files changed, 68 insertions(+)

diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index 4972a7559f..0a5faa2134 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -131,3 +131,31 @@
 	dr_mode = "peripheral";
 	u-boot,dm-spl;
 };
+
+&wkup_gpio_pins_default {
+	u-boot,dm-spl;
+};
+
+&wkup_gpio0 {
+	u-boot,dm-spl;
+};
+
+&mcu_fss0_hpb0_pins_default {
+	u-boot,dm-spl;
+};
+
+&fss {
+	u-boot,dm-spl;
+};
+
+&hbmc {
+	u-boot,dm-spl;
+
+	flash@0,0 {
+		u-boot,dm-spl;
+	};
+};
+
+&hbmc_mux {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index f5e4166926..bd30284755 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -107,6 +107,31 @@
 			J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
 		>;
 	};
+
+	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
+			J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
+			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
+			J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
+			J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
+			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
+			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
+			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
+			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
+			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
+			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
+			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
+			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
+			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
+		>;
+	};
+
+	wkup_gpio_pins_default: wkup-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
+		>;
+	};
 };
 
 &main_pmx0 {
@@ -214,4 +239,19 @@
 	maximum-speed = "high-speed";
 };
 
+&hbmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
+	reg = <0x0 0x47040000 0x0 0x100>,
+	      <0x0 0x50000000 0x0 0x8000000>;
+	ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
+		 <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
+
+	flash@0,0 {
+		compatible = "cypress,hyperflash", "cfi-flash";
+		reg = <0x0 0x0 0x4000000>;
+	};
+};
+
 #include "k3-j7200-common-proc-board-u-boot.dtsi"

From f7fdeec4b45dc9cd82f0fe135a6fddd3d857a23a Mon Sep 17 00:00:00 2001
From: Vignesh Raghavendra <vigneshr@ti.com>
Date: Thu, 13 Aug 2020 14:56:18 +0530
Subject: [PATCH 04/26] configs: j7200_evm_*_defconfig: Enable HyperFlash boot
 related configs

Enable configs required to support HyperFlash boot and detection of
onboard mux switch for HyperFlash selection

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 configs/j7200_evm_a72_defconfig |  3 +++
 configs/j7200_evm_r5_defconfig  | 13 +++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 2f7f93a0b0..0845f8a45d 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -41,7 +41,9 @@ CONFIG_SPL_DMA=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_POWER_DOMAIN=y
@@ -87,6 +89,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 2908bc30c4..bd1268e9cf 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
+CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x70000
@@ -37,7 +38,9 @@ CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_POWER_DOMAIN=y
@@ -67,6 +70,8 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
@@ -87,6 +92,14 @@ CONFIG_MMC_SDHCI=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_AM654=y
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_HBMC_AM654=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_STMICRO=y

From f8d3d4d14aabee4e8959524629f72d62b6706ec0 Mon Sep 17 00:00:00 2001
From: Vignesh Raghavendra <vigneshr@ti.com>
Date: Thu, 13 Aug 2020 14:56:19 +0530
Subject: [PATCH 05/26] configs: j721e_evm.h: Add U-Boot image address for
 HyperFlash boot

Add memory mapped address location of U-Boot images in HyperFlash boot
mode.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 include/configs/j721e_evm.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index c8a76037ff..a570893378 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -23,8 +23,10 @@
 #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SPL_TEXT_BASE +	\
 					 CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
+#define CONFIG_SYS_UBOOT_BASE		0x50280000
 /* Image load address in RAM for DFU boot*/
 #else
+#define CONFIG_SYS_UBOOT_BASE		0x50080000
 /*
  * Maximum size in memory allocated to the SPL BSS. Keep it as tight as
  * possible (to allow the build to go through), as this directly affects

From 31defbd347eb9fc49c9f9e4c5615e164aee35c22 Mon Sep 17 00:00:00 2001
From: Suman Anna <s-anna@ti.com>
Date: Mon, 17 Aug 2020 16:57:34 -0500
Subject: [PATCH 06/26] arm: dts: k3-j721e-main: Configure MAIN R5FSS1 for
 Split-mode

Switch the MAIN R5FSS1 cluster to be configured for Split-mode as the
default so that two different applications can be run on each of the
R5F cores in performance mode. LockStep-mode would be available only
on SoCs efused with the appropriate bit, and Split-mode is the mode
that is available on all J721E SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/dts/k3-j721e-main.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index a285b1afa8..33db74a267 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -302,7 +302,7 @@
 
 	main_r5fss1: r5fss@5e00000 {
 		compatible = "ti,j721e-r5fss";
-		lockstep-mode = <1>;
+		lockstep-mode = <0>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,

From 3c195299a8601aef15bd24572791f02340ed690a Mon Sep 17 00:00:00 2001
From: Suman Anna <s-anna@ti.com>
Date: Mon, 17 Aug 2020 16:57:35 -0500
Subject: [PATCH 07/26] configs: j721e_evm: Add Main R5FSS1 Core1 to default
 rproc boot list

The default rproc list currently used by A72 U-Boot to boot various
remote processors include the Main R5FSS0 (Split-mode) Core1, Main
R5FSS1 (LockStep mode) Core0 and the three DSPs. The Main R5FSS1 cluster
is configured for Split mode by default in the dts now, so add the
Main R5FSS1 Core1 (rproc #5) to the default rproc boot list. This
core is now booted after the Main R5FSS1 Core0 and before the DSPs.

The order of the rprocs to boot can always be changed at runtime if
desired by overwriting the 'rproc_fw_binaries' environment variable
at U-boot prompt. Note that the R5FSS Core1 cannot be booted before
its associated Core0.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 include/configs/j721e_evm.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index a570893378..2eaa058501 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -117,6 +117,7 @@
 #define DEFAULT_RPROCS	""						\
 		"3 /lib/firmware/j7-main-r5f0_1-fw "			\
 		"4 /lib/firmware/j7-main-r5f1_0-fw "			\
+		"5 /lib/firmware/j7-main-r5f1_1-fw "			\
 		"6 /lib/firmware/j7-c66_0-fw "				\
 		"7 /lib/firmware/j7-c66_1-fw "				\
 		"8 /lib/firmware/j7-c71_0-fw "

From a9e5caf59661180424fbc4ad4736c77549bd5354 Mon Sep 17 00:00:00 2001
From: Suman Anna <s-anna@ti.com>
Date: Mon, 17 Aug 2020 16:57:36 -0500
Subject: [PATCH 08/26] env: ti: j721e-evm: Limit scope of rproc env variables
 used by R5 SPL

The commit 316c927135d6 ("include: configs: j721e_evm: Add env variables
for mcu_r5fss0_core0 & main_r5fss0_core0") added four different new env
variables 'addr_mainr5f0_0load', 'name_mainr5f0_0fw', 'addr_mcur5f0_0load'
and 'name_mcur5f0_0fw' to the generic environment, but these are only
needed and used in R5 SPL for early-booting the MCU R5FSS0 and Main
R5FSS0 Core0 on J721E SoCs.

These are not really needed for A72 U-Boot, so limit the scope of
these variables only to R5 SPL. While at this, also fix the loadaddr
variable values to include the hex prefix like with other such env
variables.

Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
---
 include/configs/j721e_evm.h | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index 2eaa058501..15c34e19bf 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -83,16 +83,23 @@
 	"uuid_disk=${uuid_gpt_disk};" \
 	"name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
 
+#ifdef CONFIG_SYS_K3_SPL_ATF
+#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC				\
+	"addr_mainr5f0_0load=0x88000000\0"				\
+	"name_mainr5f0_0fw=/lib/firmware/j7-main-r5f0_0-fw\0"		\
+	"addr_mcur5f0_0load=0x89000000\0"				\
+	"name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0"
+#else
+#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC ""
+#endif /* CONFIG_SYS_K3_SPL_ATF */
+
 /* U-Boot MMC-specific configuration */
 #define EXTRA_ENV_J721E_BOARD_SETTINGS_MMC				\
 	"boot=mmc\0"							\
 	"mmcdev=1\0"							\
 	"bootpart=1:2\0"						\
 	"bootdir=/boot\0"						\
-	"addr_mainr5f0_0load=88000000\0"					\
-	"name_mainr5f0_0fw=/lib/firmware/j7-main-r5f0_0-fw\0"		\
-	"addr_mcur5f0_0load=89000000\0"					\
-	"name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0"		\
+	EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC				\
 	"rd_spec=-\0"							\
 	"init_mmc=run args_all args_mmc\0"				\
 	"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \

From ca569e9bbe8ecc3bf2d7494e0f0b9793a9ac4644 Mon Sep 17 00:00:00 2001
From: Suman Anna <s-anna@ti.com>
Date: Mon, 17 Aug 2020 18:15:07 -0500
Subject: [PATCH 09/26] dt-bindings: remoteproc: k3-r5f: Update bindings for
 J7200 SoCs

The K3 J7200 SoCs have two dual-core Arm R5F clusters/subsystems, with
2 R5F cores each, one in each of the MCU and MAIN voltage domains.

These clusters are a revised version compared to those present on
J721E SoCs. Update the K3 R5F remoteproc bindings with the compatible
info relevant to these R5F clusters/subsystems on K3 J7200 SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt b/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt
index c2fa6e8344..5708c23017 100644
--- a/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt
+++ b/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt
@@ -25,6 +25,8 @@ The following are the mandatory properties:
 			                       K3 AM65x SoCs
 			    "ti,j721e-r5fss" for R5F clusters/subsystems on
 			                       K3 J721E SoCs
+			    "ti,j7200-r5fss" for R5F clusters/subsystems on
+			                       K3 J7200 SoCs
 - power-domains:	Should contain a phandle to a PM domain provider node
 			and an args specifier containing the R5FSS device id
 			value. This property is as per the binding,
@@ -56,6 +58,7 @@ The following are the mandatory properties:
 - compatible:		Should be one of the following,
 			    "ti,am654-r5f" for the R5F cores in K3 AM65x SoCs
 			    "ti,j721e-r5f" for the R5F cores in K3 J721E SOCs
+			    "ti,j7200-r5f" for the R5F cores in K3 J7200 SOCs
 - reg:			Should contain an entry for each value in 'reg-names'.
 			Each entry should have the memory region's start address
 			and the size of the region, the representation matching
@@ -79,7 +82,7 @@ The following are the mandatory properties:
 			specifier. Please refer to the following reset bindings
 			for the reset argument specifier,
 			Documentation/devicetree/bindings/reset/ti,sci-reset.txt
-			    for AM65x and J721E SoCs
+			    for AM65x, J721E and J7200 SoCs
 
 Optional properties:
 --------------------

From 6aa3b740c3e04256d5e22dbae8bc5a802aa3b9b9 Mon Sep 17 00:00:00 2001
From: Suman Anna <s-anna@ti.com>
Date: Mon, 17 Aug 2020 18:15:08 -0500
Subject: [PATCH 10/26] remoteproc: k3-r5: Add support for J7200 R5Fs

The K3 J7200 SoC family has a revised R5F sub-system and contains a
subset of the R5F clusters present on J721E SoCs. The integration of
these clusters is very much similar to J721E SoCs otherwise.

The revised IP has the following two new features:
 1. TCMs are auto-initialized during module power-up, and the behavior
    is programmable through a MMR bit controlled by System Firmware.
 2. The LockStep-mode allows the Core1 TCMs to be combined with the
    Core0 TCMs effectively doubling the amount of TCMs available.
    The LockStep-mode on previous SoCs could only use the Core0 TCMs.
    This combined TCMs appear contiguous at the respective Core0 TCM
    addresses.

Add the support to these clusters in the K3 R5F remoteproc driver
using J7200 specific compatibles and revised logic accounting for
the above IP features/differences.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 drivers/remoteproc/ti_k3_r5f_rproc.c | 99 +++++++++++++++++++++++++---
 1 file changed, 89 insertions(+), 10 deletions(-)

diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c
index 1a7f1f8a00..8e21a38be7 100644
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@@ -2,8 +2,9 @@
 /*
  * Texas Instruments' K3 R5 Remoteproc driver
  *
- * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
  *	Lokesh Vutla <lokeshvutla@ti.com>
+ *	Suman Anna <s-anna@ti.com>
  */
 
 #include <common.h>
@@ -37,6 +38,8 @@
 #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN			0x00001000
 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN			0x00002000
 #define PROC_BOOT_CFG_FLAG_GEN_IGN_BOOTVECTOR		0x10000000
+/* Available from J7200 SoCs onwards */
+#define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS		0x00004000
 
 /* R5 TI-SCI Processor Control Flags */
 #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT		0x00000001
@@ -54,6 +57,16 @@ enum cluster_mode {
 	CLUSTER_MODE_LOCKSTEP,
 };
 
+/**
+ * struct k3_r5f_ip_data - internal data structure used for IP variations
+ * @tcm_is_double: flag to denote the larger unified TCMs in certain modes
+ * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC
+ */
+struct k3_r5f_ip_data {
+	bool tcm_is_double;
+	bool tcm_ecc_autoinit;
+};
+
 /**
  * struct k3_r5_mem - internal memory structure
  * @cpu_addr: MPU virtual address of the memory region
@@ -74,6 +87,7 @@ struct k3_r5f_mem {
  * @cluster: pointer to the parent cluster.
  * @reset: reset control handle
  * @tsp: TI-SCI processor control handle
+ * @ipdata: cached pointer to R5F IP specific feature data
  * @mem: Array of available internal memories
  * @num_mem: Number of available memories
  * @atcm_enable: flag to control ATCM enablement
@@ -86,6 +100,7 @@ struct k3_r5f_core {
 	struct k3_r5f_cluster *cluster;
 	struct reset_ctl reset;
 	struct ti_sci_proc tsp;
+	struct k3_r5f_ip_data *ipdata;
 	struct k3_r5f_mem *mem;
 	int num_mems;
 	u32 atcm_enable;
@@ -257,6 +272,18 @@ static int k3_r5f_core_sanity_check(struct k3_r5f_core *core)
 	return 0;
 }
 
+/* Zero out TCMs so that ECC can be effective on all TCM addresses */
+void k3_r5f_init_tcm_memories(struct k3_r5f_core *core, bool auto_inited)
+{
+	if (core->ipdata->tcm_ecc_autoinit && auto_inited)
+		return;
+
+	if (core->atcm_enable)
+		memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);
+	if (core->btcm_enable)
+		memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);
+}
+
 /**
  * k3_r5f_load() - Load up the Remote processor image
  * @dev:	rproc device pointer
@@ -268,7 +295,9 @@ static int k3_r5f_core_sanity_check(struct k3_r5f_core *core)
 static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size)
 {
 	struct k3_r5f_core *core = dev_get_priv(dev);
-	u32 boot_vector;
+	u64 boot_vector;
+	u32 ctrl, sts, cfg = 0;
+	bool mem_auto_init;
 	int ret;
 
 	dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size);
@@ -281,6 +310,12 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size)
 	if (ret)
 		return ret;
 
+	ret = ti_sci_proc_get_status(&core->tsp, &boot_vector, &cfg, &ctrl,
+				     &sts);
+	if (ret)
+		return ret;
+	mem_auto_init = !(cfg & PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS);
+
 	ret = k3_r5f_prepare(dev);
 	if (ret) {
 		dev_err(dev, "R5f prepare failed for core %d\n",
@@ -288,11 +323,7 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size)
 		goto proc_release;
 	}
 
-	/* Zero out TCMs so that ECC can be effective on all TCM addresses */
-	if (core->atcm_enable)
-		memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);
-	if (core->btcm_enable)
-		memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);
+	k3_r5f_init_tcm_memories(core, mem_auto_init);
 
 	ret = rproc_elf_load_image(dev, addr, size);
 	if (ret < 0) {
@@ -302,7 +333,7 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size)
 
 	boot_vector = rproc_elf_get_boot_addr(dev, addr);
 
-	dev_dbg(dev, "%s: Boot vector = 0x%x\n", __func__, boot_vector);
+	dev_dbg(dev, "%s: Boot vector = 0x%llx\n", __func__, boot_vector);
 
 	ret = ti_sci_proc_set_config(&core->tsp, boot_vector, 0, 0);
 
@@ -657,6 +688,8 @@ static int k3_r5f_of_to_priv(struct k3_r5f_core *core)
 		return ret;
 	}
 
+	core->ipdata = (struct k3_r5f_ip_data *)dev_get_driver_data(core->dev);
+
 	return 0;
 }
 
@@ -702,6 +735,38 @@ static int k3_r5f_core_of_get_memories(struct k3_r5f_core *core)
 	return 0;
 }
 
+/*
+ * Each R5F core within a typical R5FSS instance has a total of 64 KB of TCMs,
+ * split equally into two 32 KB banks between ATCM and BTCM. The TCMs from both
+ * cores are usable in Split-mode, but only the Core0 TCMs can be used in
+ * LockStep-mode. The newer revisions of the R5FSS IP maximizes these TCMs by
+ * leveraging the Core1 TCMs as well in certain modes where they would have
+ * otherwise been unusable (Eg: LockStep-mode on J7200 SoCs). This is done by
+ * making a Core1 TCM visible immediately after the corresponding Core0 TCM.
+ * The SoC memory map uses the larger 64 KB sizes for the Core0 TCMs, and the
+ * dts representation reflects this increased size on supported SoCs. The Core0
+ * TCM sizes therefore have to be adjusted to only half the original size in
+ * Split mode.
+ */
+static void k3_r5f_core_adjust_tcm_sizes(struct k3_r5f_core *core)
+{
+	struct k3_r5f_cluster *cluster = core->cluster;
+
+	if (cluster->mode == CLUSTER_MODE_LOCKSTEP)
+		return;
+
+	if (!core->ipdata->tcm_is_double)
+		return;
+
+	if (core == cluster->cores[0]) {
+		core->mem[0].size /= 2;
+		core->mem[1].size /= 2;
+
+		dev_dbg(core->dev, "adjusted TCM sizes, ATCM = 0x%zx BTCM = 0x%zx\n",
+			core->mem[0].size, core->mem[1].size);
+	}
+}
+
 /**
  * k3_r5f_probe() - Basic probe
  * @dev:	corresponding k3 remote processor device
@@ -755,6 +820,8 @@ static int k3_r5f_probe(struct udevice *dev)
 		return ret;
 	}
 
+	k3_r5f_core_adjust_tcm_sizes(core);
+
 	dev_dbg(dev, "Remoteproc successfully probed\n");
 
 	return 0;
@@ -771,9 +838,20 @@ static int k3_r5f_remove(struct udevice *dev)
 	return 0;
 }
 
+static const struct k3_r5f_ip_data k3_data = {
+	.tcm_is_double = false,
+	.tcm_ecc_autoinit = false,
+};
+
+static const struct k3_r5f_ip_data j7200_data = {
+	.tcm_is_double = true,
+	.tcm_ecc_autoinit = true,
+};
+
 static const struct udevice_id k3_r5f_rproc_ids[] = {
-	{ .compatible = "ti,am654-r5f"},
-	{ .compatible = "ti,j721e-r5f"},
+	{ .compatible = "ti,am654-r5f", .data = (ulong)&k3_data, },
+	{ .compatible = "ti,j721e-r5f", .data = (ulong)&k3_data, },
+	{ .compatible = "ti,j7200-r5f", .data = (ulong)&j7200_data, },
 	{}
 };
 
@@ -810,6 +888,7 @@ static int k3_r5f_cluster_probe(struct udevice *dev)
 static const struct udevice_id k3_r5fss_ids[] = {
 	{ .compatible = "ti,am654-r5fss"},
 	{ .compatible = "ti,j721e-r5fss"},
+	{ .compatible = "ti,j7200-r5fss"},
 	{}
 };
 

From 7873e9df8fc47fb2532112e7fe4ad546f7a46fcb Mon Sep 17 00:00:00 2001
From: Suman Anna <s-anna@ti.com>
Date: Mon, 17 Aug 2020 18:15:09 -0500
Subject: [PATCH 11/26] armv8: K3: j7200: Add custom MMU support

The A72 U-Boot code can load and boot a number of the available
R5FSS Cores on the J7200 SoC. Change the memory attributes for the
DDR regions used by the remote processors so that the cores can see
and execute the proper code.

The J7200 SoC has less number of remote processors compared to J721E,
so use less memory for the remote processors. So, a separate table
based on the current J721E table is added for J7200 SoCs, and selected
using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/mach-k3/arm64-mmu.c | 59 +++++++++++++++++++++++++++++++++++-
 1 file changed, 58 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index 95f830b7ff..a0da3df593 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -2,8 +2,9 @@
 /*
  * K3: ARM64 MMU setup
  *
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
  *	Lokesh Vutla <lokeshvutla@ti.com>
+ *	Suman Anna <s-anna@ti.com>
  * (This file is derived from arch/arm/mach-zynqmp/cpu.c)
  *
  */
@@ -66,6 +67,8 @@ struct mm_region *mem_map = am654_mem_map;
 #endif /* CONFIG_SOC_K3_AM6 */
 
 #ifdef CONFIG_SOC_K3_J721E
+
+#ifdef CONFIG_TARGET_J721E_A72_EVM
 /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
 #define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 6)
 
@@ -122,4 +125,58 @@ struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
 };
 
 struct mm_region *mem_map = j721e_mem_map;
+#endif /* CONFIG_TARGET_J721E_A72_EVM */
+
+#ifdef CONFIG_TARGET_J7200_A72_EVM
+#define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 5)
+
+/* ToDo: Add 64bit IO */
+struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x20000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xa0000000UL,
+		.phys = 0xa0000000UL,
+		.size = 0x04800000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+			 PTE_BLOCK_NON_SHARE
+	}, {
+		.virt = 0xa4800000UL,
+		.phys = 0xa4800000UL,
+		.size = 0x5b800000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x880000000UL,
+		.phys = 0x880000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x500000000UL,
+		.phys = 0x500000000UL,
+		.size = 0x400000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = j7200_mem_map;
+#endif /* CONFIG_TARGET_J7200_A72_EVM */
+
 #endif /* CONFIG_SOC_K3_J721E */

From 10c4de02f0f0e424d196a47fb933f2d619966cfe Mon Sep 17 00:00:00 2001
From: Suman Anna <s-anna@ti.com>
Date: Mon, 17 Aug 2020 18:15:10 -0500
Subject: [PATCH 12/26] arm: dts: k3-j7200-mcu: Add MCU domain R5F cluster node

The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.

Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with
the ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/dts/k3-j7200-common-proc-board.dts |  5 +++
 arch/arm/dts/k3-j7200-mcu-wakeup.dtsi       | 40 +++++++++++++++++++++
 2 files changed, 45 insertions(+)

diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts
index 3f1d03c960..b485889525 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -13,6 +13,11 @@
 		stdout-path = "serial2:115200n8";
 		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
 	};
+
+	aliases {
+		remoteproc0 = &mcu_r5fss0_core0;
+		remoteproc1 = &mcu_r5fss0_core1;
+	};
 };
 
 &wkup_pmx0 {
diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
index 4c899c8aca..75c0c8597d 100644
--- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
@@ -269,4 +269,44 @@
 			ti,cpts-periodic-outputs = <2>;
 		};
 	};
+
+	mcu_r5fss0: r5fss@41000000 {
+		compatible = "ti,j7200-r5fss";
+		lockstep-mode = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x41000000 0x00 0x41000000 0x20000>,
+			 <0x41400000 0x00 0x41400000 0x20000>;
+		power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
+
+		mcu_r5fss0_core0: r5f@41000000 {
+			compatible = "ti,j7200-r5f";
+			reg = <0x41000000 0x00010000>,
+			      <0x41010000 0x00010000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <250>;
+			ti,sci-proc-ids = <0x01 0xff>;
+			resets = <&k3_reset 250 1>;
+			firmware-name = "j7200-mcu-r5f0_0-fw";
+			atcm-enable = <1>;
+			btcm-enable = <1>;
+			loczrama = <1>;
+		};
+
+		mcu_r5fss0_core1: r5f@41400000 {
+			compatible = "ti,j7200-r5f";
+			reg = <0x41400000 0x00008000>,
+			      <0x41410000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <251>;
+			ti,sci-proc-ids = <0x02 0xff>;
+			resets = <&k3_reset 251 1>;
+			firmware-name = "j7200-mcu-r5f0_1-fw";
+			atcm-enable = <1>;
+			btcm-enable = <1>;
+			loczrama = <1>;
+		};
+	};
 };

From 3f7e032f70da685f8b5e76c0ad7577033e996044 Mon Sep 17 00:00:00 2001
From: Suman Anna <s-anna@ti.com>
Date: Mon, 17 Aug 2020 18:15:11 -0500
Subject: [PATCH 13/26] arm: dts: k3-j7200-main: Add MAIN domain R5F cluster
 nodes

The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.

Add the DT node for the MAIN domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in Split-mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/dts/k3-j7200-common-proc-board.dts |  2 ++
 arch/arm/dts/k3-j7200-main.dtsi             | 40 +++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts
index b485889525..cc3d933cbb 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -17,6 +17,8 @@
 	aliases {
 		remoteproc0 = &mcu_r5fss0_core0;
 		remoteproc1 = &mcu_r5fss0_core1;
+		remoteproc2 = &main_r5fss0_core0;
+		remoteproc3 = &main_r5fss0_core1;
 	};
 };
 
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index aaa1fdd5a3..c25f03cf23 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -340,4 +340,44 @@
 			dr_mode = "otg";
 		};
 	};
+
+	main_r5fss0: r5fss@5c00000 {
+		compatible = "ti,j7200-r5fss";
+		lockstep-mode = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
+			 <0x5d00000 0x00 0x5d00000 0x20000>;
+		power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
+
+		main_r5fss0_core0: r5f@5c00000 {
+			compatible = "ti,j7200-r5f";
+			reg = <0x5c00000 0x00010000>,
+			      <0x5c10000 0x00010000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <245>;
+			ti,sci-proc-ids = <0x06 0xFF>;
+			resets = <&k3_reset 245 1>;
+			firmware-name = "j7200-main-r5f0_0-fw";
+			atcm-enable = <1>;
+			btcm-enable = <1>;
+			loczrama = <1>;
+		};
+
+		main_r5fss0_core1: r5f@5d00000 {
+			compatible = "ti,j7200-r5f";
+			reg = <0x5d00000 0x00008000>,
+			      <0x5d10000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <246>;
+			ti,sci-proc-ids = <0x07 0xFF>;
+			resets = <&k3_reset 246 1>;
+			firmware-name = "j7200-main-r5f0_1-fw";
+			atcm-enable = <1>;
+			btcm-enable = <1>;
+			loczrama = <1>;
+		};
+	};
 };

From c091bb049973ae73cb8d63b1bb4cf04047cd27da Mon Sep 17 00:00:00 2001
From: Suman Anna <s-anna@ti.com>
Date: Mon, 17 Aug 2020 18:15:12 -0500
Subject: [PATCH 14/26] env: ti: j721e-evm: Update rproc_fw_binaries env
 variable for J7200

The J7200 SoCs have different number of remote processors, but reuse
the same environment settings as the J721E SoCs. The current env
variable rproc_fw_binaries is geared towards J721E SoCs and is
incorrect for J7200 SoCs. Please see the logic originally added in
commit 0b4ab9c9a754 ("env: ti: j721e-evm: Add support to boot rprocs
including R5Fs and DSPs").

Fix this by defining the DEFAULT_RPROCS macro appropriately using
the corresponding TARGET_EVM Kconfig symbol. This macro is used by
the 'rproc_fw_binaries' env variable in the common remoteproc env
header file k3_rproc.h.

The list of R5F cores to be started before loading and booting the
Linux kernel are as follows, and mainly comprises of the Main R5FSS0
cores in this order:
   Main R5FSS0 (Split) Core0 : 2 /lib/firmware/j7200-main-r5f0_0-fw
   Main R5FSS0 (Split) Core1 : 3 /lib/firmware/j7200-main-r5f0_1-fw

The MCU R5FSS0 is in LockStep mode and is expected to be booted by
R5 SPL, so it is not included in the list. The order of rprocs to
boot cannot be really modified as only the Main R5FSS0 cores are
involved and Core0 has to be booted first always before the
corresponding Core1.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 include/configs/j721e_evm.h | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index 15c34e19bf..9988c43641 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -2,7 +2,7 @@
 /*
  * Configuration header file for K3 J721E EVM
  *
- * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
  *	Lokesh Vutla <lokeshvutla@ti.com>
  */
 
@@ -118,9 +118,14 @@
 		"${bootdir}/${name_fit}\0"				\
 	"partitions=" PARTS_DEFAULT
 
+/* Set the default list of remote processors to boot */
+#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
 #ifdef DEFAULT_RPROCS
 #undef DEFAULT_RPROCS
 #endif
+#endif
+
+#ifdef CONFIG_TARGET_J721E_A72_EVM
 #define DEFAULT_RPROCS	""						\
 		"3 /lib/firmware/j7-main-r5f0_1-fw "			\
 		"4 /lib/firmware/j7-main-r5f1_0-fw "			\
@@ -128,6 +133,13 @@
 		"6 /lib/firmware/j7-c66_0-fw "				\
 		"7 /lib/firmware/j7-c66_1-fw "				\
 		"8 /lib/firmware/j7-c71_0-fw "
+#endif /* CONFIG_TARGET_J721E_A72_EVM */
+
+#ifdef CONFIG_TARGET_J7200_A72_EVM
+#define DEFAULT_RPROCS ""						\
+		"2 /lib/firmware/j7200-main-r5f0_0-fw "			\
+		"3 /lib/firmware/j7200-main-r5f0_1-fw "
+#endif /* CONFIG_TARGET_J7200_A72_EVM */
 
 /* set default dfu_bufsiz to 128KB (sector size of OSPI) */
 #define EXTRA_ENV_DFUARGS \

From d529e4a435b7ac30bc2d1d036d9f4f3bbff615f8 Mon Sep 17 00:00:00 2001
From: Suman Anna <s-anna@ti.com>
Date: Mon, 17 Aug 2020 18:15:13 -0500
Subject: [PATCH 15/26] configs: j7200_evm_a72: Enable R5F remoteproc driver

The J7200 SoCs has two R5F sub-systems. Enable the TI K3
R5F remoteproc driver and the remoteproc command options
to allow these R5F processors to be booted from A72 U-Boot.

The Kconfigs are added using savedefconfig.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 configs/j7200_evm_a72_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 0845f8a45d..b505275836 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -63,6 +63,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_UFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
@@ -143,6 +144,7 @@ CONFIG_POWER_DOMAIN=y
 CONFIG_TI_SCI_POWER_DOMAIN=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_SCSI=y

From f61687df0f6d8f4157664b1cc6c7e37108a2d138 Mon Sep 17 00:00:00 2001
From: Suman Anna <s-anna@ti.com>
Date: Mon, 17 Aug 2020 18:15:14 -0500
Subject: [PATCH 16/26] configs: j7200_evm_a72: Enhance bootcmd to start
 remoteprocs

The A72 U-boot can support early booting of any of the Main or MCU R5F
remote processors from U-boot prompt to achieve various system usecases
before booting the Linux kernel. Update the default BOOTCOMMAND to provide
an automatic and easier way to start various remote processors through
added environment variables.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 configs/j7200_evm_a72_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index b505275836..7c900b1d2e 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -30,7 +30,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 # CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y

From 615d10f736e850c073a17b2f64fd08c7f5b32fe2 Mon Sep 17 00:00:00 2001
From: Suman Anna <s-anna@ti.com>
Date: Tue, 18 Aug 2020 14:09:43 -0500
Subject: [PATCH 17/26] env: ti: j721e-evm: Update R5 SPL rproc env variables
 for J7200

The R5 SPL on J7200 SoCs will be limited to booting just the
MCU R5FSS0 R5F core in LockStep-mode at present, so add the
two required environment variables 'addr_mcur5f0_0load' and
'name_mcur5f0_0fw' that are needed by the R5 SPL early-boot
logic. The firmware name used is also different from that on
J721E SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 include/configs/j721e_evm.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index 9988c43641..1b47e18b2f 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -84,11 +84,17 @@
 	"name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
 
 #ifdef CONFIG_SYS_K3_SPL_ATF
+#if defined(CONFIG_TARGET_J721E_R5_EVM)
 #define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC				\
 	"addr_mainr5f0_0load=0x88000000\0"				\
 	"name_mainr5f0_0fw=/lib/firmware/j7-main-r5f0_0-fw\0"		\
 	"addr_mcur5f0_0load=0x89000000\0"				\
 	"name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0"
+#elif defined(CONFIG_TARGET_J7200_R5_EVM)
+#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC				\
+	"addr_mcur5f0_0load=0x89000000\0"				\
+	"name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw\0"
+#endif /* CONFIG_TARGET_J721E_R5_EVM */
 #else
 #define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC ""
 #endif /* CONFIG_SYS_K3_SPL_ATF */

From 70377b7279d64edb759db5371052281051b1649d Mon Sep 17 00:00:00 2001
From: Suman Anna <s-anna@ti.com>
Date: Tue, 18 Aug 2020 14:09:44 -0500
Subject: [PATCH 18/26] arm: dts: k3-j7200-r5: Add fs_loader node

Add a generic fs_loader node to the K3 J7200 R5 common board dts
file and use it as the chosen firmware-loader so that it can be
used for loading various firmwares from a boot media/filesystem
in R5 SPL on K3 J7200 EVM.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index bd30284755..db63d93777 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -18,6 +18,12 @@
 	chosen {
 		stdout-path = &main_uart0;
 		tick-timer = &timer1;
+		firmware-loader = &fs_loader0;
+	};
+
+	fs_loader0: fs_loader@0 {
+		u-boot,dm-pre-reloc;
+		compatible = "u-boot,fs-loader";
 	};
 
 	a72_0: a72@0 {

From a0549cc95222f62e41858df61702a710aa8a9bca Mon Sep 17 00:00:00 2001
From: Suman Anna <s-anna@ti.com>
Date: Tue, 18 Aug 2020 14:09:45 -0500
Subject: [PATCH 19/26] configs: j7200_evm_r5: Enable FS_LOADER

Enable the FS_LOADER and associated configs in the j7200_evm_r5_defconfig
so that the R5 SPL can support the loading of firmware files from a boot
media/file system.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 configs/j7200_evm_r5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index bd1268e9cf..3820fc508b 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -86,6 +86,7 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
+CONFIG_FS_LOADER=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_SDHCI=y

From 42b7aebe4ab47d7d981572d15d9bba999007b2ac Mon Sep 17 00:00:00 2001
From: "Matwey V. Kornilov" <matwey.kornilov@gmail.com>
Date: Mon, 24 Aug 2020 21:00:32 +0300
Subject: [PATCH 20/26] ti: Use devtype=mmc instead of setenv devtype mmc

If devtype variable is setted via setenv, then the following devtype=X style is
ignored. Currently, many u-boot commands use devtype variable in the latter
manner:

    mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi

Use devtype=mmc instead of setenv devtype mmc to avoid bugs with booting from
another devtype.

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
---
 include/environment/ti/mmc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h
index 1c8e49a8b3..b86c8dc7a4 100644
--- a/include/environment/ti/mmc.h
+++ b/include/environment/ti/mmc.h
@@ -57,7 +57,7 @@
 		"fi;\0" \
 	"mmcboot=mmc dev ${mmcdev}; " \
 		"devnum=${mmcdev}; " \
-		"setenv devtype mmc; " \
+		"devtype=mmc; " \
 		"if mmc rescan; then " \
 			"echo SD/MMC found on device ${mmcdev};" \
 			"if run loadimage; then " \

From 8c444c184c36dfa314a2a500349785f58c8a8d24 Mon Sep 17 00:00:00 2001
From: "Matwey V. Kornilov" <matwey.kornilov@gmail.com>
Date: Mon, 24 Aug 2020 21:00:33 +0300
Subject: [PATCH 21/26] am335x_evm: Allow booting from usb-storage device

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
---
 include/configs/am335x_evm.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 9c4ef369c5..103c046137 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -66,6 +66,12 @@
 #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
 	#devtypel #instance " "
 
+#if CONFIG_IS_ENABLED(CMD_USB)
+# define BOOT_TARGET_USB(func) func(USB, usb, 0)
+#else
+# define BOOT_TARGET_USB(func)
+#endif
+
 #if CONFIG_IS_ENABLED(CMD_PXE)
 # define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
 #else
@@ -84,6 +90,7 @@
 	func(MMC, mmc, 1) \
 	func(LEGACY_MMC, legacy_mmc, 1) \
 	func(NAND, nand, 0) \
+	BOOT_TARGET_USB(func) \
 	BOOT_TARGET_PXE(func) \
 	BOOT_TARGET_DHCP(func)
 

From 38e6ddc4d7fb215a15b1ff5b3ebd72ee3cc009e7 Mon Sep 17 00:00:00 2001
From: Faiz Abbas <faiz_abbas@ti.com>
Date: Mon, 14 Sep 2020 12:11:13 +0530
Subject: [PATCH 22/26] arm: dts: am335x-icev2: Add spi node

Add spi and spi nor flash nodes for am335x-icev2.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
---
 arch/arm/dts/am335x-icev2.dts | 50 +++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts
index 37484cb6f5..2a1b3a53e9 100644
--- a/arch/arm/dts/am335x-icev2.dts
+++ b/arch/arm/dts/am335x-icev2.dts
@@ -436,3 +436,53 @@
 		reg = <3>;
 	};
 };
+
+&spi0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins_default>;
+
+	sn65hvs882@1 {
+		compatible = "pisosr-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+
+		reg = <1>;
+		spi-max-frequency = <1000000>;
+		spi-cpol;
+	};
+
+	spi_nor: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q64", "jedec,spi-nor";
+		spi-max-frequency = <80000000>;
+		m25p,fast-read;
+		reg = <0>;
+
+		partition@0 {
+			label = "u-boot-spl";
+			reg = <0x0 0x80000>;
+			read-only;
+		};
+
+		partition@1 {
+			label = "u-boot";
+			reg = <0x80000 0x100000>;
+			read-only;
+		};
+
+		partition@2 {
+			label = "u-boot-env";
+			reg = <0x180000 0x20000>;
+			read-only;
+		};
+
+		partition@3 {
+			label = "misc";
+			reg = <0x1A0000 0x660000>;
+		};
+	};
+};

From 280af011563574844fa3c20acd2cbbd7ee669da8 Mon Sep 17 00:00:00 2001
From: Faiz Abbas <faiz_abbas@ti.com>
Date: Mon, 14 Sep 2020 12:11:14 +0530
Subject: [PATCH 23/26] spi: spi-uclass: Block dm_scan_fdt_dev with OF_CONTROL
 to prevent build failures

There are devices which don't use OF_CONTROL or OF_PLATDATA but instead
rely on statically defined platdata. Block dm_scan_fdt_dev() with both
configs to avoid build failures under this condition.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/spi/spi-uclass.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index cffd9cf0b0..55a8eed890 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -497,7 +497,7 @@ UCLASS_DRIVER(spi) = {
 	.id		= UCLASS_SPI,
 	.name		= "spi",
 	.flags		= DM_UC_FLAG_SEQ_ALIAS,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 	.post_bind	= dm_scan_fdt_dev,
 #endif
 	.post_probe	= spi_post_probe,

From 41cf3cb39ddbb8a0b892781388e1054653d33ed1 Mon Sep 17 00:00:00 2001
From: Faiz Abbas <faiz_abbas@ti.com>
Date: Mon, 14 Sep 2020 12:11:15 +0530
Subject: [PATCH 24/26] arm: mach-omap2: am33xx: Add device structure for spi

Add platform data and a device structure for the spi device
present on am335x-icev2. This requires moving all omap3_spi
platform data structures and symbols to an omap3_spi.h so that
the board file can access them.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
---
 arch/arm/mach-omap2/am33xx/board.c | 18 +++++++
 drivers/spi/omap3_spi.c            | 70 +--------------------------
 include/configs/am335x_evm.h       |  2 -
 include/omap3_spi.h                | 78 ++++++++++++++++++++++++++++++
 4 files changed, 97 insertions(+), 71 deletions(-)
 create mode 100644 include/omap3_spi.h

diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index a7b56b6bb3..2888390d24 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -14,6 +14,7 @@
 #include <init.h>
 #include <net.h>
 #include <ns16550.h>
+#include <omap3_spi.h>
 #include <spl.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
@@ -49,6 +50,12 @@
 #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET		0xDC
 #define AM43XX_RDWRLVLFULL_START			0x80000000
 
+/* SPI flash. */
+#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
+#define AM33XX_SPI0_BASE	0x48030000
+#define AM33XX_SPI0_OFFSET	(AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
@@ -142,6 +149,17 @@ U_BOOT_DEVICES(am33xx_gpios) = {
 #endif
 };
 #endif
+#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct omap3_spi_plat omap3_spi_pdata = {
+	.regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
+	.pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
+};
+
+U_BOOT_DEVICE(am33xx_spi) = {
+	.name = "omap3_spi",
+	.platdata = &omap3_spi_pdata,
+};
+#endif
 #endif
 
 #if !CONFIG_IS_ENABLED(DM_GPIO)
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index fbf9575851..fb1cf360fc 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -22,82 +22,14 @@
 #include <malloc.h>
 #include <asm/io.h>
 #include <linux/bitops.h>
+#include <omap3_spi.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define OMAP4_MCSPI_REG_OFFSET	0x100
-
 struct omap2_mcspi_platform_config {
 	unsigned int regs_offset;
 };
 
-/* per-register bitmasks */
-#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
-#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
-#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE	BIT(0)
-#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
-
-#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
-
-#define OMAP3_MCSPI_MODULCTRL_SINGLE	BIT(0)
-#define OMAP3_MCSPI_MODULCTRL_MS	BIT(2)
-#define OMAP3_MCSPI_MODULCTRL_STEST	BIT(3)
-
-#define OMAP3_MCSPI_CHCONF_PHA		BIT(0)
-#define OMAP3_MCSPI_CHCONF_POL		BIT(1)
-#define OMAP3_MCSPI_CHCONF_CLKD_MASK	GENMASK(5, 2)
-#define OMAP3_MCSPI_CHCONF_EPOL		BIT(6)
-#define OMAP3_MCSPI_CHCONF_WL_MASK	GENMASK(11, 7)
-#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	BIT(12)
-#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	BIT(13)
-#define OMAP3_MCSPI_CHCONF_TRM_MASK	GENMASK(13, 12)
-#define OMAP3_MCSPI_CHCONF_DMAW		BIT(14)
-#define OMAP3_MCSPI_CHCONF_DMAR		BIT(15)
-#define OMAP3_MCSPI_CHCONF_DPE0		BIT(16)
-#define OMAP3_MCSPI_CHCONF_DPE1		BIT(17)
-#define OMAP3_MCSPI_CHCONF_IS		BIT(18)
-#define OMAP3_MCSPI_CHCONF_TURBO	BIT(19)
-#define OMAP3_MCSPI_CHCONF_FORCE	BIT(20)
-
-#define OMAP3_MCSPI_CHSTAT_RXS		BIT(0)
-#define OMAP3_MCSPI_CHSTAT_TXS		BIT(1)
-#define OMAP3_MCSPI_CHSTAT_EOT		BIT(2)
-
-#define OMAP3_MCSPI_CHCTRL_EN		BIT(0)
-#define OMAP3_MCSPI_CHCTRL_DIS		(0 << 0)
-
-#define OMAP3_MCSPI_WAKEUPENABLE_WKEN	BIT(0)
-#define MCSPI_PINDIR_D0_IN_D1_OUT	0
-#define MCSPI_PINDIR_D0_OUT_D1_IN	1
-
-#define OMAP3_MCSPI_MAX_FREQ		48000000
-#define SPI_WAIT_TIMEOUT		10
-
-/* OMAP3 McSPI registers */
-struct mcspi_channel {
-	unsigned int chconf;		/* 0x2C, 0x40, 0x54, 0x68 */
-	unsigned int chstat;		/* 0x30, 0x44, 0x58, 0x6C */
-	unsigned int chctrl;		/* 0x34, 0x48, 0x5C, 0x70 */
-	unsigned int tx;		/* 0x38, 0x4C, 0x60, 0x74 */
-	unsigned int rx;		/* 0x3C, 0x50, 0x64, 0x78 */
-};
-
-struct mcspi {
-	unsigned char res1[0x10];
-	unsigned int sysconfig;		/* 0x10 */
-	unsigned int sysstatus;		/* 0x14 */
-	unsigned int irqstatus;		/* 0x18 */
-	unsigned int irqenable;		/* 0x1C */
-	unsigned int wakeupenable;	/* 0x20 */
-	unsigned int syst;		/* 0x24 */
-	unsigned int modulctrl;		/* 0x28 */
-	struct mcspi_channel channel[4];
-	/* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
-	/* channel1: 0x40 - 0x50, bus 0 & 1 */
-	/* channel2: 0x54 - 0x64, bus 0 & 1 */
-	/* channel3: 0x68 - 0x78, bus 0 */
-};
-
 struct omap3_spi_priv {
 	struct mcspi *regs;
 	unsigned int cs;
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 103c046137..5af90d932d 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -287,8 +287,6 @@
 #define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
 #endif
 
-/* SPI flash. */
-
 /* Network. */
 /* Enable Atheros phy driver */
 
diff --git a/include/omap3_spi.h b/include/omap3_spi.h
new file mode 100644
index 0000000000..cae3770583
--- /dev/null
+++ b/include/omap3_spi.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef __OMAP3_SPI_H_
+#define __OMAP3_SPI_H_
+
+/* per-register bitmasks */
+#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
+#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
+#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE	BIT(0)
+#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
+
+#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
+
+#define OMAP3_MCSPI_MODULCTRL_SINGLE	BIT(0)
+#define OMAP3_MCSPI_MODULCTRL_MS	BIT(2)
+#define OMAP3_MCSPI_MODULCTRL_STEST	BIT(3)
+
+#define OMAP3_MCSPI_CHCONF_PHA		BIT(0)
+#define OMAP3_MCSPI_CHCONF_POL		BIT(1)
+#define OMAP3_MCSPI_CHCONF_CLKD_MASK	GENMASK(5, 2)
+#define OMAP3_MCSPI_CHCONF_EPOL		BIT(6)
+#define OMAP3_MCSPI_CHCONF_WL_MASK	GENMASK(11, 7)
+#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	BIT(12)
+#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	BIT(13)
+#define OMAP3_MCSPI_CHCONF_TRM_MASK	GENMASK(13, 12)
+#define OMAP3_MCSPI_CHCONF_DMAW		BIT(14)
+#define OMAP3_MCSPI_CHCONF_DMAR		BIT(15)
+#define OMAP3_MCSPI_CHCONF_DPE0		BIT(16)
+#define OMAP3_MCSPI_CHCONF_DPE1		BIT(17)
+#define OMAP3_MCSPI_CHCONF_IS		BIT(18)
+#define OMAP3_MCSPI_CHCONF_TURBO	BIT(19)
+#define OMAP3_MCSPI_CHCONF_FORCE	BIT(20)
+
+#define OMAP3_MCSPI_CHSTAT_RXS		BIT(0)
+#define OMAP3_MCSPI_CHSTAT_TXS		BIT(1)
+#define OMAP3_MCSPI_CHSTAT_EOT		BIT(2)
+
+#define OMAP3_MCSPI_CHCTRL_EN		BIT(0)
+#define OMAP3_MCSPI_CHCTRL_DIS		(0 << 0)
+
+#define OMAP3_MCSPI_WAKEUPENABLE_WKEN	BIT(0)
+#define MCSPI_PINDIR_D0_IN_D1_OUT	0
+#define MCSPI_PINDIR_D0_OUT_D1_IN	1
+
+#define OMAP3_MCSPI_MAX_FREQ		48000000
+#define SPI_WAIT_TIMEOUT		10
+
+#define OMAP4_MCSPI_REG_OFFSET	0x100
+
+/* OMAP3 McSPI registers */
+struct mcspi_channel {
+	unsigned int chconf;		/* 0x2C, 0x40, 0x54, 0x68 */
+	unsigned int chstat;		/* 0x30, 0x44, 0x58, 0x6C */
+	unsigned int chctrl;		/* 0x34, 0x48, 0x5C, 0x70 */
+	unsigned int tx;		/* 0x38, 0x4C, 0x60, 0x74 */
+	unsigned int rx;		/* 0x3C, 0x50, 0x64, 0x78 */
+};
+
+struct mcspi {
+	unsigned char res1[0x10];
+	unsigned int sysconfig;		/* 0x10 */
+	unsigned int sysstatus;		/* 0x14 */
+	unsigned int irqstatus;		/* 0x18 */
+	unsigned int irqenable;		/* 0x1C */
+	unsigned int wakeupenable;	/* 0x20 */
+	unsigned int syst;		/* 0x24 */
+	unsigned int modulctrl;		/* 0x28 */
+	struct mcspi_channel channel[4];
+	/* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
+	/* channel1: 0x40 - 0x50, bus 0 & 1 */
+	/* channel2: 0x54 - 0x64, bus 0 & 1 */
+	/* channel3: 0x68 - 0x78, bus 0 */
+};
+
+struct omap3_spi_plat {
+	struct mcspi *regs;
+	unsigned int pin_dir:1;
+};
+#endif

From afd4f15a39de0fa572792a3037545afbac386ee5 Mon Sep 17 00:00:00 2001
From: Faiz Abbas <faiz_abbas@ti.com>
Date: Mon, 14 Sep 2020 12:11:16 +0530
Subject: [PATCH 25/26] spi: omap3_spi: Read platform data in
 ofdata_to_platdata()

Add an ofdata_to_platdata() callback to access dts in U-boot and
access all platform data in it. This prepares the driver for supporting
both device tree as well as static platform data structures in SPL.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
---
 drivers/spi/omap3_spi.c | 37 ++++++++++++++++++++++++++-----------
 1 file changed, 26 insertions(+), 11 deletions(-)

diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index fb1cf360fc..56cb217486 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -414,17 +414,10 @@ static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen)
 static int omap3_spi_probe(struct udevice *dev)
 {
 	struct omap3_spi_priv *priv = dev_get_priv(dev);
-	const void *blob = gd->fdt_blob;
-	int node = dev_of_offset(dev);
+	struct omap3_spi_plat *plat = dev_get_platdata(dev);
 
-	struct omap2_mcspi_platform_config* data =
-		(struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
-
-	priv->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
-	if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
-		priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
-	else
-		priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
+	priv->regs = plat->regs;
+	priv->pin_dir = plat->pin_dir;
 	priv->wordlen = SPI_DEFAULT_WORDLEN;
 
 	spi_reset(priv->regs);
@@ -476,6 +469,7 @@ static const struct dm_spi_ops omap3_spi_ops = {
 	 */
 };
 
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 static struct omap2_mcspi_platform_config omap2_pdata = {
 	.regs_offset = 0,
 };
@@ -484,16 +478,37 @@ static struct omap2_mcspi_platform_config omap4_pdata = {
 	.regs_offset = OMAP4_MCSPI_REG_OFFSET,
 };
 
+static int omap3_spi_ofdata_to_platdata(struct udevice *dev)
+{
+	struct omap2_mcspi_platform_config *data =
+		(struct omap2_mcspi_platform_config *)dev_get_driver_data(dev);
+	struct omap3_spi_plat *plat = dev_get_platdata(dev);
+
+	plat->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
+
+	if (dev_read_bool(dev, "ti,pindir-d0-out-d1-in"))
+		plat->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
+	else
+		plat->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
+
+	return 0;
+}
+
 static const struct udevice_id omap3_spi_ids[] = {
 	{ .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
 	{ .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
 	{ }
 };
-
+#endif
 U_BOOT_DRIVER(omap3_spi) = {
 	.name   = "omap3_spi",
 	.id     = UCLASS_SPI,
+	.flags	= DM_FLAG_PRE_RELOC,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 	.of_match = omap3_spi_ids,
+	.ofdata_to_platdata = omap3_spi_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct omap3_spi_plat),
+#endif
 	.probe = omap3_spi_probe,
 	.ops    = &omap3_spi_ops,
 	.priv_auto_alloc_size = sizeof(struct omap3_spi_priv),

From 5ba2883160d15b669957dcc50be2733a9b4abe94 Mon Sep 17 00:00:00 2001
From: Faiz Abbas <faiz_abbas@ti.com>
Date: Mon, 14 Sep 2020 12:11:17 +0530
Subject: [PATCH 26/26] configs: Add spiboot support for am335x

am335x internal SRAM is too small to support the addition of
SPI bootmode to the default defconfig. Add a separate spiboot_defconfig

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
---
 board/ti/am335x/MAINTAINERS          |  1 +
 configs/am335x_evm_spiboot_defconfig | 93 ++++++++++++++++++++++++++++
 2 files changed, 94 insertions(+)
 create mode 100644 configs/am335x_evm_spiboot_defconfig

diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS
index e100adfd68..219c8715bf 100644
--- a/board/ti/am335x/MAINTAINERS
+++ b/board/ti/am335x/MAINTAINERS
@@ -5,3 +5,4 @@ F:	board/ti/am335x/
 F:	include/configs/am335x_evm.h
 F:	configs/am335x_boneblack_vboot_defconfig
 F:	configs/am335x_evm_defconfig
+F:	configs/am335x_evm_spiboot_defconfig
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
new file mode 100644
index 0000000000..d71a7ce75c
--- /dev/null
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_ENV_OFFSET=0x100000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_SPL_DM_SPI=y
+CONFIG_AM33XX=y
+# CONFIG_SPL_MMC_SUPPORT is not set
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
+CONFIG_LOGLEVEL=3
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_FIT_IMAGE_TINY=y
+# CONFIG_SPL_FS_EXT4 is not set
+CONFIG_SPL_MTD_SUPPORT=y
+# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_SPL=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
+CONFIG_CMD_MTDPARTS=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
+CONFIG_ENV_OVERWRITE=y
+# CONFIG_ENV_IS_IN_FAT is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_ENV_IS_NOWHERE=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_CLK=y
+CONFIG_CLK_CDCE9XX=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_NAND=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+# CONFIG_SPL_DM_MMC is not set
+# CONFIG_MMC_HW_PARTITIONING is not set
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+# CONFIG_SPL_NAND_AM33XX_BCH is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OMAP3_SPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_TI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_USB_ETHER=y
+CONFIG_WDT=y
+# CONFIG_SPL_WDT is not set
+CONFIG_DYNAMIC_CRC_TABLE=y
+CONFIG_RSA=y
+CONFIG_LZO=y
+# CONFIG_OF_LIBFDT_OVERLAY is not set