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imx: imx8mm-evk: enable ethernet
add phy-reset-gpios to reset phy Add board_phy_config to configure phy Enable DM_ETH Signed-off-by: Peng Fan <peng.fan@nxp.com>
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parent
673f659732
commit
bdcf3a88cc
4 changed files with 56 additions and 0 deletions
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@ -113,3 +113,7 @@
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&pinctrl_pmic {
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u-boot,dm-spl;
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};
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&fec1 {
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phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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};
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@ -4,6 +4,11 @@
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -14,8 +19,40 @@ int dram_init(void)
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return 0;
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}
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#if IS_ENABLED(CONFIG_FEC_MXC)
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static int setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Use 125M anatop REF_CLK1 for ENET1, not from external */
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clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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/* enable rgmii rxc skew and phy mode select to RGMII copper */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int board_init(void)
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{
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if (IS_ENABLED(CONFIG_FEC_MXC))
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setup_fec();
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return 0;
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}
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@ -35,6 +35,9 @@ CONFIG_CMD_FUSE=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_CMD_EXT2=y
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@ -62,7 +65,11 @@ CONFIG_DM_MMC=y
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CONFIG_SUPPORT_EMMC_BOOT=y
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CONFIG_FSL_ESDHC_IMX=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_DM_ETH=y
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CONFIG_PHY_GIGE=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_PINCTRL_IMX8M=y
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@ -150,4 +150,12 @@
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define FEC_QUIRK_ENET_MAC
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#define IMX_FEC_BASE 0x30BE0000
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#endif
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