mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Merge tag 'u-boot-rockchip-20191206' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- rockchip pwm driver update to support all the SoCs - RK3308 GMAC and pinctrl support - More UART interface support on PX30 and pmugrf reg fix - Fixup on misc for eth_addr/serial# - Other updates on variant SoCs
This commit is contained in:
commit
bead4f2f2c
24 changed files with 973 additions and 45 deletions
|
@ -143,6 +143,15 @@
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|||
};
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};
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&mac {
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assigned-clocks = <&cru SCLK_MAC>;
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assigned-clock-parents = <&mac_clkin>;
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clock_in_out = "input";
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pinctrl-names = "default";
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pinctrl-0 = <&rmiim1_pins &macm1_refclk>;
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status = "okay";
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};
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&pwm5 {
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status = "okay";
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pinctrl-names = "active";
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|
|
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@ -12,6 +12,8 @@
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};
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&emmc {
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/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
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u-boot,spl-fifo-mode;
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u-boot,dm-pre-reloc;
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};
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|
|
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@ -627,6 +627,28 @@
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status = "disabled";
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};
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mac: ethernet@ff4e0000 {
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compatible = "rockchip,rk3308-mac";
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reg = <0x0 0xff4e0000 0x0 0x10000>;
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rockchip,grf = <&grf>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
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<&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
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<&cru SCLK_MAC>, <&cru ACLK_MAC>,
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<&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
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clock-names = "stmmaceth", "mac_clk_rx",
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"mac_clk_tx", "clk_mac_ref",
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"clk_mac_refout", "aclk_mac",
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"pclk_mac", "clk_mac_speed";
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phy-mode = "rmii";
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pinctrl-names = "default";
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pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
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resets = <&cru SRST_MAC_A>;
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reset-names = "stmmaceth";
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status = "disabled";
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};
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cru: clock-controller@ff500000 {
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compatible = "rockchip,rk3308-cru";
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reg = <0x0 0xff500000 0x0 0x1000>;
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|
|
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@ -58,6 +58,8 @@
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};
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&emmc {
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/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
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u-boot,spl-fifo-mode;
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u-boot,dm-pre-reloc;
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};
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|
|
|
@ -357,6 +357,25 @@ enum {
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UART2_DIVNP5_SHIFT = 0,
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UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT,
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/* CRU_CLK_SEL40_CON */
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UART3_PLL_SEL_SHIFT = 14,
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UART3_PLL_SEL_MASK = 3 << UART3_PLL_SEL_SHIFT,
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UART3_PLL_SEL_GPLL = 0,
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UART3_PLL_SEL_24M,
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UART3_PLL_SEL_480M,
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UART3_PLL_SEL_NPLL,
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UART3_DIV_CON_SHIFT = 0,
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UART3_DIV_CON_MASK = 0x1f << UART3_DIV_CON_SHIFT,
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/* CRU_CLK_SEL41_CON */
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UART3_CLK_SEL_SHIFT = 14,
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UART3_CLK_SEL_MASK = 3 << UART3_PLL_SEL_SHIFT,
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UART3_CLK_SEL_UART3 = 0,
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UART3_CLK_SEL_UART3_NP5,
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UART3_CLK_SEL_UART3_FRAC,
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UART3_DIVNP5_SHIFT = 0,
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UART3_DIVNP5_MASK = 0x1f << UART3_DIVNP5_SHIFT,
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/* CRU_CLK_SEL46_CON */
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UART5_PLL_SEL_SHIFT = 14,
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UART5_PLL_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT,
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|
|
|
@ -112,18 +112,18 @@ struct px30_grf {
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check_member(px30_grf, mac_con1, 0x904);
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struct px30_pmugrf {
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unsigned int gpio0a_e;
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unsigned int gpio0b_e;
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unsigned int gpio0c_e;
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unsigned int gpio0d_e;
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unsigned int gpio0a_p;
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unsigned int gpio0b_p;
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unsigned int gpio0c_p;
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unsigned int gpio0d_p;
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unsigned int gpio0al_iomux;
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unsigned int gpio0bl_iomux;
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unsigned int gpio0cl_iomux;
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unsigned int gpio0dl_iomux;
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unsigned int gpio0a_p;
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unsigned int gpio0b_p;
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unsigned int gpio0c_p;
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unsigned int gpio0d_p;
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unsigned int gpio0a_e;
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unsigned int gpio0b_e;
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unsigned int gpio0c_e;
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unsigned int gpio0d_e;
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unsigned int gpio0l_sr;
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unsigned int gpio0h_sr;
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unsigned int gpio0l_smt;
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|
|
|
@ -7,13 +7,15 @@
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#ifndef _ASM_ARCH_PWM_H
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#define _ASM_ARCH_PWM_H
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struct rk3288_pwm {
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u32 cnt;
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u32 period_hpr;
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u32 duty_lpr;
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u32 ctrl;
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struct rockchip_pwm_regs {
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unsigned long duty;
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unsigned long period;
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unsigned long cntr;
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unsigned long ctrl;
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};
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check_member(rk3288_pwm, ctrl, 0xc);
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#define PWM_CTRL_TIMER_EN (1 << 0)
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#define PWM_CTRL_OUTPUT_EN (1 << 3)
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#define RK_PWM_DISABLE (0 << 0)
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#define RK_PWM_ENABLE (1 << 0)
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@ -33,6 +35,9 @@ check_member(rk3288_pwm, ctrl, 0xc);
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#define PWM_OUTPUT_LEFT (0 << 5)
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#define PWM_OUTPUT_CENTER (1 << 5)
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#define PWM_LOCK (1 << 6)
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#define PWM_UNLOCK (0 << 6)
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#define PWM_LP_ENABLE (1 << 8)
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#define PWM_LP_DISABLE (0 << 8)
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|
|
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@ -30,7 +30,7 @@ int rockchip_setup_macaddr(void)
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/* Only generate a MAC address, if none is set in the environment */
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if (env_get("ethaddr"))
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return -1;
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return 0;
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if (!cpuid) {
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debug("%s: could not retrieve 'cpuid#'\n", __func__);
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@ -92,6 +92,7 @@ int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length)
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char cpuid_str[cpuid_length * 2 + 1];
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u64 serialno;
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char serialno_str[17];
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const char *oldid;
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int i;
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memset(cpuid_str, 0, sizeof(cpuid_str));
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@ -113,8 +114,16 @@ int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length)
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serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
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snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno);
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oldid = env_get("cpuid#");
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if (oldid && strcmp(oldid, cpuid_str) != 0)
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printf("cpuid: value %s present in env does not match hardware %s\n",
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oldid, cpuid_str);
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env_set("cpuid#", cpuid_str);
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env_set("serial#", serialno_str);
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/* Only generate serial# when none is set yet */
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if (!env_get("serial#"))
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env_set("serial#", serialno_str);
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return 0;
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}
|
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|
|
|
@ -27,12 +27,12 @@ config TPL_MAX_SIZE
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config TPL_STACK
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default 0xff0e4fff
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config DEBUG_UART2_CHANNEL
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int "Mux channel to use for debug UART2"
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config DEBUG_UART_CHANNEL
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int "Mux channel to use for debug UART2/UART3"
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depends on DEBUG_UART_BOARD_INIT
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default 0
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help
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UART2 can use two different set of pins to route the output.
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UART2 and UART3 can use two different set of pins to route the output.
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For using the UART for early debugging the route to use needs
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to be declared (0 or 1).
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|
|
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@ -37,6 +37,7 @@ static struct mm_region px30_mem_map[] = {
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struct mm_region *mem_map = px30_mem_map;
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#define PMU_PWRDN_CON 0xff000018
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#define PMUGRF_BASE 0xff010000
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#define GRF_BASE 0xff140000
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#define CRU_BASE 0xff2b0000
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#define VIDEO_PHY_BASE 0xff2e0000
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|
@ -49,6 +50,23 @@ struct mm_region *mem_map = px30_mem_map;
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|||
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#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
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/* GRF_GPIO1BH_IOMUX */
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enum {
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GPIO1B7_SHIFT = 12,
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GPIO1B7_MASK = 0xf << GPIO1B7_SHIFT,
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GPIO1B7_GPIO = 0,
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GPIO1B7_FLASH_RDN,
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GPIO1B7_UART3_RXM1,
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GPIO1B7_SPI0_CLK,
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GPIO1B6_SHIFT = 8,
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GPIO1B6_MASK = 0xf << GPIO1B6_SHIFT,
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GPIO1B6_GPIO = 0,
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GPIO1B6_FLASH_CS1,
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GPIO1B6_UART3_TXM1,
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GPIO1B6_SPI0_CSN,
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};
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/* GRF_GPIO1CL_IOMUX */
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enum {
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GPIO1C1_SHIFT = 4,
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|
@ -128,6 +146,23 @@ enum {
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GPIO3A1_UART5_RX = 4,
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};
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/* PMUGRF_GPIO0CL_IOMUX */
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enum {
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GPIO0C1_SHIFT = 2,
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GPIO0C1_MASK = 0x3 << GPIO0C1_SHIFT,
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GPIO0C1_GPIO = 0,
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GPIO0C1_PWM_3,
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GPIO0C1_UART3_RXM0,
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GPIO0C1_PMU_DEBUG4,
|
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|
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GPIO0C0_SHIFT = 0,
|
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GPIO0C0_MASK = 0x3 << GPIO0C0_SHIFT,
|
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GPIO0C0_GPIO = 0,
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GPIO0C0_PWM_1,
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GPIO0C0_UART3_TXM0,
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GPIO0C0_PMU_DEBUG3,
|
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};
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
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static struct px30_grf * const grf = (void *)GRF_BASE;
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|
@ -175,6 +210,11 @@ int arch_cpu_init(void)
|
|||
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
|
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void board_debug_uart_init(void)
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{
|
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#if defined(CONFIG_DEBUG_UART_BASE) && \
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(CONFIG_DEBUG_UART_BASE == 0xff168000) && \
|
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(CONFIG_DEBUG_UART_CHANNEL != 1)
|
||||
static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
|
||||
#endif
|
||||
static struct px30_grf * const grf = (void *)GRF_BASE;
|
||||
static struct px30_cru * const cru = (void *)CRU_BASE;
|
||||
|
||||
|
@ -191,6 +231,43 @@ void board_debug_uart_init(void)
|
|||
GPIO1C1_MASK | GPIO1C0_MASK,
|
||||
GPIO1C1_UART1_TX << GPIO1C1_SHIFT |
|
||||
GPIO1C0_UART1_RX << GPIO1C0_SHIFT);
|
||||
#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff168000)
|
||||
/* GRF_IOFUNC_CON0 */
|
||||
enum {
|
||||
CON_IOMUX_UART3SEL_SHIFT = 9,
|
||||
CON_IOMUX_UART3SEL_MASK = 1 << CON_IOMUX_UART3SEL_SHIFT,
|
||||
CON_IOMUX_UART3SEL_M0 = 0,
|
||||
CON_IOMUX_UART3SEL_M1,
|
||||
};
|
||||
|
||||
/* uart_sel_clk default select 24MHz */
|
||||
rk_clrsetreg(&cru->clksel_con[40],
|
||||
UART3_PLL_SEL_MASK | UART3_DIV_CON_MASK,
|
||||
UART3_PLL_SEL_24M << UART3_PLL_SEL_SHIFT | 0);
|
||||
rk_clrsetreg(&cru->clksel_con[41],
|
||||
UART3_CLK_SEL_MASK,
|
||||
UART3_CLK_SEL_UART3 << UART3_CLK_SEL_SHIFT);
|
||||
|
||||
#if (CONFIG_DEBUG_UART_CHANNEL == 1)
|
||||
rk_clrsetreg(&grf->iofunc_con0,
|
||||
CON_IOMUX_UART3SEL_MASK,
|
||||
CON_IOMUX_UART3SEL_M1 << CON_IOMUX_UART3SEL_SHIFT);
|
||||
|
||||
rk_clrsetreg(&grf->gpio1bh_iomux,
|
||||
GPIO1B7_MASK | GPIO1B6_MASK,
|
||||
GPIO1B7_UART3_RXM1 << GPIO1B7_SHIFT |
|
||||
GPIO1B6_UART3_TXM1 << GPIO1B6_SHIFT);
|
||||
#else
|
||||
rk_clrsetreg(&grf->iofunc_con0,
|
||||
CON_IOMUX_UART3SEL_MASK,
|
||||
CON_IOMUX_UART3SEL_M0 << CON_IOMUX_UART3SEL_SHIFT);
|
||||
|
||||
rk_clrsetreg(&pmugrf->gpio0cl_iomux,
|
||||
GPIO0C1_MASK | GPIO0C0_MASK,
|
||||
GPIO0C1_UART3_RXM0 << GPIO0C1_SHIFT |
|
||||
GPIO0C0_UART3_TXM0 << GPIO0C0_SHIFT);
|
||||
#endif /* CONFIG_DEBUG_UART_CHANNEL == 1 */
|
||||
|
||||
#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000)
|
||||
/* uart_sel_clk default select 24MHz */
|
||||
rk_clrsetreg(&cru->clksel_con[46],
|
||||
|
@ -222,7 +299,7 @@ void board_debug_uart_init(void)
|
|||
UART2_CLK_SEL_MASK,
|
||||
UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT);
|
||||
|
||||
#if (CONFIG_DEBUG_UART2_CHANNEL == 1)
|
||||
#if (CONFIG_DEBUG_UART_CHANNEL == 1)
|
||||
/* Enable early UART2 */
|
||||
rk_clrsetreg(&grf->iofunc_con0,
|
||||
CON_IOMUX_UART2SEL_MASK,
|
||||
|
@ -241,7 +318,7 @@ void board_debug_uart_init(void)
|
|||
GPIO1D3_MASK | GPIO1D2_MASK,
|
||||
GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT |
|
||||
GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT);
|
||||
#endif /* CONFIG_DEBUG_UART2_CHANNEL == 1 */
|
||||
#endif /* CONFIG_DEBUG_UART_CHANNEL == 1 */
|
||||
|
||||
#endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
|
||||
}
|
||||
|
|
|
@ -72,6 +72,11 @@ enum {
|
|||
UART2_IO_SEL_M1,
|
||||
UART2_IO_SEL_USB,
|
||||
|
||||
GPIO2C0_SEL_SRC_CTRL_SHIFT = 11,
|
||||
GPIO2C0_SEL_SRC_CTRL_MASK = BIT(11),
|
||||
GPIO2C0_SEL_SRC_CTRL_IOMUX = 0,
|
||||
GPIO2C0_SEL_SRC_CTRL_SEL_PLUS,
|
||||
|
||||
GPIO3B3_SEL_SRC_CTRL_SHIFT = 7,
|
||||
GPIO3B3_SEL_SRC_CTRL_MASK = BIT(7),
|
||||
GPIO3B3_SEL_SRC_CTRL_IOMUX = 0,
|
||||
|
@ -97,6 +102,18 @@ enum {
|
|||
GPIO3B2_SEL_PLUS_EMMC_RSTN,
|
||||
GPIO3B2_SEL_PLUS_SPI1_MISO,
|
||||
GPIO3B2_SEL_PLUS_LCDC_D22_M1,
|
||||
|
||||
I2C3_IOFUNC_SRC_CTRL_SHIFT = 10,
|
||||
I2C3_IOFUNC_SRC_CTRL_MASK = BIT(10),
|
||||
I2C3_IOFUNC_SRC_CTRL_SEL_PLUS = 1,
|
||||
|
||||
GPIO2A3_SEL_SRC_CTRL_SHIFT = 7,
|
||||
GPIO2A3_SEL_SRC_CTRL_MASK = BIT(7),
|
||||
GPIO2A3_SEL_SRC_CTRL_SEL_PLUS = 1,
|
||||
|
||||
GPIO2A2_SEL_SRC_CTRL_SHIFT = 3,
|
||||
GPIO2A2_SEL_SRC_CTRL_MASK = BIT(3),
|
||||
GPIO2A2_SEL_SRC_CTRL_SEL_PLUS = 1,
|
||||
};
|
||||
|
||||
enum {
|
||||
|
@ -166,10 +183,30 @@ __weak void board_debug_uart_init(void)
|
|||
int arch_cpu_init(void)
|
||||
{
|
||||
static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE;
|
||||
static struct rk3308_grf * const grf = (void *)GRF_BASE;
|
||||
|
||||
/* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */
|
||||
rk_clrreg(&sgrf->con_secure0, 0x2b83);
|
||||
|
||||
/*
|
||||
* Enable plus options to use more pinctrl functions, including
|
||||
* GPIO2A2_PLUS, GPIO2A3_PLUS and I2C3_MULTI_SRC_PLUS.
|
||||
*/
|
||||
rk_clrsetreg(&grf->soc_con13,
|
||||
I2C3_IOFUNC_SRC_CTRL_MASK | GPIO2A3_SEL_SRC_CTRL_MASK |
|
||||
GPIO2A2_SEL_SRC_CTRL_MASK,
|
||||
I2C3_IOFUNC_SRC_CTRL_SEL_PLUS << I2C3_IOFUNC_SRC_CTRL_SHIFT |
|
||||
GPIO2A3_SEL_SRC_CTRL_SEL_PLUS << GPIO2A3_SEL_SRC_CTRL_SHIFT |
|
||||
GPIO2A2_SEL_SRC_CTRL_SEL_PLUS << GPIO2A2_SEL_SRC_CTRL_SHIFT);
|
||||
|
||||
/* Plus options about GPIO3B2_PLUS, GPIO3B3_PLUS and GPIO2C0_PLUS. */
|
||||
rk_clrsetreg(&grf->soc_con15,
|
||||
GPIO2C0_SEL_SRC_CTRL_MASK | GPIO3B3_SEL_SRC_CTRL_MASK |
|
||||
GPIO3B2_SEL_SRC_CTRL_MASK,
|
||||
GPIO2C0_SEL_SRC_CTRL_SEL_PLUS << GPIO2C0_SEL_SRC_CTRL_SHIFT |
|
||||
GPIO3B3_SEL_SRC_CTRL_SEL_PLUS << GPIO3B3_SEL_SRC_CTRL_SHIFT |
|
||||
GPIO3B2_SEL_SRC_CTRL_SEL_PLUS << GPIO3B2_SEL_SRC_CTRL_SHIFT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -4,3 +4,4 @@ S: Maintained
|
|||
F: board/rockchip/evb_px30
|
||||
F: include/configs/evb_px30.h
|
||||
F: configs/evb-px30_defconfig
|
||||
F: configs/firefly-px30_defconfig
|
||||
|
|
|
@ -45,7 +45,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
|
|||
CONFIG_TPL_OF_PLATDATA=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
# CONFIG_NET is not set
|
||||
CONFIG_TPL_DM=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
|
|
113
configs/firefly-px30_defconfig
Normal file
113
configs/firefly-px30_defconfig
Normal file
|
@ -0,0 +1,113 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_ROCKCHIP_PX30=y
|
||||
CONFIG_TARGET_EVB_PX30=y
|
||||
CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DEBUG_UART_BASE=0xFF160000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_SPL_TEXT_BASE=0x00000000
|
||||
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/px30-evb.dtb"
|
||||
CONFIG_MISC_INIT_R=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_STACK_R=y
|
||||
# CONFIG_TPL_BANNER_PRINT is not set
|
||||
CONFIG_SPL_CRC32_SUPPORT=y
|
||||
CONFIG_SPL_ATF=y
|
||||
# CONFIG_TPL_FRAMEWORK is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
CONFIG_DEBUG_UART2_CHANNEL=1
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPT=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_CMD_MISC is not set
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="px30-evb"
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x800800
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_ROCKCHIP_OTP=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_TPL_RAM=y
|
||||
CONFIG_ROCKCHIP_SDRAM_COMMON=y
|
||||
CONFIG_DM_RESET=y
|
||||
# CONFIG_SPECIFY_CONSOLE_INDEX is not set
|
||||
# CONFIG_TPL_DM_SERIAL is not set
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_DEBUG_UART_SKIP_INIT=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_DISPLAY=y
|
||||
CONFIG_LCD=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_TPL_TINY_MEMSET=y
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_LZO=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
# CONFIG_EFI_LOADER is not set
|
|
@ -19,6 +19,7 @@ CONFIG_FIT=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb"
|
||||
CONFIG_MISC_INIT_R=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
|
|
|
@ -108,7 +108,6 @@ For example:
|
|||
=> export BL31=/path/to/rkbin/bin/rk33/rk3308_bl31_v2.22.elf
|
||||
=> make roc-rk3308-cc_defconfig
|
||||
=> make CROSS_COMPILE=aarch64-linux-gnu- all
|
||||
=> make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb
|
||||
=> ./tools/mkimage -n rk3308 -T rksd -d /path/to/rkbin/bin/rk33/rk3308_ddr_589MHz_uart2_m0_v1.26.bin idbloader.img
|
||||
=> cat spl/u-boot-spl.bin >> idbloader.img
|
||||
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include <asm/arch-rockchip/grf_px30.h>
|
||||
#include <asm/arch-rockchip/grf_rk322x.h>
|
||||
#include <asm/arch-rockchip/grf_rk3288.h>
|
||||
#include <asm/arch-rk3308/grf_rk3308.h>
|
||||
#include <asm/arch-rockchip/grf_rk3328.h>
|
||||
#include <asm/arch-rockchip/grf_rk3368.h>
|
||||
#include <asm/arch-rockchip/grf_rk3399.h>
|
||||
|
@ -173,6 +174,47 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
|
||||
{
|
||||
struct rk3308_grf *grf;
|
||||
struct clk clk_speed;
|
||||
int speed, ret;
|
||||
enum {
|
||||
RK3308_GMAC_SPEED_SHIFT = 0x0,
|
||||
RK3308_GMAC_SPEED_MASK = BIT(0),
|
||||
RK3308_GMAC_SPEED_10M = 0,
|
||||
RK3308_GMAC_SPEED_100M = BIT(0),
|
||||
};
|
||||
|
||||
ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
|
||||
&clk_speed);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
switch (priv->phydev->speed) {
|
||||
case 10:
|
||||
speed = RK3308_GMAC_SPEED_10M;
|
||||
ret = clk_set_rate(&clk_speed, 2500000);
|
||||
if (ret)
|
||||
return ret;
|
||||
break;
|
||||
case 100:
|
||||
speed = RK3308_GMAC_SPEED_100M;
|
||||
ret = clk_set_rate(&clk_speed, 25000000);
|
||||
if (ret)
|
||||
return ret;
|
||||
break;
|
||||
default:
|
||||
debug("Unknown phy speed: %d\n", priv->phydev->speed);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
||||
rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
|
||||
{
|
||||
struct rk3328_grf_regs *grf;
|
||||
|
@ -377,6 +419,22 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
|
|||
pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
|
||||
}
|
||||
|
||||
static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
|
||||
{
|
||||
struct rk3308_grf *grf;
|
||||
enum {
|
||||
RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2,
|
||||
RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2),
|
||||
RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4),
|
||||
};
|
||||
|
||||
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
||||
|
||||
rk_clrsetreg(&grf->mac_con0,
|
||||
RK3308_GMAC_PHY_INTF_SEL_MASK,
|
||||
RK3308_GMAC_PHY_INTF_SEL_RMII);
|
||||
}
|
||||
|
||||
static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
|
||||
{
|
||||
struct rk3328_grf_regs *grf;
|
||||
|
@ -646,6 +704,11 @@ const struct rk_gmac_ops rk3288_gmac_ops = {
|
|||
.set_to_rgmii = rk3288_gmac_set_to_rgmii,
|
||||
};
|
||||
|
||||
const struct rk_gmac_ops rk3308_gmac_ops = {
|
||||
.fix_mac_speed = rk3308_gmac_fix_mac_speed,
|
||||
.set_to_rmii = rk3308_gmac_set_to_rmii,
|
||||
};
|
||||
|
||||
const struct rk_gmac_ops rk3328_gmac_ops = {
|
||||
.fix_mac_speed = rk3328_gmac_fix_mac_speed,
|
||||
.set_to_rgmii = rk3328_gmac_set_to_rgmii,
|
||||
|
@ -673,6 +736,8 @@ static const struct udevice_id rockchip_gmac_ids[] = {
|
|||
.data = (ulong)&rk3228_gmac_ops },
|
||||
{ .compatible = "rockchip,rk3288-gmac",
|
||||
.data = (ulong)&rk3288_gmac_ops },
|
||||
{ .compatible = "rockchip,rk3308-mac",
|
||||
.data = (ulong)&rk3308_gmac_ops },
|
||||
{ .compatible = "rockchip,rk3328-gmac",
|
||||
.data = (ulong)&rk3328_gmac_ops },
|
||||
{ .compatible = "rockchip,rk3368-gmac",
|
||||
|
|
|
@ -9,6 +9,7 @@ obj-$(CONFIG_ROCKCHIP_RK3128) += pinctrl-rk3128.o
|
|||
obj-$(CONFIG_ROCKCHIP_RK3188) += pinctrl-rk3188.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK322X) += pinctrl-rk322x.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3288) += pinctrl-rk3288.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
|
||||
|
|
464
drivers/pinctrl/rockchip/pinctrl-rk3308.c
Normal file
464
drivers/pinctrl/rockchip/pinctrl-rk3308.c
Normal file
|
@ -0,0 +1,464 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <dm/pinctrl.h>
|
||||
#include <regmap.h>
|
||||
#include <syscon.h>
|
||||
|
||||
#include "pinctrl-rockchip.h"
|
||||
|
||||
static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
|
||||
{
|
||||
.num = 1,
|
||||
.pin = 14,
|
||||
.reg = 0x28,
|
||||
.bit = 12,
|
||||
.mask = 0xf
|
||||
}, {
|
||||
.num = 1,
|
||||
.pin = 15,
|
||||
.reg = 0x2c,
|
||||
.bit = 0,
|
||||
.mask = 0x3
|
||||
}, {
|
||||
.num = 1,
|
||||
.pin = 18,
|
||||
.reg = 0x30,
|
||||
.bit = 4,
|
||||
.mask = 0xf
|
||||
}, {
|
||||
.num = 1,
|
||||
.pin = 19,
|
||||
.reg = 0x30,
|
||||
.bit = 8,
|
||||
.mask = 0xf
|
||||
}, {
|
||||
.num = 1,
|
||||
.pin = 20,
|
||||
.reg = 0x30,
|
||||
.bit = 12,
|
||||
.mask = 0xf
|
||||
}, {
|
||||
.num = 1,
|
||||
.pin = 21,
|
||||
.reg = 0x34,
|
||||
.bit = 0,
|
||||
.mask = 0xf
|
||||
}, {
|
||||
.num = 1,
|
||||
.pin = 22,
|
||||
.reg = 0x34,
|
||||
.bit = 4,
|
||||
.mask = 0xf
|
||||
}, {
|
||||
.num = 1,
|
||||
.pin = 23,
|
||||
.reg = 0x34,
|
||||
.bit = 8,
|
||||
.mask = 0xf
|
||||
}, {
|
||||
.num = 3,
|
||||
.pin = 12,
|
||||
.reg = 0x68,
|
||||
.bit = 8,
|
||||
.mask = 0xf
|
||||
}, {
|
||||
.num = 3,
|
||||
.pin = 13,
|
||||
.reg = 0x68,
|
||||
.bit = 12,
|
||||
.mask = 0xf
|
||||
}, {
|
||||
.num = 2,
|
||||
.pin = 2,
|
||||
.reg = 0x608,
|
||||
.bit = 0,
|
||||
.mask = 0x7
|
||||
}, {
|
||||
.num = 2,
|
||||
.pin = 3,
|
||||
.reg = 0x608,
|
||||
.bit = 4,
|
||||
.mask = 0x7
|
||||
}, {
|
||||
.num = 2,
|
||||
.pin = 16,
|
||||
.reg = 0x610,
|
||||
.bit = 8,
|
||||
.mask = 0x7
|
||||
}, {
|
||||
.num = 3,
|
||||
.pin = 10,
|
||||
.reg = 0x610,
|
||||
.bit = 0,
|
||||
.mask = 0x7
|
||||
}, {
|
||||
.num = 3,
|
||||
.pin = 11,
|
||||
.reg = 0x610,
|
||||
.bit = 4,
|
||||
.mask = 0x7
|
||||
},
|
||||
};
|
||||
|
||||
static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
|
||||
{
|
||||
/* rtc_clk */
|
||||
.bank_num = 0,
|
||||
.pin = 19,
|
||||
.func = 1,
|
||||
.route_offset = 0x314,
|
||||
.route_val = BIT(16 + 0) | BIT(0),
|
||||
}, {
|
||||
/* uart2_rxm0 */
|
||||
.bank_num = 1,
|
||||
.pin = 22,
|
||||
.func = 2,
|
||||
.route_offset = 0x314,
|
||||
.route_val = BIT(16 + 2) | BIT(16 + 3),
|
||||
}, {
|
||||
/* uart2_rxm1 */
|
||||
.bank_num = 4,
|
||||
.pin = 26,
|
||||
.func = 2,
|
||||
.route_offset = 0x314,
|
||||
.route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
|
||||
}, {
|
||||
/* i2c3_sdam0 */
|
||||
.bank_num = 0,
|
||||
.pin = 15,
|
||||
.func = 2,
|
||||
.route_offset = 0x608,
|
||||
.route_val = BIT(16 + 8) | BIT(16 + 9),
|
||||
}, {
|
||||
/* i2c3_sdam1 */
|
||||
.bank_num = 3,
|
||||
.pin = 12,
|
||||
.func = 2,
|
||||
.route_offset = 0x608,
|
||||
.route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
|
||||
}, {
|
||||
/* i2c3_sdam2 */
|
||||
.bank_num = 2,
|
||||
.pin = 0,
|
||||
.func = 3,
|
||||
.route_offset = 0x608,
|
||||
.route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),
|
||||
}, {
|
||||
/* i2s-8ch-1-sclktxm0 */
|
||||
.bank_num = 1,
|
||||
.pin = 3,
|
||||
.func = 2,
|
||||
.route_offset = 0x308,
|
||||
.route_val = BIT(16 + 3),
|
||||
}, {
|
||||
/* i2s-8ch-1-sclkrxm0 */
|
||||
.bank_num = 1,
|
||||
.pin = 4,
|
||||
.func = 2,
|
||||
.route_offset = 0x308,
|
||||
.route_val = BIT(16 + 3),
|
||||
}, {
|
||||
/* i2s-8ch-1-sclktxm1 */
|
||||
.bank_num = 1,
|
||||
.pin = 13,
|
||||
.func = 2,
|
||||
.route_offset = 0x308,
|
||||
.route_val = BIT(16 + 3) | BIT(3),
|
||||
}, {
|
||||
/* i2s-8ch-1-sclkrxm1 */
|
||||
.bank_num = 1,
|
||||
.pin = 14,
|
||||
.func = 2,
|
||||
.route_offset = 0x308,
|
||||
.route_val = BIT(16 + 3) | BIT(3),
|
||||
}, {
|
||||
/* pdm-clkm0 */
|
||||
.bank_num = 1,
|
||||
.pin = 4,
|
||||
.func = 3,
|
||||
.route_offset = 0x308,
|
||||
.route_val = BIT(16 + 12) | BIT(16 + 13),
|
||||
}, {
|
||||
/* pdm-clkm1 */
|
||||
.bank_num = 1,
|
||||
.pin = 14,
|
||||
.func = 4,
|
||||
.route_offset = 0x308,
|
||||
.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
|
||||
}, {
|
||||
/* pdm-clkm2 */
|
||||
.bank_num = 2,
|
||||
.pin = 6,
|
||||
.func = 2,
|
||||
.route_offset = 0x308,
|
||||
.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
|
||||
}, {
|
||||
/* pdm-clkm-m2 */
|
||||
.bank_num = 2,
|
||||
.pin = 4,
|
||||
.func = 3,
|
||||
.route_offset = 0x600,
|
||||
.route_val = BIT(16 + 2) | BIT(2),
|
||||
}, {
|
||||
/* spi1_miso */
|
||||
.bank_num = 3,
|
||||
.pin = 10,
|
||||
.func = 3,
|
||||
.route_offset = 0x314,
|
||||
.route_val = BIT(16 + 9),
|
||||
}, {
|
||||
/* spi1_miso_m1 */
|
||||
.bank_num = 2,
|
||||
.pin = 4,
|
||||
.func = 2,
|
||||
.route_offset = 0x314,
|
||||
.route_val = BIT(16 + 9) | BIT(9),
|
||||
}, {
|
||||
/* mac_rxd0_m0 */
|
||||
.bank_num = 1,
|
||||
.pin = 20,
|
||||
.func = 3,
|
||||
.route_offset = 0x314,
|
||||
.route_val = BIT(16 + 14),
|
||||
}, {
|
||||
/* mac_rxd0_m1 */
|
||||
.bank_num = 4,
|
||||
.pin = 2,
|
||||
.func = 2,
|
||||
.route_offset = 0x314,
|
||||
.route_val = BIT(16 + 14) | BIT(14),
|
||||
}, {
|
||||
/* uart3_rx */
|
||||
.bank_num = 3,
|
||||
.pin = 12,
|
||||
.func = 4,
|
||||
.route_offset = 0x314,
|
||||
.route_val = BIT(16 + 15),
|
||||
}, {
|
||||
/* uart3_rx_m1 */
|
||||
.bank_num = 0,
|
||||
.pin = 17,
|
||||
.func = 3,
|
||||
.route_offset = 0x314,
|
||||
.route_val = BIT(16 + 15) | BIT(15),
|
||||
},
|
||||
};
|
||||
|
||||
static int rk3308_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
|
||||
{
|
||||
struct rockchip_pinctrl_priv *priv = bank->priv;
|
||||
int iomux_num = (pin / 8);
|
||||
struct regmap *regmap;
|
||||
int reg, ret, mask, mux_type;
|
||||
u8 bit;
|
||||
u32 data, route_reg, route_val;
|
||||
|
||||
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
|
||||
? priv->regmap_pmu : priv->regmap_base;
|
||||
|
||||
/* get basic quadrupel of mux registers and the correct reg inside */
|
||||
mux_type = bank->iomux[iomux_num].type;
|
||||
reg = bank->iomux[iomux_num].offset;
|
||||
reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
|
||||
|
||||
if (bank->recalced_mask & BIT(pin))
|
||||
rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
|
||||
|
||||
if (bank->route_mask & BIT(pin)) {
|
||||
if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
|
||||
&route_val)) {
|
||||
ret = regmap_write(regmap, route_reg, route_val);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
data = (mask << (bit + 16));
|
||||
data |= (mux & mask) << bit;
|
||||
ret = regmap_write(regmap, reg, data);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define RK3308_PULL_OFFSET 0xa0
|
||||
|
||||
static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
|
||||
int pin_num, struct regmap **regmap,
|
||||
int *reg, u8 *bit)
|
||||
{
|
||||
struct rockchip_pinctrl_priv *priv = bank->priv;
|
||||
|
||||
*regmap = priv->regmap_base;
|
||||
*reg = RK3308_PULL_OFFSET;
|
||||
*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
|
||||
*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
|
||||
|
||||
*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
|
||||
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
|
||||
}
|
||||
|
||||
static int rk3308_set_pull(struct rockchip_pin_bank *bank,
|
||||
int pin_num, int pull)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int reg, ret;
|
||||
u8 bit, type;
|
||||
u32 data;
|
||||
|
||||
if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
|
||||
return -ENOTSUPP;
|
||||
|
||||
rk3308_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
|
||||
type = bank->pull_type[pin_num / 8];
|
||||
ret = rockchip_translate_pull_value(type, pull);
|
||||
if (ret < 0) {
|
||||
debug("unsupported pull setting %d\n", pull);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* enable the write to the equivalent lower bits */
|
||||
data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
|
||||
data |= (ret << bit);
|
||||
|
||||
ret = regmap_write(regmap, reg, data);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define RK3308_DRV_GRF_OFFSET 0x100
|
||||
|
||||
static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
|
||||
int pin_num, struct regmap **regmap,
|
||||
int *reg, u8 *bit)
|
||||
{
|
||||
struct rockchip_pinctrl_priv *priv = bank->priv;
|
||||
|
||||
*regmap = priv->regmap_base;
|
||||
*reg = RK3308_DRV_GRF_OFFSET;
|
||||
*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
|
||||
*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
|
||||
|
||||
*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
|
||||
*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
|
||||
}
|
||||
|
||||
static int rk3308_set_drive(struct rockchip_pin_bank *bank,
|
||||
int pin_num, int strength)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int reg, ret;
|
||||
u32 data;
|
||||
u8 bit;
|
||||
int type = bank->drv[pin_num / 8].drv_type;
|
||||
|
||||
rk3308_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
|
||||
ret = rockchip_translate_drive_value(type, strength);
|
||||
if (ret < 0) {
|
||||
debug("unsupported driver strength %d\n", strength);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* enable the write to the equivalent lower bits */
|
||||
data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
|
||||
data |= (ret << bit);
|
||||
ret = regmap_write(regmap, reg, data);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define RK3308_SCHMITT_PINS_PER_REG 8
|
||||
#define RK3308_SCHMITT_BANK_STRIDE 16
|
||||
#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
|
||||
|
||||
static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
|
||||
int pin_num,
|
||||
struct regmap **regmap,
|
||||
int *reg, u8 *bit)
|
||||
{
|
||||
struct rockchip_pinctrl_priv *priv = bank->priv;
|
||||
|
||||
*regmap = priv->regmap_base;
|
||||
*reg = RK3308_SCHMITT_GRF_OFFSET;
|
||||
|
||||
*reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
|
||||
*reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
|
||||
*bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3308_set_schmitt(struct rockchip_pin_bank *bank,
|
||||
int pin_num, int enable)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
int reg;
|
||||
u8 bit;
|
||||
u32 data;
|
||||
|
||||
rk3308_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
|
||||
/* enable the write to the equivalent lower bits */
|
||||
data = BIT(bit + 16) | (enable << bit);
|
||||
|
||||
return regmap_write(regmap, reg, data);
|
||||
}
|
||||
|
||||
static struct rockchip_pin_bank rk3308_pin_banks[] = {
|
||||
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_8WIDTH_2BIT),
|
||||
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_8WIDTH_2BIT),
|
||||
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_8WIDTH_2BIT),
|
||||
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_8WIDTH_2BIT),
|
||||
PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_8WIDTH_2BIT,
|
||||
IOMUX_8WIDTH_2BIT),
|
||||
};
|
||||
|
||||
static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
|
||||
.pin_banks = rk3308_pin_banks,
|
||||
.nr_banks = ARRAY_SIZE(rk3308_pin_banks),
|
||||
.grf_mux_offset = 0x0,
|
||||
.iomux_recalced = rk3308_mux_recalced_data,
|
||||
.niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
|
||||
.iomux_routes = rk3308_mux_route_data,
|
||||
.niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
|
||||
.set_mux = rk3308_set_mux,
|
||||
.set_drive = rk3308_set_drive,
|
||||
.set_pull = rk3308_set_pull,
|
||||
.set_schmitt = rk3308_set_schmitt,
|
||||
};
|
||||
|
||||
static const struct udevice_id rk3308_pinctrl_ids[] = {
|
||||
{
|
||||
.compatible = "rockchip,rk3308-pinctrl",
|
||||
.data = (ulong)&rk3308_pin_ctrl
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(pinctrl_rk3308) = {
|
||||
.name = "rockchip_rk3308_pinctrl",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = rk3308_pinctrl_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
|
||||
.ops = &rockchip_pinctrl_ops,
|
||||
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
.bind = dm_scan_fdt_dev,
|
||||
#endif
|
||||
.probe = rockchip_pinctrl_probe,
|
||||
};
|
|
@ -539,7 +539,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d
|
|||
* 4bit iomux'es are spread over two registers.
|
||||
*/
|
||||
inc = (iom->type & (IOMUX_WIDTH_4BIT |
|
||||
IOMUX_WIDTH_3BIT)) ? 8 : 4;
|
||||
IOMUX_WIDTH_3BIT |
|
||||
IOMUX_8WIDTH_2BIT)) ? 8 : 4;
|
||||
if (iom->type & IOMUX_SOURCE_PMU)
|
||||
pmu_offs += inc;
|
||||
else
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#define IOMUX_SOURCE_PMU BIT(2)
|
||||
#define IOMUX_UNROUTED BIT(3)
|
||||
#define IOMUX_WIDTH_3BIT BIT(4)
|
||||
#define IOMUX_8WIDTH_2BIT BIT(5)
|
||||
|
||||
/**
|
||||
* Defined some common pins constants
|
||||
|
|
|
@ -15,22 +15,38 @@
|
|||
#include <asm/arch-rockchip/pwm.h>
|
||||
#include <power/regulator.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
struct rockchip_pwm_data {
|
||||
struct rockchip_pwm_regs regs;
|
||||
unsigned int prescaler;
|
||||
bool supports_polarity;
|
||||
bool supports_lock;
|
||||
u32 enable_conf;
|
||||
u32 enable_conf_mask;
|
||||
};
|
||||
|
||||
struct rk_pwm_priv {
|
||||
struct rk3288_pwm *regs;
|
||||
fdt_addr_t base;
|
||||
ulong freq;
|
||||
uint enable_conf;
|
||||
u32 conf_polarity;
|
||||
const struct rockchip_pwm_data *data;
|
||||
};
|
||||
|
||||
static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
|
||||
{
|
||||
struct rk_pwm_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (!priv->data->supports_polarity) {
|
||||
debug("%s: Do not support polarity\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
debug("%s: polarity=%u\n", __func__, polarity);
|
||||
priv->enable_conf &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
|
||||
if (polarity)
|
||||
priv->enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
|
||||
priv->conf_polarity = PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
|
||||
else
|
||||
priv->enable_conf |= PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
|
||||
priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -39,20 +55,44 @@ static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
|
|||
uint duty_ns)
|
||||
{
|
||||
struct rk_pwm_priv *priv = dev_get_priv(dev);
|
||||
struct rk3288_pwm *regs = priv->regs;
|
||||
const struct rockchip_pwm_regs *regs = &priv->data->regs;
|
||||
unsigned long period, duty;
|
||||
u32 ctrl;
|
||||
|
||||
debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
|
||||
writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
|
||||
PWM_CONTINUOUS | priv->enable_conf |
|
||||
RK_PWM_DISABLE,
|
||||
®s->ctrl);
|
||||
|
||||
period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000);
|
||||
duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000);
|
||||
ctrl = readl(priv->base + regs->ctrl);
|
||||
/*
|
||||
* Lock the period and duty of previous configuration, then
|
||||
* change the duty and period, that would not be effective.
|
||||
*/
|
||||
if (priv->data->supports_lock) {
|
||||
ctrl |= PWM_LOCK;
|
||||
writel(ctrl, priv->base + regs->ctrl);
|
||||
}
|
||||
|
||||
period = lldiv((uint64_t)priv->freq * period_ns,
|
||||
priv->data->prescaler * 1000000000);
|
||||
duty = lldiv((uint64_t)priv->freq * duty_ns,
|
||||
priv->data->prescaler * 1000000000);
|
||||
|
||||
writel(period, priv->base + regs->period);
|
||||
writel(duty, priv->base + regs->duty);
|
||||
|
||||
if (priv->data->supports_polarity) {
|
||||
ctrl &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
|
||||
ctrl |= priv->conf_polarity;
|
||||
}
|
||||
|
||||
/*
|
||||
* Unlock and set polarity at the same time,
|
||||
* the configuration of duty, period and polarity
|
||||
* would be effective together at next period.
|
||||
*/
|
||||
if (priv->data->supports_lock)
|
||||
ctrl &= ~PWM_LOCK;
|
||||
writel(ctrl, priv->base + regs->ctrl);
|
||||
|
||||
writel(period, ®s->period_hpr);
|
||||
writel(duty, ®s->duty_lpr);
|
||||
debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
|
||||
|
||||
return 0;
|
||||
|
@ -61,10 +101,20 @@ static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
|
|||
static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
|
||||
{
|
||||
struct rk_pwm_priv *priv = dev_get_priv(dev);
|
||||
struct rk3288_pwm *regs = priv->regs;
|
||||
const struct rockchip_pwm_regs *regs = &priv->data->regs;
|
||||
u32 ctrl;
|
||||
|
||||
debug("%s: Enable '%s'\n", __func__, dev->name);
|
||||
clrsetbits_le32(®s->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0);
|
||||
|
||||
ctrl = readl(priv->base + regs->ctrl);
|
||||
ctrl &= ~priv->data->enable_conf_mask;
|
||||
|
||||
if (enable)
|
||||
ctrl |= priv->data->enable_conf;
|
||||
else
|
||||
ctrl &= ~priv->data->enable_conf;
|
||||
|
||||
writel(ctrl, priv->base + regs->ctrl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -73,7 +123,7 @@ static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
|
|||
{
|
||||
struct rk_pwm_priv *priv = dev_get_priv(dev);
|
||||
|
||||
priv->regs = (struct rk3288_pwm *)dev_read_addr(dev);
|
||||
priv->base = dev_read_addr(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -89,8 +139,12 @@ static int rk_pwm_probe(struct udevice *dev)
|
|||
debug("%s get clock fail!\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
priv->freq = clk_get_rate(&clk);
|
||||
priv->enable_conf = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE;
|
||||
priv->data = (struct rockchip_pwm_data *)dev_get_driver_data(dev);
|
||||
|
||||
if (priv->data->supports_polarity)
|
||||
priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -101,8 +155,54 @@ static const struct pwm_ops rk_pwm_ops = {
|
|||
.set_enable = rk_pwm_set_enable,
|
||||
};
|
||||
|
||||
static const struct rockchip_pwm_data pwm_data_v1 = {
|
||||
.regs = {
|
||||
.duty = 0x04,
|
||||
.period = 0x08,
|
||||
.cntr = 0x00,
|
||||
.ctrl = 0x0c,
|
||||
},
|
||||
.prescaler = 2,
|
||||
.supports_polarity = false,
|
||||
.supports_lock = false,
|
||||
.enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
|
||||
.enable_conf_mask = BIT(1) | BIT(3),
|
||||
};
|
||||
|
||||
static const struct rockchip_pwm_data pwm_data_v2 = {
|
||||
.regs = {
|
||||
.duty = 0x08,
|
||||
.period = 0x04,
|
||||
.cntr = 0x00,
|
||||
.ctrl = 0x0c,
|
||||
},
|
||||
.prescaler = 1,
|
||||
.supports_polarity = true,
|
||||
.supports_lock = false,
|
||||
.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
|
||||
PWM_CONTINUOUS,
|
||||
.enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
|
||||
};
|
||||
|
||||
static const struct rockchip_pwm_data pwm_data_v3 = {
|
||||
.regs = {
|
||||
.duty = 0x08,
|
||||
.period = 0x04,
|
||||
.cntr = 0x00,
|
||||
.ctrl = 0x0c,
|
||||
},
|
||||
.prescaler = 1,
|
||||
.supports_polarity = true,
|
||||
.supports_lock = true,
|
||||
.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
|
||||
PWM_CONTINUOUS,
|
||||
.enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
|
||||
};
|
||||
|
||||
static const struct udevice_id rk_pwm_ids[] = {
|
||||
{ .compatible = "rockchip,rk3288-pwm" },
|
||||
{ .compatible = "rockchip,rk2928-pwm", .data = (ulong)&pwm_data_v1},
|
||||
{ .compatible = "rockchip,rk3288-pwm", .data = (ulong)&pwm_data_v2},
|
||||
{ .compatible = "rockchip,rk3328-pwm", .data = (ulong)&pwm_data_v3},
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
@ -36,7 +36,7 @@
|
|||
"pxefile_addr_r=0x00600000\0" \
|
||||
"fdt_addr_r=0x01f00000\0" \
|
||||
"kernel_addr_r=0x02080000\0" \
|
||||
"ramdisk_addr_r=0x04000000\0"
|
||||
"ramdisk_addr_r=0x06000000\0"
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
|
|
|
@ -51,7 +51,7 @@
|
|||
"pxefile_addr_r=0x00600000\0" \
|
||||
"fdt_addr_r=0x01f00000\0" \
|
||||
"kernel_addr_r=0x02080000\0" \
|
||||
"ramdisk_addr_r=0x04000000\0"
|
||||
"ramdisk_addr_r=0x06000000\0"
|
||||
|
||||
#ifndef ROCKCHIP_DEVICE_SETTINGS
|
||||
#define ROCKCHIP_DEVICE_SETTINGS
|
||||
|
|
Loading…
Add table
Reference in a new issue