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https://github.com/Fishwaldo/u-boot.git
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mxs: clock: Use 'mxs' prefix for methods
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
parent
14e26bcfa7
commit
bf48fcb61b
8 changed files with 44 additions and 44 deletions
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@ -41,7 +41,7 @@
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#define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000)
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#define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000)
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#define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
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#define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
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static uint32_t mx28_get_pclk(void)
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static uint32_t mxs_get_pclk(void)
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{
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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@ -73,7 +73,7 @@ static uint32_t mx28_get_pclk(void)
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return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
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return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
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}
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}
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static uint32_t mx28_get_hclk(void)
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static uint32_t mxs_get_hclk(void)
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{
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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@ -88,10 +88,10 @@ static uint32_t mx28_get_hclk(void)
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return 0;
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return 0;
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div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
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div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
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return mx28_get_pclk() / div;
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return mxs_get_pclk() / div;
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}
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}
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static uint32_t mx28_get_emiclk(void)
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static uint32_t mxs_get_emiclk(void)
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{
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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@ -116,7 +116,7 @@ static uint32_t mx28_get_emiclk(void)
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return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
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return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
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}
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}
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static uint32_t mx28_get_gpmiclk(void)
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static uint32_t mxs_get_gpmiclk(void)
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{
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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@ -143,7 +143,7 @@ static uint32_t mx28_get_gpmiclk(void)
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/*
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/*
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* Set IO clock frequency, in kHz
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* Set IO clock frequency, in kHz
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*/
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*/
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void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
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void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq)
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{
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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@ -176,7 +176,7 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
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/*
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/*
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* Get IO clock, returns IO clock in kHz
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* Get IO clock, returns IO clock in kHz
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*/
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*/
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static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
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static uint32_t mxs_get_ioclk(enum mxs_ioclock io)
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{
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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@ -197,7 +197,7 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
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/*
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/*
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* Configure SSP clock frequency, in kHz
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* Configure SSP clock frequency, in kHz
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*/
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*/
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void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
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void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
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{
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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@ -216,7 +216,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
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if (xtal)
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if (xtal)
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clk = XTAL_FREQ_KHZ;
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clk = XTAL_FREQ_KHZ;
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else
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else
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clk = mx28_get_ioclk(ssp >> 1);
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clk = mxs_get_ioclk(ssp >> 1);
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if (freq > clk)
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if (freq > clk)
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return;
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return;
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@ -241,7 +241,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
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/*
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/*
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* Return SSP frequency, in kHz
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* Return SSP frequency, in kHz
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*/
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*/
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static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
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static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
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{
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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@ -263,7 +263,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
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if (tmp == 0)
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if (tmp == 0)
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return 0;
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return 0;
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clk = mx28_get_ioclk(ssp >> 1);
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clk = mxs_get_ioclk(ssp >> 1);
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return clk / tmp;
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return clk / tmp;
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}
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}
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@ -271,10 +271,10 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
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/*
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/*
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* Set SSP/MMC bus frequency, in kHz)
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* Set SSP/MMC bus frequency, in kHz)
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*/
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*/
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void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
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void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
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{
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{
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struct mxs_ssp_regs *ssp_regs;
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struct mxs_ssp_regs *ssp_regs;
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const uint32_t sspclk = mx28_get_sspclk(bus);
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const uint32_t sspclk = mxs_get_sspclk(bus);
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uint32_t reg;
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uint32_t reg;
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uint32_t divide, rate, tgtclk;
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uint32_t divide, rate, tgtclk;
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@ -313,26 +313,26 @@ uint32_t mxc_get_clock(enum mxc_clock clk)
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{
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{
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switch (clk) {
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switch (clk) {
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case MXC_ARM_CLK:
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case MXC_ARM_CLK:
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return mx28_get_pclk() * 1000000;
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return mxs_get_pclk() * 1000000;
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case MXC_GPMI_CLK:
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case MXC_GPMI_CLK:
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return mx28_get_gpmiclk() * 1000000;
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return mxs_get_gpmiclk() * 1000000;
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case MXC_AHB_CLK:
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case MXC_AHB_CLK:
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case MXC_IPG_CLK:
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case MXC_IPG_CLK:
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return mx28_get_hclk() * 1000000;
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return mxs_get_hclk() * 1000000;
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case MXC_EMI_CLK:
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case MXC_EMI_CLK:
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return mx28_get_emiclk();
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return mxs_get_emiclk();
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case MXC_IO0_CLK:
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case MXC_IO0_CLK:
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return mx28_get_ioclk(MXC_IOCLK0);
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return mxs_get_ioclk(MXC_IOCLK0);
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case MXC_IO1_CLK:
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case MXC_IO1_CLK:
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return mx28_get_ioclk(MXC_IOCLK1);
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return mxs_get_ioclk(MXC_IOCLK1);
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case MXC_SSP0_CLK:
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case MXC_SSP0_CLK:
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return mx28_get_sspclk(MXC_SSPCLK0);
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return mxs_get_sspclk(MXC_SSPCLK0);
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case MXC_SSP1_CLK:
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case MXC_SSP1_CLK:
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return mx28_get_sspclk(MXC_SSPCLK1);
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return mxs_get_sspclk(MXC_SSPCLK1);
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case MXC_SSP2_CLK:
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case MXC_SSP2_CLK:
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return mx28_get_sspclk(MXC_SSPCLK2);
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return mxs_get_sspclk(MXC_SSPCLK2);
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case MXC_SSP3_CLK:
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case MXC_SSP3_CLK:
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return mx28_get_sspclk(MXC_SSPCLK3);
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return mxs_get_sspclk(MXC_SSPCLK3);
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case MXC_XTAL_CLK:
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case MXC_XTAL_CLK:
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return XTAL_FREQ_KHZ * 1000;
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return XTAL_FREQ_KHZ * 1000;
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}
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}
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@ -52,9 +52,9 @@ enum mxs_sspclock {
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uint32_t mxc_get_clock(enum mxc_clock clk);
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uint32_t mxc_get_clock(enum mxc_clock clk);
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void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq);
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void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
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void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
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void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
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void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq);
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void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
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/* Compatibility with the FEC Ethernet driver */
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/* Compatibility with the FEC Ethernet driver */
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#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK)
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#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK)
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@ -43,12 +43,12 @@ DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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/* IO0 clock at 480MHz */
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/* IO0 clock at 480MHz */
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mx28_set_ioclk(MXC_IOCLK0, 480000);
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mxs_set_ioclk(MXC_IOCLK0, 480000);
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/* IO1 clock at 480MHz */
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/* IO1 clock at 480MHz */
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mx28_set_ioclk(MXC_IOCLK1, 480000);
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mxs_set_ioclk(MXC_IOCLK1, 480000);
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/* SSP0 clock at 96MHz */
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/* SSP0 clock at 96MHz */
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mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
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mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
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return 0;
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return 0;
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}
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}
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@ -43,14 +43,14 @@ DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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/* IO0 clock at 480MHz */
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/* IO0 clock at 480MHz */
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mx28_set_ioclk(MXC_IOCLK0, 480000);
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mxs_set_ioclk(MXC_IOCLK0, 480000);
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/* IO1 clock at 480MHz */
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/* IO1 clock at 480MHz */
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mx28_set_ioclk(MXC_IOCLK1, 480000);
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mxs_set_ioclk(MXC_IOCLK1, 480000);
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/* SSP0 clock at 96MHz */
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/* SSP0 clock at 96MHz */
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mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
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mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
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/* SSP2 clock at 160MHz */
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/* SSP2 clock at 160MHz */
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mx28_set_sspclk(MXC_SSPCLK2, 160000, 0);
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mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
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#ifdef CONFIG_CMD_USB
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#ifdef CONFIG_CMD_USB
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mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
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mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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/* IO0 clock at 480MHz */
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/* IO0 clock at 480MHz */
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mx28_set_ioclk(MXC_IOCLK0, 480000);
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mxs_set_ioclk(MXC_IOCLK0, 480000);
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/* IO1 clock at 480MHz */
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/* IO1 clock at 480MHz */
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mx28_set_ioclk(MXC_IOCLK1, 480000);
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mxs_set_ioclk(MXC_IOCLK1, 480000);
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/* SSP0 clock at 96MHz */
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/* SSP0 clock at 96MHz */
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mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
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mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
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/* SSP2 clock at 160MHz */
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/* SSP2 clock at 160MHz */
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mx28_set_sspclk(MXC_SSPCLK2, 160000, 0);
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mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
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#ifdef CONFIG_CMD_USB
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#ifdef CONFIG_CMD_USB
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mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
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mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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/* IO0 clock at 480MHz */
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/* IO0 clock at 480MHz */
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mx28_set_ioclk(MXC_IOCLK0, 480000);
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mxs_set_ioclk(MXC_IOCLK0, 480000);
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/* IO1 clock at 480MHz */
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/* IO1 clock at 480MHz */
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mx28_set_ioclk(MXC_IOCLK1, 480000);
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mxs_set_ioclk(MXC_IOCLK1, 480000);
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/* SSP0 clock at 96MHz */
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/* SSP0 clock at 96MHz */
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mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
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mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
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/* SSP2 clock at 96MHz */
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/* SSP2 clock at 96MHz */
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mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
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mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
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#ifdef CONFIG_CMD_USB
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#ifdef CONFIG_CMD_USB
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mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT);
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mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT);
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/* Set the clock speed */
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/* Set the clock speed */
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if (mmc->clock)
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if (mmc->clock)
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mx28_set_ssp_busclock(priv->id, mmc->clock / 1000);
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mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
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switch (mmc->bus_width) {
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switch (mmc->bus_width) {
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case 1:
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case 1:
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SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
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SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
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/* Set initial bit clock 400 KHz */
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/* Set initial bit clock 400 KHz */
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mx28_set_ssp_busclock(priv->id, 400);
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mxs_set_ssp_busclock(priv->id, 400);
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/* Send initial 74 clock cycles (185 us @ 400 KHz)*/
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/* Send initial 74 clock cycles (185 us @ 400 KHz)*/
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writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
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writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
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writel(0, &ssp_regs->hw_ssp_cmd0);
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writel(0, &ssp_regs->hw_ssp_cmd0);
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mx28_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
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mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
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return 0;
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return 0;
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}
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}
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