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arm: socfpga: Fix FPGA bitstream programming routine

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In case the FPGA bitstream is aligned to 4 bytes, skip the
part of the assembler which handles unaligned bitstream.
Otherwise, that part will loop indefinitelly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
This commit is contained in:
Marek Vasut 2015-07-27 22:34:54 +02:00
parent ae27120c31
commit bfa89d2ba8
1 changed files with 3 additions and 0 deletions
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3
drivers/fpga/socfpga.c
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@ -160,10 +160,13 @@ static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
" sub %1, #32\n" " sub %1, #32\n"
" subs %2, #1\n" " subs %2, #1\n"
" bne 1b\n" " bne 1b\n"
" cmp %3, #0\n"
" beq 3f\n"
"2: ldr %2, [%0], #4\n" "2: ldr %2, [%0], #4\n"
" str %2, [%1]\n" " str %2, [%1]\n"
" subs %3, #1\n" " subs %3, #1\n"
" bne 2b\n" " bne 2b\n"
"3: nop\n"
: "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) : : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc"); : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
} }