mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-15 19:51:37 +00:00
Merge commit '4720b83d2c711062cfb55f03591b8f12c897d7cb' of https://github.com/tienfong/uboot_mainline
This commit is contained in:
commit
c03942ddc9
6 changed files with 260 additions and 9 deletions
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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* Copyright (C) 2016-2021 Intel Corporation
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*/
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#ifndef _SOCFPGA_MISC_H_
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@ -45,7 +45,12 @@ int is_fpga_config_ready(void);
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#endif
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void do_bridge_reset(int enable, unsigned int mask);
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void force_periph_program(unsigned int status);
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bool is_regular_boot_valid(void);
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bool is_periph_program_force(void);
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void set_regular_boot(unsigned int status);
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void socfpga_pl310_clear(void);
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void socfpga_get_managers_addr(void);
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int qspi_flash_software_reset(void);
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#endif /* _SOCFPGA_MISC_H_ */
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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* Copyright (C) 2016-2021 Intel Corporation
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*/
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#ifndef _RESET_MANAGER_ARRIA10_H_
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@ -22,6 +22,7 @@ int socfpga_bridges_reset(void);
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#define RSTMGR_A10_PER1MODRST 0x28
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#define RSTMGR_A10_BRGMODRST 0x2c
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#define RSTMGR_A10_SYSMODRST 0x30
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#define RSTMGR_A10_SYSWARMMASK 0x50
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#define RSTMGR_CTRL RSTMGR_A10_CTRL
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@ -115,4 +116,7 @@ int socfpga_bridges_reset(void);
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#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK BIT(2)
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#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK BIT(3)
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#define ALT_RSTMGR_FPGAMGRWARMMASK_S2F_SET_MSK BIT(3)
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#define ALT_RSTMGR_SYSWARMMASK_S2F_SET_MSK BIT(4)
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#endif /* _RESET_MANAGER_ARRIA10_H_ */
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
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* Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
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*/
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#ifndef _SYSTEM_MANAGER_ARRIA10_H_
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@ -31,6 +31,11 @@
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#define SYSMGR_A10_NOC_IDLEACK 0xd0
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#define SYSMGR_A10_NOC_IDLESTATUS 0xd4
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#define SYSMGR_A10_FPGA2SOC_CTRL 0xd8
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#define SYSMGR_A10_ROMCODE_CTRL 0x204
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#define SYSMGR_A10_ROMCODE_INITSWSTATE 0x20C
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#define SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND 0x208
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#define SYSMGR_A10_ISW_HANDOFF_BASE 0x230
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#define SYSMGR_A10_ISW_HANDOFF_7 0x1c
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#define SYSMGR_SDMMC SYSMGR_A10_SDMMC
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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* Copyright (C) 2016-2021 Intel Corporation
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*/
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#include <altera.h>
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@ -11,6 +11,7 @@
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#include <miiphy.h>
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#include <netdev.h>
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#include <ns16550.h>
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#include <spi_flash.h>
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#include <watchdog.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/pinmux.h>
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@ -21,6 +22,7 @@
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#include <asm/arch/nic301.h>
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#include <asm/io.h>
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#include <asm/pl310.h>
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#include <linux/sizes.h>
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#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08
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#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
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@ -29,6 +31,13 @@
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#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
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#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
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#define REGULAR_BOOT_MAGIC 0xd15ea5e
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#define PERIPH_RBF_PROG_FORCE 0x50455249
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#define QSPI_S25FL_SOFT_RESET_COMMAND 0x00f0ff82
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#define QSPI_N25_SOFT_RESET_COMMAND 0x00000001
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#define QSPI_NO_SOFT_RESET 0x00000000
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/*
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* FPGA programming support for SoC FPGA Arria 10
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*/
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@ -122,3 +131,118 @@ void do_bridge_reset(int enable, unsigned int mask)
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else
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socfpga_bridges_reset();
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}
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/*
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* This function set/unset flag with number "0x50455249" to
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* handoff register isw_handoff[7] - 0xffd0624c
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* This flag is used to force periph RBF program regardless FPGA status
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* and double periph RBF config are needed on some devices or boards to
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* stabilize the IO config system.
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*/
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void force_periph_program(unsigned int status)
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{
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if (status)
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writel(PERIPH_RBF_PROG_FORCE, socfpga_get_sysmgr_addr() +
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SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
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else
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writel(0, socfpga_get_sysmgr_addr() +
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SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
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}
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/*
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* This function is used to check whether
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* handoff register isw_handoff[7] contains
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* flag for forcing the periph RBF program "0x50455249".
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*/
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bool is_periph_program_force(void)
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{
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unsigned int status;
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status = readl(socfpga_get_sysmgr_addr() +
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SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
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if (status == PERIPH_RBF_PROG_FORCE)
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return true;
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else
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return false;
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}
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/*
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* This function set/unset magic number "0xd15ea5e" to
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* handoff register isw_handoff[7] - 0xffd0624c
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* This magic number is part of boot progress tracking
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* and it's required for warm reset workaround on MPFE hang issue.
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*/
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void set_regular_boot(unsigned int status)
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{
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if (status)
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writel(REGULAR_BOOT_MAGIC, socfpga_get_sysmgr_addr() +
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SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
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else
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writel(0, socfpga_get_sysmgr_addr() +
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SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
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}
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/*
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* This function is used to check whether
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* handoff register isw_handoff[7] contains
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* magic number "0xd15ea5e".
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*/
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bool is_regular_boot_valid(void)
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{
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unsigned int status;
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status = readl(socfpga_get_sysmgr_addr() +
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SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
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if (status == REGULAR_BOOT_MAGIC)
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return true;
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else
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return false;
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}
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#if IS_ENABLED(CONFIG_CADENCE_QSPI)
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/* This function is used to trigger software reset
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* to the QSPI flash. On some boards, the QSPI flash reset may
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* not be connected to the HPS warm reset.
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*/
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int qspi_flash_software_reset(void)
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{
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struct udevice *flash;
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int ret;
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/* Get the flash info */
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ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS,
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CONFIG_SF_DEFAULT_CS,
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CONFIG_SF_DEFAULT_SPEED,
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CONFIG_SF_DEFAULT_MODE,
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&flash);
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if (ret) {
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debug("Failed to initialize SPI flash at ");
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debug("%u:%u (error %d)\n", CONFIG_SF_DEFAULT_BUS,
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CONFIG_SF_DEFAULT_CS, ret);
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return -ENODEV;
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}
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if (!flash)
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return -EINVAL;
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/*
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* QSPI flash software reset command, for the case where
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* no HPS reset connected to QSPI flash reset
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*/
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if (!memcmp(flash->name, "N25", SZ_1 + SZ_2))
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writel(QSPI_N25_SOFT_RESET_COMMAND, socfpga_get_sysmgr_addr() +
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SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND);
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else if (!memcmp(flash->name, "S25FL", SZ_1 + SZ_4))
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writel(QSPI_S25FL_SOFT_RESET_COMMAND,
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socfpga_get_sysmgr_addr() +
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SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND);
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else /* No software reset */
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writel(QSPI_NO_SOFT_RESET, socfpga_get_sysmgr_addr() +
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SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND);
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return 0;
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}
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#endif
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
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* Copyright (C) 2012-2021 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <asm/arch/fpga_manager.h>
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#include <mmc.h>
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#include <memalign.h>
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#include <linux/delay.h>
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#define FPGA_BUFSIZ 16 * 1024
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#define FSBL_IMAGE_IS_VALID 0x49535756
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#define FSBL_IMAGE_IS_INVALID 0x0
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#define BOOTROM_CONFIGURES_IO_PINMUX 0x3
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DECLARE_GLOBAL_DATA_PTR;
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void spl_board_init(void)
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{
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int ret;
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ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
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/* enable console uart printing */
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@ -116,8 +123,7 @@ void spl_board_init(void)
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/* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
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if (is_fpgamgr_user_mode()) {
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int ret = config_pins(gd->fdt_blob, "shared");
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ret = config_pins(gd->fdt_blob, "shared");
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if (ret)
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return;
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@ -127,11 +133,110 @@ void spl_board_init(void)
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} else if (!is_fpgamgr_early_user_mode()) {
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/* Program IOSSM(early IO release) or full FPGA */
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fpgamgr_program(buf, FPGA_BUFSIZ, 0);
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/* Skipping double program for combined RBF */
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if (!is_fpgamgr_user_mode()) {
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/*
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* Expect FPGA entered early user mode, so
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* the flag is set to re-program IOSSM
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*/
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force_periph_program(true);
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/* Re-program IOSSM to stabilize IO system */
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fpgamgr_program(buf, FPGA_BUFSIZ, 0);
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force_periph_program(false);
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}
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}
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/* If the IOSSM/full FPGA is already loaded, start DDR */
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if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
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if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode()) {
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if (!is_regular_boot_valid()) {
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/*
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* Ensure all signals in stable state before triggering
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* warm reset. This value is recommended from stress
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* test.
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*/
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mdelay(10);
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#if IS_ENABLED(CONFIG_CADENCE_QSPI)
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/*
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* Trigger software reset to QSPI flash.
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* On some boards, the QSPI flash reset may not be
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* connected to the HPS warm reset.
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*/
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qspi_flash_software_reset();
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#endif
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ret = readl(socfpga_get_rstmgr_addr() +
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RSTMGR_A10_SYSWARMMASK);
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/*
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* Masking s2f & FPGA manager module reset from warm
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* reset
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*/
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writel(ret & (~(ALT_RSTMGR_SYSWARMMASK_S2F_SET_MSK |
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ALT_RSTMGR_FPGAMGRWARMMASK_S2F_SET_MSK)),
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socfpga_get_rstmgr_addr() +
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RSTMGR_A10_SYSWARMMASK);
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/*
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* BootROM will configure both IO and pin mux after a
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* warm reset
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*/
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ret = readl(socfpga_get_sysmgr_addr() +
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SYSMGR_A10_ROMCODE_CTRL);
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writel(ret | BOOTROM_CONFIGURES_IO_PINMUX,
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socfpga_get_sysmgr_addr() +
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SYSMGR_A10_ROMCODE_CTRL);
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/*
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* Up to here, image is considered valid and should be
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* set as valid before warm reset is triggered
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*/
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writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() +
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SYSMGR_A10_ROMCODE_INITSWSTATE);
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/*
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* Set this flag to scratch register, so that a proper
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* boot progress before / after warm reset can be
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* tracked by FSBL
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*/
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set_regular_boot(true);
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WATCHDOG_RESET();
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reset_cpu();
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}
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/*
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* Reset this flag to scratch register, so that a proper
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* boot progress before / after warm reset can be
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* tracked by FSBL
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*/
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set_regular_boot(false);
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ret = readl(socfpga_get_rstmgr_addr() +
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RSTMGR_A10_SYSWARMMASK);
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/*
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* Unmasking s2f & FPGA manager module reset from warm
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* reset
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*/
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writel(ret | ALT_RSTMGR_SYSWARMMASK_S2F_SET_MSK |
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ALT_RSTMGR_FPGAMGRWARMMASK_S2F_SET_MSK,
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socfpga_get_rstmgr_addr() + RSTMGR_A10_SYSWARMMASK);
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/*
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* Up to here, MPFE hang workaround is considered done and
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* should be reset as invalid until FSBL successfully loading
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* SSBL, and prepare jumping to SSBL, then only setting as
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* valid
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*/
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writel(FSBL_IMAGE_IS_INVALID, socfpga_get_sysmgr_addr() +
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SYSMGR_A10_ROMCODE_INITSWSTATE);
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ddr_calibration_sequence();
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}
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if (!is_fpgamgr_user_mode())
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fpgamgr_program(buf, FPGA_BUFSIZ, 0);
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@ -169,3 +274,10 @@ void board_init_f(ulong dummy)
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config_dedicated_pins(gd->fdt_blob);
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WATCHDOG_RESET();
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}
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/* board specific function prior loading SSBL / U-Boot proper */
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void spl_board_prepare_for_boot(void)
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{
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writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() +
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SYSMGR_A10_ROMCODE_INITSWSTATE);
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}
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@ -604,7 +604,8 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,
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if (strstr(uname, "fpga-periph") &&
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(!is_fpgamgr_early_user_mode() ||
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is_fpgamgr_user_mode())) {
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is_fpgamgr_user_mode() ||
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is_periph_program_force())) {
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fpga_node_name = uname;
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printf("FPGA: Start to program ");
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printf("peripheral/full bitstream ...\n");
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