mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-19 05:31:32 +00:00
ARM: rmobile: Fix CPGW address on V3M Eagle
Fix the CPGWPR/CPGWPCR register address on V3M Eagle to unlock access to the CPG clock control registers. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
parent
6d82ed8d37
commit
c267952c41
1 changed files with 4 additions and 3 deletions
|
@ -26,8 +26,8 @@
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
#define CPGWPR 0xE6150900
|
||||||
#define CPGWPCR 0xE6150904
|
#define CPGWPCR 0xE6150904
|
||||||
#define CPGWPR 0xE615090C
|
|
||||||
|
|
||||||
/* PLL */
|
/* PLL */
|
||||||
#define PLL0CR 0xE61500D8
|
#define PLL0CR 0xE61500D8
|
||||||
|
@ -54,8 +54,9 @@ void s_init(void)
|
||||||
|
|
||||||
int board_early_init_f(void)
|
int board_early_init_f(void)
|
||||||
{
|
{
|
||||||
writel(0xA5A5FFFF, CPGWPCR);
|
/* Unlock CPG access */
|
||||||
writel(0x5A5A0000, CPGWPR);
|
writel(0xA5A5FFFF, CPGWPR);
|
||||||
|
writel(0x5A5A0000, CPGWPCR);
|
||||||
|
|
||||||
/* TMU0 */
|
/* TMU0 */
|
||||||
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
|
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
|
||||||
|
|
Loading…
Add table
Reference in a new issue