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arm: socfpga: Add clock manager for Intel N5X device
Add clock manager for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
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3 changed files with 94 additions and 0 deletions
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arch/arm/mach-socfpga/clock_manager_n5x.c
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arch/arm/mach-socfpga/clock_manager_n5x.c
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
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*
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*/
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#include <common.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/system_manager.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <clk.h>
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#include <dm.h>
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#include <dt-bindings/clock/n5x-clock.h>
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#include <malloc.h>
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DECLARE_GLOBAL_DATA_PTR;
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static ulong cm_get_rate_dm(u32 id)
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{
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struct udevice *dev;
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struct clk clk;
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ulong rate;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(socfpga_n5x_clk),
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&dev);
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if (ret)
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return 0;
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clk.id = id;
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ret = clk_request(dev, &clk);
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if (ret < 0)
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return 0;
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rate = clk_get_rate(&clk);
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clk_free(&clk);
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if ((rate == (unsigned long)-ENXIO) ||
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(rate == (unsigned long)-EIO)) {
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debug("%s id %u: clk_get_rate err: %ld\n",
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__func__, id, rate);
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return 0;
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}
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return rate;
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}
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static u32 cm_get_rate_dm_khz(u32 id)
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{
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return cm_get_rate_dm(id) / 1000;
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}
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unsigned long cm_get_mpu_clk_hz(void)
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{
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return cm_get_rate_dm(N5X_MPU_CLK);
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}
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unsigned int cm_get_l4_sys_free_clk_hz(void)
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{
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return cm_get_rate_dm(N5X_L4_SYS_FREE_CLK);
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}
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void cm_print_clock_quick_summary(void)
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{
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printf("MPU %10d kHz\n",
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cm_get_rate_dm_khz(N5X_MPU_CLK));
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printf("L4 Main %8d kHz\n",
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cm_get_rate_dm_khz(N5X_L4_MAIN_CLK));
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printf("L4 sys free %8d kHz\n",
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cm_get_rate_dm_khz(N5X_L4_SYS_FREE_CLK));
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printf("L4 MP %8d kHz\n",
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cm_get_rate_dm_khz(N5X_L4_MP_CLK));
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printf("L4 SP %8d kHz\n",
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cm_get_rate_dm_khz(N5X_L4_SP_CLK));
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printf("SDMMC %8d kHz\n",
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cm_get_rate_dm_khz(N5X_SDMMC_CLK));
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}
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@ -28,6 +28,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
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#include <asm/arch/clock_manager_s10.h>
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#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
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#include <asm/arch/clock_manager_agilex.h>
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#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
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#include <asm/arch/clock_manager_n5x.h>
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#endif
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#endif /* _CLOCK_MANAGER_H_ */
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arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
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arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
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*/
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#ifndef _CLOCK_MANAGER_N5X_
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#define _CLOCK_MANAGER_N5X_
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#include <asm/arch/clock_manager_soc64.h>
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#include "../../../../../drivers/clk/altera/clk-n5x.h"
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#endif /* _CLOCK_MANAGER_N5X_ */
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