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armv7: integrate cache maintenance support
- Enable I-cache on bootup - Enable MMU and D-cache immediately after relocation - Do necessary initialization before enabling d-cache and MMU - Changes to cleanup_before_linux() - Make changes according to the new framework Signed-off-by: Aneesh V <aneesh@ti.com>
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parent
e47f2db537
commit
c2dd0d4554
5 changed files with 51 additions and 32 deletions
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@ -35,13 +35,10 @@
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#include <command.h>
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#include <command.h>
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#include <asm/system.h>
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#include <asm/system.h>
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#include <asm/cache.h>
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#include <asm/cache.h>
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#include <asm/armv7.h>
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static void cache_flush(void);
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int cleanup_before_linux(void)
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int cleanup_before_linux(void)
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{
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{
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unsigned int i;
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/*
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/*
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* this function is called just before we call linux
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* this function is called just before we call linux
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* it prepares the processor for linux
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* it prepares the processor for linux
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@ -50,31 +47,29 @@ int cleanup_before_linux(void)
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*/
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*/
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disable_interrupts();
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disable_interrupts();
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/* turn off I/D-cache */
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/*
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* Turn off I-cache and invalidate it
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*/
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icache_disable();
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icache_disable();
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invalidate_icache_all();
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/*
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* turn off D-cache
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* dcache_disable() in turn flushes the d-cache and disables MMU
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*/
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dcache_disable();
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dcache_disable();
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/* invalidate I-cache */
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/*
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cache_flush();
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* After D-cache is flushed and before it is disabled there may
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* be some new valid entries brought into the cache. We are sure
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#ifndef CONFIG_L2_OFF
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* that these lines are not dirty and will not affect our execution.
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/* turn off L2 cache */
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* (because unwinding the call-stack and setting a bit in CP15 SCTRL
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l2_cache_disable();
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* is all we did during this. We have not pushed anything on to the
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/* invalidate L2 cache also */
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* stack. Neither have we affected any static data)
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invalidate_dcache(get_device_type());
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* So just invalidate the entire d-cache again to avoid coherency
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#endif
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* problems for kernel
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i = 0;
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*/
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/* mem barrier to sync up things */
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invalidate_dcache_all();
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asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
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#ifndef CONFIG_L2_OFF
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l2_cache_enable();
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#endif
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return 0;
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return 0;
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}
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}
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static void cache_flush(void)
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{
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asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
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}
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@ -255,6 +255,14 @@ clbss_l:str r2, [r0] /* clear loop... */
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* initialization, now running from RAM.
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* initialization, now running from RAM.
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*/
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*/
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jump_2_ram:
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jump_2_ram:
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/*
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* If I-cache is enabled invalidate it
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*/
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#ifndef CONFIG_SYS_ICACHE_OFF
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mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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#endif
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ldr r0, _board_init_r_ofs
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ldr r0, _board_init_r_ofs
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adr r1, _start
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adr r1, _start
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add lr, r0, r1
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add lr, r0, r1
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@ -290,6 +298,9 @@ cpu_init_crit:
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mov r0, #0 @ set up for MCR
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mov r0, #0 @ set up for MCR
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
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mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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/*
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/*
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* disable MMU stuff and caches
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* disable MMU stuff and caches
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@ -298,7 +309,12 @@ cpu_init_crit:
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bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
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bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
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bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
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bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
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orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
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orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
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orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
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orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
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#ifdef CONFIG_SYS_ICACHE_OFF
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bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
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#else
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
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#endif
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mcr p15, 0, r0, c1, c0, 0
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mcr p15, 0, r0, c1, c0, 0
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/*
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/*
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@ -450,6 +450,12 @@ void board_init_r (gd_t *id, ulong dest_addr)
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gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
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gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
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monitor_flash_len = _end_ofs;
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monitor_flash_len = _end_ofs;
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/*
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* Enable D$:
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* I$, if needed, must be already enabled in start.S
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*/
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dcache_enable();
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debug ("monitor flash len: %08lX\n", monitor_flash_len);
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debug ("monitor flash len: %08lX\n", monitor_flash_len);
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board_init(); /* Setup chipselects */
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board_init(); /* Setup chipselects */
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@ -34,6 +34,12 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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void __arm_init_before_mmu(void)
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{
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}
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void arm_init_before_mmu(void)
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__attribute__((weak, alias("__arm_init_before_mmu")));
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static void cp_delay (void)
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static void cp_delay (void)
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{
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{
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volatile int i;
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volatile int i;
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@ -65,6 +71,7 @@ static inline void mmu_setup(void)
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int i;
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int i;
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u32 reg;
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u32 reg;
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arm_init_before_mmu();
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/* Set up an identity-mapping for all 4GB, rw for everyone */
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/* Set up an identity-mapping for all 4GB, rw for everyone */
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for (i = 0; i < 4096; i++)
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for (i = 0; i < 4096; i++)
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page_table[i] = i << 20 | (3 << 10) | 0x12;
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page_table[i] = i << 20 | (3 << 10) | 0x12;
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@ -37,11 +37,6 @@ void __flush_cache(unsigned long start, unsigned long size)
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asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
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asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
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/* disable write buffer as well (page 2-22) */
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/* disable write buffer as well (page 2-22) */
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asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
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asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
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#endif
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#ifdef CONFIG_OMAP34XX
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void v7_flush_cache_all(void);
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v7_flush_cache_all();
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#endif
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#endif
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return;
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return;
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}
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}
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