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https://github.com/Fishwaldo/u-boot.git
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arm: pxa: Add support for ICP DAS LP-8x4x
LP-8x4x is a programmable automation controller by ICP DAS. It is shipped with outdated U-Boot v1.3.0 This patch adds enough supports to boot the board: - 128M of 128M SDRAM - 32M of 48M NOR Flash memory - 1 of 4 Serial consoles (PXA FFUART) - 2 of 2 Ethernet controllers (DM9000) Signed-off-by: Sergey Yanovich <ynvich@gmail.com> Series-to: u-boot Series-cc: marex
This commit is contained in:
Sergey Yanovich
Marek Vasut
parent
58bb8f5f61
commit
c3442c1e32
5 changed files with 455 additions and 0 deletions
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@ -1074,6 +1074,10 @@ Alison Wang <b18965@freescale.com>
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vf610twr VF610
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Sergey Yanovich <ynvich@gmail.com>
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lp8x4x xscale/pxa
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-------------------------------------------------------------------------
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Unknown / orphaned boards:
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41
board/icpdas/lp8x4x/Makefile
Normal file
41
board/icpdas/lp8x4x/Makefile
Normal file
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@ -0,0 +1,41 @@
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#
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# ICPDAS LP-8x4x Support
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#
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# Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := lp8x4x.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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147
board/icpdas/lp8x4x/lp8x4x.c
Normal file
147
board/icpdas/lp8x4x/lp8x4x.c
Normal file
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@ -0,0 +1,147 @@
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/*
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* ICP DAS LP-8x4x Support
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*
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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* adapted from Voipac PXA270 Support by
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* Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/regs-mmc.h>
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#include <asm/arch/pxa.h>
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#include <netdev.h>
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#include <serial.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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/* We have RAM, disable cache */
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dcache_disable();
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icache_disable();
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/* memory and cpu-speed are setup before relocation */
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/* so we do _nothing_ here */
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0xa0000100;
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return 0;
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}
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int dram_init(void)
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{
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pxa2xx_dram_init();
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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}
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#ifdef CONFIG_CMD_MMC
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int board_mmc_init(bd_t *bis)
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{
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pxa_mmc_register(0);
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return 0;
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}
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#endif
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#ifdef CONFIG_CMD_USB
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int usb_board_init(void)
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{
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writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
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~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
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UHCHR);
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writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
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while (readl(UHCHR) & UHCHR_FSBIR)
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continue; /* required by checkpath.pl */
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writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
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writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
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/* Clear any OTG Pin Hold */
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if (readl(PSSR) & PSSR_OTGPH)
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writel(readl(PSSR) | PSSR_OTGPH, PSSR);
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writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
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writel(readl(UHCRHDA) | 0x100, UHCRHDA);
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/* Set port power control mask bits, only 3 ports. */
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writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
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/* enable port 2 */
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writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
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UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
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return 0;
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}
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void usb_board_init_fail(void)
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{
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return;
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}
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void usb_board_stop(void)
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{
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writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
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udelay(11);
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writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
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writel(readl(UHCCOMS) | 1, UHCCOMS);
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udelay(10);
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writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
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return;
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}
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#endif
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#ifdef CONFIG_DRIVER_DM9000
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void lp8x4x_eth1_mac_init(void)
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{
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u8 eth1addr[8];
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int i;
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u8 reg;
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eth_getenv_enetaddr_by_index("eth", 1, eth1addr);
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if (!is_valid_ether_addr(eth1addr))
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return;
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for (i = 0, reg = 0x10; i < 6; i++, reg++) {
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writeb(reg, (u8 *)(DM9000_IO_2));
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writeb(eth1addr[i], (u8 *)(DM9000_DATA_2));
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}
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}
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int board_eth_init(bd_t *bis)
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{
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lp8x4x_eth1_mac_init();
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return dm9000_initialize(bis);
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}
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#endif
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@ -348,6 +348,7 @@ pdnb3 arm ixp pdnb3 prodriv
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scpu arm ixp pdnb3 prodrive - pdnb3:SCPU
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balloon3 arm pxa
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h2200 arm pxa
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lp8x4x arm pxa lp8x4x icpdas
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lubbock arm pxa
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palmld arm pxa
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palmtc arm pxa
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262
include/configs/lp8x4x.h
Normal file
262
include/configs/lp8x4x.h
Normal file
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@ -0,0 +1,262 @@
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/*
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* ICP DAS LP-8x4x configuration file
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*
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* Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Board Configuration Options
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*/
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#define CONFIG_CPU_PXA27X /* Marvell PXA270 CPU */
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#define MACH_TYPE_LP8X4X 4539 /* ICP DAS LP-8x4x */
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#define CONFIG_MACH_TYPE MACH_TYPE_LP8X4X
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#define CONFIG_SYS_MALLOC_LEN (128*1024)
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_BOOTCOMMAND \
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"bootm 80000;"
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#define CONFIG_BOOTARGS \
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"console=ttySA0,115200 mem=128M root=/dev/mmcblk0p1 rw" \
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"init=/sbin/init rootfstype=ext3"
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#define CONFIG_TIMESTAMP
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#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_LZMA /* LZMA compression support */
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#undef CONFIG_OF_LIBFDT
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/*
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* Serial Console Configuration
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*/
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#define CONFIG_PXA_SERIAL
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#define CONFIG_FFUART 1
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#define CONFIG_CONS_INDEX 3
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#define CONFIG_BAUDRATE 115200
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/*
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* Bootloader Components Configuration
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_ENV
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#undef CONFIG_CMD_IMLS
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_USB
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#undef CONFIG_LCD
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#undef CONFIG_CMD_IDE
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/*
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* Networking Configuration
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* chip on the ICPDAS LINPAC board
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*/
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#ifdef CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_DRIVER_DM9000 1
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#define CONFIG_DM9000_BASE 0x0C000000
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#define DM9000_IO 0x0C000000
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#define DM9000_DATA 0x0C004000
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#define DM9000_IO_2 0x0D000000
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#define DM9000_DATA_2 0x0D004000
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#define CONFIG_NET_RETRY_COUNT 10
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#endif
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/*
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* MMC Card Configuration
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*/
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#ifdef CONFIG_CMD_MMC
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_PXA_MMC_GENERIC
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_EXT2
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#define CONFIG_DOS_PARTITION
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#endif
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/*
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* KGDB
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*/
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* HUSH Shell Configuration
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*/
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#define CONFIG_SYS_HUSH_PARSER 1
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#undef CONFIG_SYS_LONGHELP
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT "$ "
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#else
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#define CONFIG_SYS_PROMPT "=> "
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#endif
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_DEVICE_NULLDEV 1
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_AUTO_COMPLETE 1
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/*
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* Clock Configuration
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*/
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#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */
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/*
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* DRAM Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
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#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
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#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */
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#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0xa0008000
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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/* Use first 64kb bank of the internal SRAM */
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#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
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/*
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* NOR FLASH
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*/
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#define CONFIG_SYS_MONITOR_BASE 0x0
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#define CONFIG_SYS_MONITOR_LEN 0x40000
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SIZE 0x40000
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#define CONFIG_ENV_SECT_SIZE 0x40000
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
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#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
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#define CONFIG_SYS_FLASH_PROTECTION 1
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#define CONFIG_ENV_IS_IN_FLASH 1
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/*
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* GPIO settings
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*/
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#define CONFIG_SYS_GPSR0_VAL 0x0808c014
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#define CONFIG_SYS_GPSR1_VAL 0x00cf0002
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#define CONFIG_SYS_GPSR2_VAL 0x0221c000
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#define CONFIG_SYS_GPSR3_VAL 0x00020000
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#define CONFIG_SYS_GPCR0_VAL 0x00000000
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#define CONFIG_SYS_GPCR1_VAL 0x0000ab80
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#define CONFIG_SYS_GPCR2_VAL 0x00100000
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#define CONFIG_SYS_GPCR3_VAL 0x0
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#define CONFIG_SYS_GPDR0_VAL 0xc0e9ddf4
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#define CONFIG_SYS_GPDR1_VAL 0xfcffab83
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#define CONFIG_SYS_GPDR2_VAL 0x02f1ffff
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#define CONFIG_SYS_GPDR3_VAL 0x00021b81
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#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
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#define CONFIG_SYS_GAFR0_U_VAL 0xa5e54018
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#define CONFIG_SYS_GAFR1_L_VAL 0x999a955a
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#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a
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#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
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#define CONFIG_SYS_GAFR2_U_VAL 0x55f0a402
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#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c
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#define CONFIG_SYS_GAFR3_U_VAL 0x00001599
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#define CONFIG_SYS_PSSR_VAL 0x32
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/*
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* Clock settings
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*/
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#define CONFIG_SYS_CKEN 0x005002c0
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#define CONFIG_SYS_CCCR 0x02000290
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#define CONFIG_SYS_CLKCFG 0x0000000b
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/*
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* Memory settings
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*/
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#define CONFIG_SYS_MSC0_VAL 0x2bd8aad2
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#define CONFIG_SYS_MSC1_VAL 0xb8c9b8dc
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#define CONFIG_SYS_MSC2_VAL 0xfff9b8c9
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#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
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#define CONFIG_SYS_MDREFR_VAL 0x2093e018
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#define CONFIG_SYS_MDCNFG_VAL 0x890009d1
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#define CONFIG_SYS_MDMRS_VAL 0x00220022
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#define CONFIG_SYS_SXCNFG_VAL 0x40044004
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/*
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* PCMCIA and CF Interfaces
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||||
*/
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#define CONFIG_SYS_MECR_VAL 0x00000001
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#define CONFIG_SYS_MCMEM0_VAL 0x0000c497
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#define CONFIG_SYS_MCMEM1_VAL 0x0000c497
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#define CONFIG_SYS_MCATT0_VAL 0x0000c497
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#define CONFIG_SYS_MCATT1_VAL 0x0000c497
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#define CONFIG_SYS_MCIO0_VAL 0x00008407
|
||||
#define CONFIG_SYS_MCIO1_VAL 0x00008407
|
||||
|
||||
/*
|
||||
* LCD
|
||||
*/
|
||||
#ifdef CONFIG_LCD
|
||||
#define CONFIG_VOIPAC_LCD
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_OHCI_NEW
|
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT
|
||||
#define CONFIG_SYS_USB_OHCI_BOARD_INIT
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lp8x4x"
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Add table
Reference in a new issue