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Patch by Detlev Zundel, 14 Mar 2005:
NC650: changed NAND flash addressing to using UPMB
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3 changed files with 51 additions and 6 deletions
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@ -2,7 +2,10 @@
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Changes for U-Boot 1.1.3:
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Changes for U-Boot 1.1.3:
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======================================================================
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======================================================================
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* Patch by Stefan Roese, 14 March 2005:
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* Patch by Detlev Zundel, 14 Mar 2005:
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NC650: changed NAND flash addressing to using UPMB
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* Patch by Stefan Roese, 14 Mar 2005:
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Update for esd voh405 fpga image
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Update for esd voh405 fpga image
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* INKA4x0: Allow initialization of LCD backlight dimming from
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* INKA4x0: Allow initialization of LCD backlight dimming from
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@ -10,7 +13,7 @@ Changes for U-Boot 1.1.3:
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* Add port initialization for digital I/O on INKA4x0
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* Add port initialization for digital I/O on INKA4x0
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* Patch by Stefan Roese, 01 March 2005:
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* Patch by Stefan Roese, 01 Mar 2005:
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Update for esd boards dp405 and hub405
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Update for esd boards dp405 and hub405
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* Fix get_partition_info() parameter error in all other calls
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* Fix get_partition_info() parameter error in all other calls
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@ -18,7 +21,7 @@ Changes for U-Boot 1.1.3:
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* Enable USB and IDE support for INKA4x0 board
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* Enable USB and IDE support for INKA4x0 board
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* Patch by Andrew Dyer, 28 February 2005:
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* Patch by Andrew Dyer, 28 Feb 2005:
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fix ext2load passing an incorrect pointer to get_partition_info()
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fix ext2load passing an incorrect pointer to get_partition_info()
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resulting in load failure for devices other than 0
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resulting in load failure for devices other than 0
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@ -70,6 +70,36 @@ const uint sdram_table[] = {
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0x7ffffc07, _not_used_, _not_used_, _not_used_
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0x7ffffc07, _not_used_, _not_used_, _not_used_
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};
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};
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const uint nand_flash_table[] = {
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/* single read. (offset 0 in upm RAM) */
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0x0ff3fc04, 0x0ff3fc04, 0x0ff3fc04, 0x0ffffc04,
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0xfffffc00, 0xfffffc05, 0xfffffc05, 0xfffffc05,
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/* burst read. (offset 8 in upm RAM) */
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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/* single write. (offset 18 in upm RAM) */
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0x00fffc04, 0x00fffc04, 0x00fffc04, 0x0ffffc04,
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0x0ffffc84, 0x0ffffc84, 0xfffffc00, 0xfffffc05,
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/* burst write. (offset 20 in upm RAM) */
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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/* refresh. (offset 30 in upm RAM) */
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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/* exception. (offset 3c in upm RAM) */
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05
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};
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/* ------------------------------------------------------------------------- */
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/* ------------------------------------------------------------------------- */
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/*
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/*
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@ -182,6 +212,12 @@ long int initdram (int board_type)
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udelay (10000);
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udelay (10000);
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/* Configure UPMB for NAND flash access */
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upmconfig (UPMB, (uint *) nand_flash_table,
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sizeof (nand_flash_table) / sizeof (uint));
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memctl->memc_mbmr = CFG_MBMR_NAND;
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return (size_b0);
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return (size_b0);
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}
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}
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@ -309,7 +309,7 @@
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
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/*
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/*
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* BR2 and OR2 (NAND Flash)
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* BR2 and OR2 (NAND Flash) - now addressed through UPMB
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*/
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*/
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#define CFG_NAND_BASE 0x50000000
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#define CFG_NAND_BASE 0x50000000
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#define CFG_NAND_SIZE 0x04000000
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#define CFG_NAND_SIZE 0x04000000
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@ -317,8 +317,8 @@
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#define CFG_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
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#define CFG_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
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OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
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OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
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#define CFG_BR2_PRELIM ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
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#define CFG_BR2_PRELIM ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V )
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#define CFG_OR2_PRELIM (((-CFG_NAND_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_NAND)
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#define CFG_OR2_PRELIM (((-CFG_NAND_SIZE) & OR_AM_MSK) | OR_BI )
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/*
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/*
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* BR3 and OR3 (SDRAM)
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* BR3 and OR3 (SDRAM)
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@ -382,6 +382,12 @@
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MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
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MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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/*
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* MBMR settings for NAND flash
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*/
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#define CFG_MBMR_NAND ( MBMR_WLFB_5X )
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/*
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/*
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* Internal Definitions
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* Internal Definitions
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*
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*
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