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am33xx: Document what we're doing with ddrctrl->ddrckectrl

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- Remove the call to set ddrctrl->ddrioctrl as it's all zeros.
- Comment what we're really setting in ddrctrl->ddrckectrl which is that
  we're operating in the normal mode where EMIF/PHY clock is controlled
  by the PHY.

Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Tom Rini 2012-07-24 14:03:24 -07:00 • committed by Albert ARIBAUD
parent 7d8a961d31
commit c48c895433
2 changed files with 3 additions and 4 deletions
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6
arch/arm/cpu/armv7/am33xx/emif4.c
View file

@ -170,10 +170,8 @@ void config_ddr(short ddr_type)
config_io_ctrl(&ioctrl); config_io_ctrl(&ioctrl);
writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, /* Set CKE to be controlled by EMIF/DDR PHY */
&ddrctrl->ddrioctrl); writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
writel(readl(&ddrctrl->ddrckectrl) | 0x00000001,
&ddrctrl->ddrckectrl);
config_emif_ddr2(); config_emif_ddr2();
} }

1
arch/arm/include/asm/arch-am33xx/ddr_defs.h
View file

@ -28,6 +28,7 @@
#define CMD_FORCE 0x00 #define CMD_FORCE 0x00
#define CMD_DELAY 0x00 #define CMD_DELAY 0x00
#define PHY_DLL_LOCK_DIFF 0x0 #define PHY_DLL_LOCK_DIFF 0x0
#define DDR_CKE_CTRL_NORMAL 0x1
#define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */ #define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */
#define DDR2_EMIF_TIM1 0x0666B3C9 #define DDR2_EMIF_TIM1 0x0666B3C9