From dd1c5523d6f44e842e69f2fcb50788c6060eab86 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 1 Jul 2008 17:03:19 +0200 Subject: [PATCH 1/5] ppc4xx: Fix 460EX/GT PCIe port initialization This patch fixes a bug where the 460EX/GT PCIe UTLSET1 register was configured incorrectly. Thanks to Olga Buchonina from AMCC for pointing this out. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_pcie.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 503facca30..d50a538e38 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -615,22 +615,20 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport) #if defined(CONFIG_460EX) || defined(CONFIG_460GT) int __ppc4xx_init_pcie_port_hw(int port, int rootport) { - u32 val = 1 << 24; + u32 val; u32 utlset1; - if (rootport) { + if (rootport) val = PTYPE_ROOT_PORT << 20; - utlset1 = 0x21222222; - } else { + else val = PTYPE_LEGACY_ENDPOINT << 20; - utlset1 = 0x20222222; - } if (port == 0) { val |= LNKW_X1 << 12; + utlset1 = 0x20000000; } else { val |= LNKW_X4 << 12; - utlset1 |= 0x00101101; + utlset1 = 0x20101101; } SDR_WRITE(SDRN_PESDR_DLPSET(port), val); From 47ce4a28ccfcfb803aa68d3d4505a8de056a8a5e Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Sat, 14 Jun 2008 16:53:02 -0400 Subject: [PATCH 2/5] ppc4xx: Update and add FDT to Korat board support Signed-off-by: Larry Johnson Signed-off-by: Stefan Roese --- board/korat/korat.c | 44 ++++++++++++++++++++++++++++++++++++++--- include/configs/korat.h | 10 +++++++--- 2 files changed, 48 insertions(+), 6 deletions(-) diff --git a/board/korat/korat.c b/board/korat/korat.c index a7b4b27c6d..dc977242ba 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -26,12 +26,15 @@ */ #include +#include #include +#include #include -#include -#include -#include #include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -604,6 +607,16 @@ int testdram(void) } #endif /* defined(CFG_DRAM_TEST) */ +#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) +/* + * Assign interrupts to PCI devices. + */ +void korat_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2); +} +#endif + /* * pci_pre_init * @@ -654,6 +667,10 @@ int pci_pre_init(struct pci_controller *hose) addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; mtdcr(plb1_acr, addr); +#if defined(CONFIG_PCI_PNP) + hose->fixup_irq = korat_pci_fixup_irq; +#endif + return 1; } #endif /* defined(CONFIG_PCI) */ @@ -779,3 +796,24 @@ int post_hotkeys_pressed(void) return 0; /* No hotkeys supported */ } #endif /* CONFIG_POST */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 1; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize - CFG_FLASH0_SIZE; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/include/configs/korat.h b/include/configs/korat.h index 765566697f..e2610be933 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -129,7 +129,7 @@ #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_FLASH1_TOP - CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE) @@ -185,7 +185,7 @@ #define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" /* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ CFG_BOOTFILE \ CFG_ROOTPATH \ "netdev=eth0\0" \ @@ -216,7 +216,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_IBM_EMAC4_V4 1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */ #define CONFIG_PHY_DYNAMIC_ANEG 1 @@ -548,4 +548,8 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ From cf1c2ed91df26903b956948f37f82de9e1158a89 Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Sat, 14 Jun 2008 17:02:49 -0400 Subject: [PATCH 3/5] ppc4xx: Remove implementation of testdram() from Korat board support Signed-off-by: Larry Johnson Signed-off-by: Stefan Roese --- board/korat/korat.c | 38 -------------------------------------- include/configs/korat.h | 1 - 2 files changed, 39 deletions(-) diff --git a/board/korat/korat.c b/board/korat/korat.c index dc977242ba..51874ea8db 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -569,44 +569,6 @@ int checkboard(void) return 0; } -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - /* TODO: find correct size of SDRAM */ - for (k = 0; k < CFG_MBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) - printf("%3d MB\r", k / 1024); - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; -} -#endif /* defined(CFG_DRAM_TEST) */ - #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) /* * Assign interrupts to PCI devices. diff --git a/include/configs/korat.h b/include/configs/korat.h index e2610be933..4ca4ed0066 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -145,7 +145,6 @@ #define CONFIG_DDR_ECC /* Use ECC when available */ #define SPD_EEPROM_ADDRESS {0x50} #define CONFIG_PROG_SDRAM_TLB -#define CFG_DRAM_TEST #define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ /* 440EPx errata CHIP 11 */ From 5d812b8b4ad9667c77a5bf92b4ba81699abc9fc3 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 9 Jul 2008 17:33:57 +0200 Subject: [PATCH 4/5] ppc4xx: Enable support for > 2GB SDRAM on AMCC Katmai Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM. To support such configurations, we "only" map the first 2GB via the TLB's. We need some free virtual address space for the remaining peripherals like, SoC devices, FLASH etc. Note that ECC is currently not supported on configurations with more than 2GB SDRAM. This is because we only map the first 2GB on such systems, and therefore the ECC parity byte of the remaining area can't be written. Signed-off-by: Stefan Roese --- cpu/ppc4xx/44x_spd_ddr2.c | 56 +++++++++++++++++++++++++++------- include/asm-ppc/ppc4xx-sdram.h | 4 +-- include/configs/katmai.h | 7 +++++ 3 files changed, 54 insertions(+), 13 deletions(-) diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index c28fc463b5..9a5340c351 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -137,6 +137,20 @@ #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ #endif +/* + * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM. + * To support such configurations, we "only" map the first 2GB via the TLB's. We + * need some free virtual address space for the remaining peripherals like, SoC + * devices, FLASH etc. + * + * Note that ECC is currently not supported on configurations with more than 2GB + * SDRAM. This is because we only map the first 2GB on such systems, and therefore + * the ECC parity byte of the remaining area can't be written. + */ +#ifndef CONFIG_MAX_MEM_MAPPED +#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) +#endif + /* * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed */ @@ -181,7 +195,7 @@ typedef enum ddr_cas_id { /*-----------------------------------------------------------------------------+ * Prototypes *-----------------------------------------------------------------------------*/ -static unsigned long sdram_memsize(void); +static phys_size_t sdram_memsize(void); static void get_spd_info(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks); @@ -306,9 +320,9 @@ static unsigned char spd_read(uchar chip, uint addr) /*-----------------------------------------------------------------------------+ * sdram_memsize *-----------------------------------------------------------------------------*/ -static unsigned long sdram_memsize(void) +static phys_size_t sdram_memsize(void) { - unsigned long mem_size; + phys_size_t mem_size; unsigned long mcopt2; unsigned long mcstat; unsigned long mb0cf; @@ -364,6 +378,8 @@ static unsigned long sdram_memsize(void) mem_size+=4096; break; default: + printf("WARNING: Unsupported bank size (SDSZ=0x%x)!\n" + , sdsz); mem_size=0; break; } @@ -371,8 +387,7 @@ static unsigned long sdram_memsize(void) } } - mem_size *= 1024 * 1024; - return(mem_size); + return mem_size << 20; } /*-----------------------------------------------------------------------------+ @@ -400,7 +415,7 @@ phys_size_t initdram(int board_type) unsigned long val; ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */ int write_recovery; - unsigned long dram_size = 0; + phys_size_t dram_size = 0; num_dimm_banks = sizeof(iic0_dimm_addr); @@ -558,6 +573,12 @@ phys_size_t initdram(int board_type) /* get installed memory size */ dram_size = sdram_memsize(); + /* + * Limit size to 2GB + */ + if (dram_size > CONFIG_MAX_MEM_MAPPED) + dram_size = CONFIG_MAX_MEM_MAPPED; + /* and program tlb entries for this size (dynamic) */ /* @@ -595,7 +616,7 @@ phys_size_t initdram(int board_type) */ set_mcsr(get_mcsr()); - return dram_size; + return sdram_memsize(); } static void get_spd_info(unsigned long *dimm_populated, @@ -2133,15 +2154,15 @@ static void program_memory_queue(unsigned long *dimm_populated, unsigned long num_dimm_banks) { unsigned long dimm_num; - unsigned long rank_base_addr; + phys_size_t rank_base_addr; unsigned long rank_reg; - unsigned long rank_size_bytes; + phys_size_t rank_size_bytes; unsigned long rank_size_id; unsigned long num_ranks; unsigned long baseadd_size; unsigned long i; unsigned long bank_0_populated = 0; - unsigned long total_size = 0; + phys_size_t total_size = 0; /*------------------------------------------------------------------ * Reset the rank_base_address. @@ -2289,6 +2310,11 @@ static void program_ecc(unsigned long *dimm_populated, if (ecc == 0) return; + if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) { + printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n"); + return; + } + mfsdram(SDRAM_MCOPT1, mcopt1); mfsdram(SDRAM_MCOPT2, mcopt2); @@ -2441,6 +2467,7 @@ static int short_mem_test(void) u32 bxcf; int i; int j; + phys_size_t base_addr; u32 test[NUMMEMTESTS][NUMMEMWORDS] = { {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF}, @@ -2467,10 +2494,17 @@ static int short_mem_test(void) if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) { /* Bank is enabled */ + /* + * Only run test on accessable memory (below 2GB) + */ + base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)); + if (base_addr >= CONFIG_MAX_MEM_MAPPED) + continue; + /*------------------------------------------------------------------ * Run the short memory test. *-----------------------------------------------------------------*/ - membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num))); + membase = (u32 *)(u32)base_addr; for (i = 0; i < NUMMEMTESTS; i++) { for (j = 0; j < NUMMEMWORDS; j++) { diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 83931f17f5..e151f0c113 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -284,8 +284,8 @@ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ -#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((u32)(n))&0xFFE00000)>>2) -#define SDRAM_RXBAS_SDBA_DECODE(n) ((((u32)(n))&0xFFE00000)<<2) +#define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) +#define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) #endif /* CONFIG_440SPE */ #if defined(CONFIG_440SP) #define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index d3789bd67a..f07e470683 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -40,6 +40,13 @@ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ +/* + * Enable this board for more than 2GB of SDRAM + */ +#define CONFIG_PHYS_64BIT +#define CONFIG_VERY_BIG_RAM +#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) + /* * Include common defines/options for all AMCC eval boards */ From b002144e1dc21374b1ef5281fe6b5d014af96650 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 10 Jul 2008 09:58:06 +0200 Subject: [PATCH 5/5] ppc4xx: Fix printf format warnings now visible with the updated format check This patch fixes ppc4xx related printf format warning. Those warnings are now visible since patch dc4b0b38d4aadf08826f6c31270f1eecd27964fd [Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is really helpful. Signed-off-by: Stefan Roese --- board/amcc/katmai/cmd_katmai.c | 4 ++-- board/esd/du440/du440.c | 4 ++-- board/lwmon5/sdram.c | 2 +- board/zeus/zeus.c | 2 +- cpu/ppc4xx/44x_spd_ddr2.c | 10 +++++----- cpu/ppc4xx/4xx_enet.c | 2 +- cpu/ppc4xx/denali_spd_ddr2.c | 8 ++++---- cpu/ppc4xx/tlb.c | 4 ++-- cpu/ppc4xx/traps.c | 26 +++++++++++++------------- 9 files changed, 31 insertions(+), 31 deletions(-) diff --git a/board/amcc/katmai/cmd_katmai.c b/board/amcc/katmai/cmd_katmai.c index 439be4fa9d..703d225606 100644 --- a/board/amcc/katmai/cmd_katmai.c +++ b/board/amcc/katmai/cmd_katmai.c @@ -176,7 +176,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif } #ifdef DEBUG - printf(" pin strap0 to write in i2c = %x\n", data); + printf(" pin strap0 to write in i2c = %lx\n", data); #endif /* DEBUG */ if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0) @@ -201,7 +201,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) data |= 0x05A50000; #ifdef DEBUG - printf(" pin strap1 to write in i2c = %x\n", data); + printf(" pin strap1 to write in i2c = %lx\n", data); #endif /* DEBUG */ udelay(1000); diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 3dbb2e135c..8765cc1f3e 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -956,9 +956,9 @@ int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ret = run_command (cmd, 0); end = get_ticks(); - printf("ticks=%d\n", (ulong)(end - start)); + printf("ticks=%ld\n", (ulong)(end - start)); us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000)); - printf("usec=%d\n", us); + printf("usec=%ld\n", us); return ret; } diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index 0a13831156..189e824073 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -84,7 +84,7 @@ void board_add_ram_info(int use_default) puts(" (ECC not"); get_sys_info(&board_cfg); - printf(" enabled, %d MHz", (board_cfg.freqPLB * 2) / 1000000); + printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000); mfsdram(DDR0_03, val); val = DDR0_03_CASLAT_DECODE(val); diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c index 0113d4845e..33d971ab02 100644 --- a/board/zeus/zeus.c +++ b/board/zeus/zeus.c @@ -280,7 +280,7 @@ static int restore_default(void) } else { crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4); if (crc != *(u32 *)buf) { - printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(u32 *)buf); + printf("ERROR: crc mismatch %08x %08x\n", crc, *(u32 *)buf); return -1; } diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 9a5340c351..a27e276f25 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -378,7 +378,7 @@ static phys_size_t sdram_memsize(void) mem_size+=4096; break; default: - printf("WARNING: Unsupported bank size (SDSZ=0x%x)!\n" + printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n" , sdsz); mem_size=0; break; @@ -860,8 +860,8 @@ static void check_rank_number(unsigned long *dimm_populated, if (dimm_rank > MAXRANKS) { - printf("ERROR: DRAM DIMM detected with %d ranks in " - "slot %d is not supported.\n", dimm_rank, dimm_num); + printf("ERROR: DRAM DIMM detected with %lu ranks in " + "slot %lu is not supported.\n", dimm_rank, dimm_num); printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS); printf("Replace the DIMM module with a supported DIMM.\n\n"); spd_ddr_init_hang (); @@ -1062,7 +1062,7 @@ static void program_copt1(unsigned long *dimm_populated, dimm_32bit = TRUE; break; default: - printf("WARNING: Detected a DIMM with a data width of %d bits.\n", + printf("WARNING: Detected a DIMM with a data width of %lu bits.\n", data_width); printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n"); break; @@ -1615,7 +1615,7 @@ static void program_mode(unsigned long *dimm_populated, printf("Make sure the PLB speed is within the supported range of the DIMMs.\n"); printf("cas3=%d cas4=%d cas5=%d\n", cas_3_0_available, cas_4_0_available, cas_5_0_available); - printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n", + printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n", sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk); spd_ddr_init_hang (); } diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index c40e0ca480..4e863dc911 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -1076,7 +1076,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096); if (!bd_cached) { - printf("%s: Error allocating MAL descriptor buffers!\n"); + printf("%s: Error allocating MAL descriptor buffers!\n", __func__); return -1; } diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index 3bd637567c..670fc5c6ed 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -339,7 +339,7 @@ static void get_spd_info(unsigned long dimm_ranks[], "\n", dimm_num, ranks_on_dimm); if (ranks_on_dimm > max_ranks_per_dimm) { printf("WARNING: DRAM DIMM in slot %lu has %lu " - "ranks.\n"); + "ranks.\n", dimm_num, ranks_on_dimm); if (1 == max_ranks_per_dimm) { printf("Only one rank will be used.\n"); } else { @@ -668,8 +668,8 @@ static void program_ddr0_03(unsigned long dimm_ranks[], "and 5.0 are supported.\n"); printf("Make sure the PLB speed is within the supported range " "of the DIMMs.\n"); - printf("sdram_freq=%d cycle2=%d cycle3=%d cycle4=%d " - "cycle5=%d\n\n", sdram_freq, cycle_2_0_clk, + printf("sdram_freq=%ld cycle2=%ld cycle3=%ld cycle4=%ld " + "cycle5=%ld\n\n", sdram_freq, cycle_2_0_clk, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk); spd_ddr_init_hang(); } @@ -1248,7 +1248,7 @@ void board_add_ram_info(int use_default) if (!is_ecc_enabled()) { printf(" not"); } - printf(" enabled, %d MHz", (2 * get_bus_freq(0)) / 1000000); + printf(" enabled, %ld MHz", (2 * get_bus_freq(0)) / 1000000); mfsdram(DDR0_03, val); printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1); diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c index f44822dbab..24a9a9cc28 100644 --- a/cpu/ppc4xx/tlb.c +++ b/cpu/ppc4xx/tlb.c @@ -316,12 +316,12 @@ static void program_tlb_addr(u64 phys_addr, virt_addr += TLB_1KB_SIZE; } } else { - printf("ERROR: no TLB size exists for the base address 0x%0X.\n", + printf("ERROR: no TLB size exists for the base address 0x%llx.\n", phys_addr); } if (rc != 0) - printf("ERROR: no TLB entries available for the base addr 0x%0X.\n", + printf("ERROR: no TLB entries available for the base addr 0x%llx.\n", phys_addr); } diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index 8b7e32a17b..55154b6f01 100644 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -214,7 +214,7 @@ MachineCheckException(struct pt_regs *regs) } #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) mfsdram(DDR0_00, val) ; - printf("DDR0: DDR0_00 %p\n", val); + printf("DDR0: DDR0_00 %lx\n", val); val = (val >> 16) & 0xff; if (val & 0x80) printf("DDR0: At least one interrupt active\n"); @@ -263,44 +263,44 @@ MachineCheckException(struct pt_regs *regs) break; default: mfsdram(DDR0_01, value2); - printf("DDR0: No DDR0 error know 0x%x %p\n", val, value2); + printf("DDR0: No DDR0 error know 0x%lx %x\n", val, value2); } mfsdram(DDR0_23, val); if (((val >> 16) & 0xff) && corr_ecc) - printf("DDR0: Syndrome for correctable ECC event 0x%x\n", + printf("DDR0: Syndrome for correctable ECC event 0x%lx\n", (val >> 16) & 0xff); mfsdram(DDR0_23, val); if (((val >> 8) & 0xff) && uncorr_ecc) - printf("DDR0: Syndrome for uncorrectable ECC event 0x%x\n", + printf("DDR0: Syndrome for uncorrectable ECC event 0x%lx\n", (val >> 8) & 0xff); mfsdram(DDR0_33, val); if (val) printf("DDR0: Address of command that caused an " - "Out-of-Range interrupt %p\n", val); + "Out-of-Range interrupt %lx\n", val); mfsdram(DDR0_34, val); if (val && uncorr_ecc) - printf("DDR0: Address of uncorrectable ECC event %p\n", val); + printf("DDR0: Address of uncorrectable ECC event %lx\n", val); mfsdram(DDR0_35, val); if (val && uncorr_ecc) - printf("DDR0: Address of uncorrectable ECC event %p\n", val); + printf("DDR0: Address of uncorrectable ECC event %lx\n", val); mfsdram(DDR0_36, val); if (val && uncorr_ecc) - printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val); + printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val); mfsdram(DDR0_37, val); if (val && uncorr_ecc) - printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val); + printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val); mfsdram(DDR0_38, val); if (val && corr_ecc) - printf("DDR0: Address of correctable ECC event %p\n", val); + printf("DDR0: Address of correctable ECC event %lx\n", val); mfsdram(DDR0_39, val); if (val && corr_ecc) - printf("DDR0: Address of correctable ECC event %p\n", val); + printf("DDR0: Address of correctable ECC event %lx\n", val); mfsdram(DDR0_40, val); if (val && corr_ecc) - printf("DDR0: Data of correctable ECC event 0x%08x\n", val); + printf("DDR0: Data of correctable ECC event 0x%08lx\n", val); mfsdram(DDR0_41, val); if (val && corr_ecc) - printf("DDR0: Data of correctable ECC event 0x%08x\n", val); + printf("DDR0: Data of correctable ECC event 0x%08lx\n", val); #endif /* CONFIG_440EPX */ #endif /* CONFIG_440 */ show_regs(regs);