mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-15 19:51:37 +00:00
Merge git://git.denx.de/u-boot-fsl-qoriq
This commit is contained in:
commit
c590e62d3b
39 changed files with 234 additions and 102 deletions
|
@ -469,6 +469,14 @@ config SYS_FSL_SDHC_CLK_DIV
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help
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This is the divider that is used to derive SDHC clock from Platform
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clock, in another word SDHC_clk = Platform_clk / this_divider.
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config SYS_FSL_QMAN_CLK_DIV
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int "QMAN clock divider"
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default 1 if ARCH_LS1043A
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default 2
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help
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This is the divider that is used to derive QMAN clock from Platform
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clock, in another word QMAN_clk = Platform_clk / this_divider.
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endmenu
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config RESV_RAM
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@ -414,8 +414,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
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ccsr_sec_t __iomem *sec;
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#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
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if (fdt_fixup_kaslr(blob))
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fdt_fixup_remove_jr(blob);
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fdt_fixup_remove_jr(blob);
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fdt_fixup_kaslr(blob);
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#endif
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sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
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@ -155,7 +155,9 @@ void get_sys_info(struct sys_info *sys_info)
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CONFIG_SYS_FSL_IFC_CLK_DIV;
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#endif
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#ifdef CONFIG_SYS_DPAA_QBMAN
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sys_info->freq_qman = sys_info->freq_systembus;
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sys_info->freq_qman = (sys_info->freq_systembus /
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CONFIG_SYS_FSL_PCLK_DIV) /
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CONFIG_SYS_FSL_QMAN_CLK_DIV;
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#endif
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}
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@ -233,39 +233,45 @@ ENTRY(lowlevel_init)
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* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
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* placeholders.
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*/
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.macro tzasc_prog, xreg
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mov x12, TZASC1_BASE
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mov x16, #0x10000
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mul x14, \xreg, x16
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add x14, x14,x12
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mov x1, #0x8
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add x1, x1, x14
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ldr w0, [x1] /* Filter 0 Gate Keeper Register */
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orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
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str w0, [x1]
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mov x1, #0x110
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add x1, x1, x14
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ldr w0, [x1] /* Region-0 Attributes Register */
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orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
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orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
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str w0, [x1]
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mov x1, #0x114
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add x1, x1, x14
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ldr w0, [x1] /* Region-0 Access Register */
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mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
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str w0, [x1]
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.endm
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#ifdef CONFIG_FSL_TZASC_1
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ldr x1, =TZASC_GATE_KEEPER(0)
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ldr w0, [x1] /* Filter 0 Gate Keeper Register */
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orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
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str w0, [x1]
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mov x13, #0
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tzasc_prog x13
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ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
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ldr w0, [x1] /* Region-0 Attributes Register */
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orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
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orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
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str w0, [x1]
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ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
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ldr w0, [x1] /* Region-0 Access Register */
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mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
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str w0, [x1]
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#endif
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#ifdef CONFIG_FSL_TZASC_2
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ldr x1, =TZASC_GATE_KEEPER(1)
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ldr w0, [x1] /* Filter 0 Gate Keeper Register */
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orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
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str w0, [x1]
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mov x13, #1
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tzasc_prog x13
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ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
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ldr w0, [x1] /* Region-1 Attributes Register */
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orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
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orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
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str w0, [x1]
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ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
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ldr w0, [x1] /* Region-1 Attributes Register */
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mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
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str w0, [x1]
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#endif
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isb
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dsb sy
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@ -517,6 +517,7 @@ static void erratum_a010539(void)
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porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
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out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
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porsr1);
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out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
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#endif
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}
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@ -115,25 +115,48 @@ static int sec_firmware_check_copy_loadable(const void *sec_firmware_img,
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u32 *loadable_l, u32 *loadable_h)
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{
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phys_addr_t sec_firmware_loadable_addr = 0;
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int conf_node_off, ld_node_off;
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int conf_node_off, ld_node_off, images;
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char *conf_node_name = NULL;
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const void *data;
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size_t size;
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ulong load;
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const char *name, *str, *type;
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int len;
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conf_node_name = SEC_FIRMEWARE_FIT_CNF_NAME;
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conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
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if (conf_node_off < 0) {
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printf("SEC Firmware: %s: no such config\n", conf_node_name);
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return -ENOENT;
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return -ENOENT;
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}
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ld_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off,
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FIT_LOADABLE_PROP);
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if (ld_node_off >= 0) {
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printf("SEC Firmware: '%s' present in config\n",
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FIT_LOADABLE_PROP);
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/* find the node holding the images information */
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images = fdt_path_offset(sec_firmware_img, FIT_IMAGES_PATH);
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if (images < 0) {
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printf("%s: Cannot find /images node: %d\n", __func__, images);
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return -1;
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}
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type = FIT_LOADABLE_PROP;
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name = fdt_getprop(sec_firmware_img, conf_node_off, type, &len);
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if (!name) {
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/* Loadables not present */
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return 0;
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}
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printf("SEC Firmware: '%s' present in config\n", type);
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for (str = name; str && ((str - name) < len);
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str = strchr(str, '\0') + 1) {
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printf("%s: '%s'\n", type, str);
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ld_node_off = fdt_subnode_offset(sec_firmware_img, images, str);
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if (ld_node_off < 0) {
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printf("cannot find image node '%s': %d\n", str,
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ld_node_off);
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return -EINVAL;
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}
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/* Verify secure firmware image */
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if (!(fit_image_verify(sec_firmware_img, ld_node_off))) {
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@ -163,11 +186,19 @@ static int sec_firmware_check_copy_loadable(const void *sec_firmware_img,
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memcpy((void *)sec_firmware_loadable_addr, data, size);
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flush_dcache_range(sec_firmware_loadable_addr,
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sec_firmware_loadable_addr + size);
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}
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/* Populate address ptrs for loadable image with loadbale addr */
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out_le32(loadable_l, (sec_firmware_loadable_addr & WORD_MASK));
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out_le32(loadable_h, (sec_firmware_loadable_addr >> WORD_SHIFT));
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/* Populate loadable address only for Trusted OS */
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if (!strcmp(str, "trustedOS@1")) {
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/*
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* Populate address ptrs for loadable image with
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* loadbale addr
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*/
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out_le32(loadable_l, (sec_firmware_loadable_addr &
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WORD_MASK));
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out_le32(loadable_h, (sec_firmware_loadable_addr >>
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WORD_SHIFT));
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}
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}
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return 0;
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}
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@ -317,9 +348,7 @@ unsigned int sec_firmware_support_psci_version(void)
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*/
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bool sec_firmware_support_hwrng(void)
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{
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uint8_t rand[8];
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if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) {
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if (!sec_firmware_get_random(rand, 8))
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return true;
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}
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@ -428,8 +457,10 @@ int fdt_fixup_kaslr(void *fdt)
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#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT)
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/* Check if random seed generation is supported */
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if (sec_firmware_support_hwrng() == false)
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if (sec_firmware_support_hwrng() == false) {
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printf("WARNING: SEC firmware not running, no kaslr-seed\n");
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return 0;
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}
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ret = sec_firmware_get_random(rand, 8);
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if (ret < 0) {
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@ -26,6 +26,13 @@
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.globl __secondary_start_page
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.align 12
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__secondary_start_page:
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#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
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msync
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isync
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mfspr r3, SPRN_HDBCR0
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oris r3, r3, 0x0080
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mtspr SPRN_HDBCR0, r3
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#endif
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/* First do some preliminary setup */
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lis r3, HID0_EMCP@h /* enable machine check */
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#ifndef CONFIG_E500MC
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@ -30,12 +30,12 @@ static const struct board_specific_parameters udimm0[] = {
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#if defined(CONFIG_TARGET_LS1088ARDB)
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{2, 1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,},
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{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
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{2, 1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,},
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{2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,},
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{}
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#elif defined(CONFIG_TARGET_LS1088AQDS)
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{2, 1666, 0, 8, 8, 0x0A0A0C0E, 0x0F10110C,},
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{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
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{2, 1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,},
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{2, 2300, 0, 4, 9, 0x0A0C0D11, 0x1214150E,},
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{}
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@ -4,12 +4,14 @@
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/fsl_serdes.h>
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#include <hwconfig.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <i2c.h>
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#include <miiphy.h>
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@ -8,9 +8,12 @@ CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_GREPENV=y
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CONFIG_CMD_MEMTEST=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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|
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@ -11,9 +11,12 @@ CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
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# CONFIG_USE_BOOTCOMMAND is not set
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_CMD_GREPENV=y
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CONFIG_CMD_MEMTEST=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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|
|
|
@ -10,9 +10,12 @@ CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
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# CONFIG_USE_BOOTCOMMAND is not set
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_CMD_GREPENV=y
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CONFIG_CMD_MEMTEST=y
|
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CONFIG_CMD_I2C=y
|
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CONFIG_CMD_MMC=y
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|
|
|
@ -13,6 +13,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
|
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
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CONFIG_SD_BOOT=y
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||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
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CONFIG_DISPLAY_BOARDINFO_LATE=y
|
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
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|
@ -21,6 +23,7 @@ CONFIG_SPL_ENV_SUPPORT=y
|
|||
CONFIG_SPL_I2C_SUPPORT=y
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CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
|
|
|
@ -15,6 +15,8 @@ CONFIG_FIT_VERBOSE=y
|
|||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
|
||||
CONFIG_SD_BOOT=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
|
||||
# CONFIG_USE_BOOTCOMMAND is not set
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
|
@ -23,6 +25,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
|
|||
CONFIG_SPL_ENV_SUPPORT=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
|
|
|
@ -11,9 +11,12 @@ CONFIG_FIT_VERBOSE=y
|
|||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
|
||||
# CONFIG_USE_BOOTCOMMAND is not set
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
|
|
|
@ -10,9 +10,12 @@ CONFIG_FIT_VERBOSE=y
|
|||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
|
||||
# CONFIG_USE_BOOTCOMMAND is not set
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
|
|
|
@ -16,6 +16,8 @@ CONFIG_FIT_VERBOSE=y
|
|||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
|
||||
CONFIG_SD_BOOT=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
|
||||
# CONFIG_USE_BOOTCOMMAND is not set
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
|
@ -26,6 +28,7 @@ CONFIG_SPL_HASH_SUPPORT=y
|
|||
CONFIG_SPL_ENV_SUPPORT=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
|
|
|
@ -15,6 +15,8 @@ CONFIG_FIT_VERBOSE=y
|
|||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
|
||||
CONFIG_SD_BOOT=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
|
||||
# CONFIG_USE_BOOTCOMMAND is not set
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
|
@ -23,6 +25,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
|
|||
CONFIG_SPL_ENV_SUPPORT=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
|
|
49
doc/uImage.FIT/sec_firmware_ppa.its
Normal file
49
doc/uImage.FIT/sec_firmware_ppa.its
Normal file
|
@ -0,0 +1,49 @@
|
|||
/dts-v1/;
|
||||
|
||||
/*
|
||||
* Example FIT image description file demonstrating the usage
|
||||
* of SEC Firmware and multiple loadable images loaded by the u-boot.
|
||||
* For booting PPA (SEC Firmware), "firmware" is searched and loaded.
|
||||
*
|
||||
* Multiple binaries will be loaded as "loadables" (if present) at their
|
||||
* respective load offsets from firmware image address.
|
||||
*/
|
||||
|
||||
/{
|
||||
description = "PPA Firmware";
|
||||
#address-cells = <1>;
|
||||
images {
|
||||
firmware@1 {
|
||||
description = "PPA Firmware: <version>";
|
||||
data = /incbin/("../obj/monitor.bin");
|
||||
type = "firmware";
|
||||
arch = "arm64";
|
||||
compression = "none";
|
||||
};
|
||||
trustedOS@1 {
|
||||
description = "Trusted OS";
|
||||
data = /incbin/("../../tee.bin");
|
||||
type = "OS";
|
||||
arch = "arm64";
|
||||
compression = "none";
|
||||
load = <0x00200000>;
|
||||
};
|
||||
fuse_scr {
|
||||
description = "Fuse Script";
|
||||
data = /incbin/("../../fuse_scr.bin");
|
||||
type = "firmware";
|
||||
arch = "arm64";
|
||||
compression = "none";
|
||||
load = <0x00180000>;
|
||||
};
|
||||
};
|
||||
|
||||
configurations {
|
||||
default = "config-1";
|
||||
config-1 {
|
||||
description = "PPA Secure firmware";
|
||||
firmware = "firmware@1";
|
||||
loadables = "trustedOS@1", "fuse_scr";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -269,14 +269,9 @@ static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
|
|||
|
||||
/* returns nonzero if entire page is blank */
|
||||
static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
|
||||
u32 *eccstat, unsigned int bufnum)
|
||||
u32 eccstat, unsigned int bufnum)
|
||||
{
|
||||
u32 reg = eccstat[bufnum / 4];
|
||||
int errors;
|
||||
|
||||
errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
|
||||
|
||||
return errors;
|
||||
return (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -290,7 +285,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
|
|||
struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
|
||||
u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
|
||||
u32 time_start;
|
||||
u32 eccstat[8] = {0};
|
||||
u32 eccstat;
|
||||
int i;
|
||||
|
||||
/* set the chip select for NAND Transaction */
|
||||
|
@ -320,20 +315,17 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
|
|||
if (ctrl->eccread) {
|
||||
int errors;
|
||||
int bufnum = ctrl->page & priv->bufnum_mask;
|
||||
int sector = bufnum * chip->ecc.steps;
|
||||
int sector_end = sector + chip->ecc.steps - 1;
|
||||
int sector_start = bufnum * chip->ecc.steps;
|
||||
int sector_end = sector_start + chip->ecc.steps - 1;
|
||||
u32 *eccstat_regs;
|
||||
|
||||
for (i = sector / 4; i <= sector_end / 4; i++) {
|
||||
if (i >= ARRAY_SIZE(eccstat)) {
|
||||
printf("%s: eccstat too small for %d\n",
|
||||
__func__, i);
|
||||
return -EIO;
|
||||
}
|
||||
eccstat_regs = ifc->ifc_nand.nand_eccstat;
|
||||
eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
|
||||
|
||||
eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
|
||||
}
|
||||
for (i = sector_start; i <= sector_end; i++) {
|
||||
if ((i != sector_start) && !(i % 4))
|
||||
eccstat = ifc_in32(&eccstat_regs[i / 4]);
|
||||
|
||||
for (i = sector; i <= sector_end; i++) {
|
||||
errors = check_read_ecc(mtd, ctrl, eccstat, i);
|
||||
|
||||
if (errors == 15) {
|
||||
|
@ -708,6 +700,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
|
|||
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
|
||||
struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
|
||||
u32 nand_fsr;
|
||||
int status;
|
||||
|
||||
if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
|
||||
return NAND_STATUS_FAIL;
|
||||
|
@ -728,10 +721,10 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
|
|||
return NAND_STATUS_FAIL;
|
||||
|
||||
nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
|
||||
status = nand_fsr >> 24;
|
||||
|
||||
/* Chip sometimes reporting write protect even when it's not */
|
||||
nand_fsr = nand_fsr | NAND_STATUS_WP;
|
||||
return nand_fsr;
|
||||
return status | NAND_STATUS_WP;
|
||||
}
|
||||
|
||||
static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Freescale Layerscape MC I/O wrapper
|
||||
*
|
||||
* Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2013-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
#include <fsl-mc/fsl_mc_sys.h>
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2013-2016 Freescale Semiconductor
|
||||
* Copyright 2013-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Freescale Layerscape MC I/O wrapper
|
||||
*
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2015-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
* Author: Prabhakar Kushwaha <prabhakar@freescale.com>
|
||||
*/
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2013-2016 Freescale Semiconductor
|
||||
* Copyright 2013-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Freescale Layerscape MC I/O wrapper
|
||||
*
|
||||
* Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2013-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/* Copyright 2013-2016 Freescale Semiconductor Inc.
|
||||
/* Copyright 2013-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
#ifndef __FSL_DPMNG_CMD_H
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 NXP Semiconductors
|
||||
* Copyright (C) 2014 Freescale Semiconductor
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <errno.h>
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2014-2016 Freescale Semiconductor
|
||||
* Copyright 2014-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2014-2016 Freescale Semiconductor
|
||||
* Copyright 2014-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
|
||||
|
|
|
@ -155,6 +155,25 @@ static void qspi_write32(u32 flags, u32 *addr, u32 val)
|
|||
out_be32(addr, val) : out_le32(addr, val);
|
||||
}
|
||||
|
||||
static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
|
||||
{
|
||||
u32 val;
|
||||
const u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
|
||||
QSPI_SR_IP_ACC_MASK;
|
||||
unsigned int retry = 5;
|
||||
|
||||
do {
|
||||
val = qspi_read32(priv->flags, &priv->regs->sr);
|
||||
|
||||
if ((~val & mask) == mask)
|
||||
return 0;
|
||||
|
||||
udelay(1);
|
||||
} while (--retry);
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
/* QSPI support swapping the flash read/write data
|
||||
* in hardware for LS102xA, but not for VF610 */
|
||||
static inline u32 qspi_endian_xchg(u32 data)
|
||||
|
@ -1017,11 +1036,7 @@ static int fsl_qspi_probe(struct udevice *bus)
|
|||
priv->num_chipselect = plat->num_chipselect;
|
||||
|
||||
/* make sure controller is not busy anywhere */
|
||||
ret = wait_for_bit_le32(&priv->regs->sr,
|
||||
QSPI_SR_BUSY_MASK |
|
||||
QSPI_SR_AHB_ACC_MASK |
|
||||
QSPI_SR_IP_ACC_MASK,
|
||||
false, 100, false);
|
||||
ret = is_controller_busy(priv);
|
||||
|
||||
if (ret) {
|
||||
debug("ERROR : The controller is busy\n");
|
||||
|
@ -1184,11 +1199,7 @@ static int fsl_qspi_claim_bus(struct udevice *dev)
|
|||
priv = dev_get_priv(bus);
|
||||
|
||||
/* make sure controller is not busy anywhere */
|
||||
ret = wait_for_bit_le32(&priv->regs->sr,
|
||||
QSPI_SR_BUSY_MASK |
|
||||
QSPI_SR_AHB_ACC_MASK |
|
||||
QSPI_SR_IP_ACC_MASK,
|
||||
false, 100, false);
|
||||
ret = is_controller_busy(priv);
|
||||
|
||||
if (ret) {
|
||||
debug("ERROR : The controller is busy\n");
|
||||
|
|
|
@ -148,7 +148,6 @@ unsigned long long get_qixis_addr(void);
|
|||
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
|
||||
#endif
|
||||
/* Command line configuration */
|
||||
#define CONFIG_CMD_GREPENV
|
||||
#define CONFIG_CMD_CACHE
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
|
@ -195,10 +194,6 @@ unsigned long long get_qixis_addr(void);
|
|||
"mcinitcmd=fsl_mc start mc 0x580a00000" \
|
||||
" 0x580e00000 \0"
|
||||
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
|
||||
"earlycon=uart8250,mmio,0x21c0500 " \
|
||||
"ramdisk_size=0x3000000 default_hugepagesz=2m" \
|
||||
" hugepagesz=2m hugepages=256"
|
||||
#if defined(CONFIG_QSPI_BOOT)
|
||||
#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
|
||||
"sf read 0x80200000 0xd00000 0x100000;"\
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Freescale Layerscape MC I/O wrapper
|
||||
*
|
||||
* Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2013-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
/*!
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2013-2016 Freescale Semiconductor
|
||||
* Copyright 2013-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Freescale Layerscape MC I/O wrapper
|
||||
*
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2015-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
* Author: Prabhakar Kushwaha <prabhakar@freescale.com>
|
||||
*/
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2013-2016 Freescale Semiconductor
|
||||
* Copyright 2013-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
#ifndef _FSL_DPNI_H
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Freescale Layerscape MC I/O wrapper
|
||||
*
|
||||
* Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2013-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
#ifndef _FSL_DPRC_H
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/* Copyright 2013-2016 Freescale Semiconductor Inc.
|
||||
/* Copyright 2013-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
#ifndef __FSL_MC_CMD_H
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2014-2016 Freescale Semiconductor
|
||||
* Copyright 2014-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
|
||||
|
|
|
@ -891,8 +891,8 @@ struct fsl_ifc_nand {
|
|||
u32 nand_erattr1;
|
||||
u32 res19[0x10];
|
||||
u32 nand_fsr;
|
||||
u32 res20[0x3];
|
||||
u32 nand_eccstat[6];
|
||||
u32 res20[0x1];
|
||||
u32 nand_eccstat[8];
|
||||
u32 res21[0x1c];
|
||||
u32 nanndcr;
|
||||
u32 res22[0x2];
|
||||
|
|
Loading…
Add table
Reference in a new issue