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CACHE: net: asix: Fix asix driver to work with data cache on
The asix driver did not align buffers, therefore it didn't work with data cache enabled. Fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
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cc5f552283
commit
c59ab0921f
1 changed files with 17 additions and 13 deletions
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@ -168,27 +168,28 @@ static inline int asix_set_hw_mii(struct ueth_data *dev)
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static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc)
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{
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__le16 res;
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ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
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asix_set_sw_mii(dev);
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asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, &res);
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asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, res);
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asix_set_hw_mii(dev);
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debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
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phy_id, loc, le16_to_cpu(res));
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phy_id, loc, le16_to_cpu(*res));
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return le16_to_cpu(res);
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return le16_to_cpu(*res);
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}
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static void
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asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val)
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{
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__le16 res = cpu_to_le16(val);
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ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
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*res = cpu_to_le16(val);
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debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
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phy_id, loc, val);
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asix_set_sw_mii(dev);
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asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, &res);
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asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, res);
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asix_set_hw_mii(dev);
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}
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@ -210,7 +211,8 @@ static int asix_sw_reset(struct ueth_data *dev, u8 flags)
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static inline int asix_get_phy_addr(struct ueth_data *dev)
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{
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u8 buf[2];
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ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2);
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int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf);
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debug("asix_get_phy_addr()\n");
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@ -242,13 +244,14 @@ static int asix_write_medium_mode(struct ueth_data *dev, u16 mode)
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static u16 asix_read_rx_ctl(struct ueth_data *dev)
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{
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__le16 v;
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int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, &v);
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ALLOC_CACHE_ALIGN_BUFFER(__le16, v, 1);
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int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, v);
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if (ret < 0)
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debug("Error reading RX_CTL register: %02x\n", ret);
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else
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ret = le16_to_cpu(v);
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ret = le16_to_cpu(*v);
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return ret;
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}
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@ -313,7 +316,7 @@ static int mii_nway_restart(struct ueth_data *dev)
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static int asix_init(struct eth_device *eth, bd_t *bd)
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{
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int embd_phy;
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unsigned char buf[ETH_ALEN];
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ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
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u16 rx_ctl;
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struct ueth_data *dev = (struct ueth_data *)eth->priv;
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int timeout = 0;
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@ -425,7 +428,8 @@ static int asix_send(struct eth_device *eth, void *packet, int length)
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int err;
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u32 packet_len;
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int actual_len;
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unsigned char msg[PKTSIZE + sizeof(packet_len)];
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ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
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PKTSIZE + sizeof(packet_len));
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debug("** %s(), len %d\n", __func__, length);
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@ -452,7 +456,7 @@ static int asix_send(struct eth_device *eth, void *packet, int length)
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static int asix_recv(struct eth_device *eth)
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{
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struct ueth_data *dev = (struct ueth_data *)eth->priv;
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static unsigned char recv_buf[AX_RX_URB_SIZE];
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ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
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unsigned char *buf_ptr;
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int err;
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int actual_len;
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