GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-06-05 22:31:36 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

mpc85xx/T1040QDS_D4: Add DDR4 support

Browse source 
T1040QDS_D4 is a variant of T1040QDS, with additional circuit to support
DDR4 memory. Tested with MTA9ASF51272AZ-2G1AYESZG.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2014-03-27 17:54:48 -07:00
parent 34e026f9b1
commit c60dee03c0
4 changed files with 31 additions and 28 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
board/freescale/t1040qds/ddr.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright 2013 Freescale Semiconductor, Inc. * Copyright 2013-2014 Freescale Semiconductor, Inc.
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
@ -39,14 +39,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
if (pbsp->n_ranks == pdimm->n_ranks && if (pbsp->n_ranks == pdimm->n_ranks &&
(pdimm->rank_density >> 30) >= pbsp->rank_gb) { (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) { if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->cpo_override = pbsp->cpo;
popts->write_data_delay =
pbsp->write_data_delay;
popts->clk_adjust = pbsp->clk_adjust; popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
popts->twot_en = pbsp->force_2t;
goto found; goto found;
} }
pbsp_highest = pbsp; pbsp_highest = pbsp;
@ -59,13 +55,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
printf("for data rate %lu MT/s\n", ddr_freq); printf("for data rate %lu MT/s\n", ddr_freq);
printf("Trying to use the highest speed (%u) parameters\n", printf("Trying to use the highest speed (%u) parameters\n",
pbsp_highest->datarate_mhz_high); pbsp_highest->datarate_mhz_high);
popts->cpo_override = pbsp_highest->cpo;
popts->write_data_delay = pbsp_highest->write_data_delay;
popts->clk_adjust = pbsp_highest->clk_adjust; popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
popts->twot_en = pbsp_highest->force_2t;
} else { } else {
panic("DIMM is not supported by this board"); panic("DIMM is not supported by this board");
} }
@ -81,7 +74,7 @@ found:
* Factors to consider for half-strength driver enable: * Factors to consider for half-strength driver enable:
* - number of DIMMs installed * - number of DIMMs installed
*/ */
popts->half_strength_driver_enable = 0; popts->half_strength_driver_enable = 1;
/* /*
* Write leveling override * Write leveling override
*/ */
@ -97,8 +90,14 @@ found:
popts->zq_en = 1; popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */ /* DHC_EN =1, ODT = 75 Ohm */
#ifdef CONFIG_SYS_FSL_DDR4
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
#else
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
#endif
} }
phys_size_t initdram(int board_type) phys_size_t initdram(int board_type)

37
board/freescale/t1040qds/ddr.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright 2013 Freescale Semiconductor, Inc. * Copyright 2013-2014 Freescale Semiconductor, Inc.
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
@ -14,9 +14,6 @@ struct board_specific_parameters {
u32 wrlvl_start; u32 wrlvl_start;
u32 wrlvl_ctl_2; u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3; u32 wrlvl_ctl_3;
u32 cpo;
u32 write_data_delay;
u32 force_2t;
}; };
/* /*
@ -28,21 +25,25 @@ struct board_specific_parameters {
static const struct board_specific_parameters udimm0[] = { static const struct board_specific_parameters udimm0[] = {
/* /*
* memory controller 0 * memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/ */
{2, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, #ifdef CONFIG_SYS_FSL_DDR4
{2, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
{1, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, #elif defined(CONFIG_SYS_FSL_DDR3)
{1, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, {2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, {1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
#else
#error DDR type not defined
#endif
{} {}
}; };

1
boards.cfg
View file

@ -942,6 +942,7 @@ Active powerpc mpc85xx - freescale p2041rdb
Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com> Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
Active powerpc mpc85xx - freescale t1040qds T1040QDS_D4 T1040QDS:PPC_T1040,SYS_FSL_DDR4 Poonam Aggrwal <poonam.aggrwal@freescale.com>
Active powerpc mpc85xx - freescale t1040qds T1040QDS_SECURE_BOOT T1040QDS:PPC_T1040,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com> Active powerpc mpc85xx - freescale t1040qds T1040QDS_SECURE_BOOT T1040QDS:PPC_T1040,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com> Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SECURE_BOOT T1040RDB:PPC_T1040,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com> Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SECURE_BOOT T1040RDB:PPC_T1040,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>

4
include/configs/T1040QDS.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright 2013 Freescale Semiconductor, Inc. * Copyright 2013-2014 Freescale Semiconductor, Inc.
* *
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
* project. * project.
@ -169,8 +169,10 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD #define CONFIG_DDR_SPD
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_FSL_DDR3
#define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_FSL_DDR_INTERACTIVE
#endif
#define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51 #define SPD_EEPROM_ADDRESS 0x51