mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 21:21:37 +00:00
ppc: Move mpc83xx clock fields to arch_global_data
Move al mpc83xx fields into arch_global_data and tidy up. Also indent the nested #ifdef for clarity. Signed-off-by: Simon Glass <sjg@chromium.org>
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748cd0591a
commit
c6731fe22a
5 changed files with 87 additions and 77 deletions
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@ -122,7 +122,7 @@ int checkcpu(void)
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printf(" at %s MHz, ", strmhz(buf, clock));
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printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
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printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
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return 0;
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}
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@ -118,7 +118,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
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do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
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"bus-frequency", bd->bi_busfreq, 1);
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do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
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"clock-frequency", gd->core_clk, 1);
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"clock-frequency", gd->arch.core_clk, 1);
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do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
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"bus-frequency", bd->bi_busfreq, 1);
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do_fixup_by_compat_u32(blob, "fsl,soc",
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@ -286,8 +286,8 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
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get_clocks();
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/* Configure the PCIE controller core clock ratio */
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out_le32(hose_cfg_base + PEX_GCLK_RATIO,
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(((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16)
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/ 333);
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(((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk)
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/ 1000000) * 16) / 333);
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udelay(1000000);
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/* Do Type 1 bridge configuration */
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@ -462,37 +462,37 @@ int get_clocks(void)
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brg_clk = qe_clk / 2;
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#endif
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gd->csb_clk = csb_clk;
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gd->arch.csb_clk = csb_clk;
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#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
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defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
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gd->tsec1_clk = tsec1_clk;
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gd->tsec2_clk = tsec2_clk;
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gd->usbdr_clk = usbdr_clk;
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gd->arch.tsec1_clk = tsec1_clk;
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gd->arch.tsec2_clk = tsec2_clk;
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gd->arch.usbdr_clk = usbdr_clk;
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#elif defined(CONFIG_MPC8309)
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gd->usbdr_clk = usbdr_clk;
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gd->arch.usbdr_clk = usbdr_clk;
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#endif
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#if defined(CONFIG_MPC834x)
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gd->usbmph_clk = usbmph_clk;
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gd->arch.usbmph_clk = usbmph_clk;
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#endif
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#if defined(CONFIG_MPC8315)
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gd->tdm_clk = tdm_clk;
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gd->arch.tdm_clk = tdm_clk;
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#endif
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#if defined(CONFIG_FSL_ESDHC)
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gd->sdhc_clk = sdhc_clk;
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#endif
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gd->core_clk = core_clk;
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gd->arch.core_clk = core_clk;
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gd->i2c1_clk = i2c1_clk;
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#if !defined(CONFIG_MPC832x)
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gd->i2c2_clk = i2c2_clk;
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#endif
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#if !defined(CONFIG_MPC8309)
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gd->enc_clk = enc_clk;
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gd->arch.enc_clk = enc_clk;
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#endif
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gd->lbiu_clk = lbiu_clk;
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gd->lclk_clk = lclk_clk;
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gd->arch.lbiu_clk = lbiu_clk;
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gd->arch.lclk_clk = lclk_clk;
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gd->mem_clk = mem_clk;
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#if defined(CONFIG_MPC8360)
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gd->mem_sec_clk = mem_sec_clk;
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gd->arch.mem_sec_clk = mem_sec_clk;
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#endif
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#if defined(CONFIG_QE)
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gd->qe_clk = qe_clk;
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@ -500,15 +500,15 @@ int get_clocks(void)
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#endif
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#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
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defined(CONFIG_MPC837x)
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gd->pciexp1_clk = pciexp1_clk;
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gd->pciexp2_clk = pciexp2_clk;
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gd->arch.pciexp1_clk = pciexp1_clk;
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gd->arch.pciexp2_clk = pciexp2_clk;
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#endif
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#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
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gd->sata_clk = sata_clk;
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gd->arch.sata_clk = sata_clk;
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#endif
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gd->pci_clk = pci_sync_in;
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gd->cpu_clk = gd->core_clk;
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gd->bus_clk = gd->csb_clk;
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gd->cpu_clk = gd->arch.core_clk;
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gd->bus_clk = gd->arch.csb_clk;
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return 0;
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}
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@ -519,7 +519,7 @@ int get_clocks(void)
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*********************************************/
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ulong get_bus_freq(ulong dummy)
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{
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return gd->csb_clk;
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return gd->arch.csb_clk;
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}
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/********************************************
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@ -536,50 +536,65 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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char buf[32];
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printf("Clock configuration:\n");
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printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk));
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printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
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printf(" Core: %-4s MHz\n",
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strmhz(buf, gd->arch.core_clk));
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printf(" Coherent System Bus: %-4s MHz\n",
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strmhz(buf, gd->arch.csb_clk));
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#if defined(CONFIG_QE)
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printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk));
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printf(" BRG: %-4s MHz\n",
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strmhz(buf, gd->arch.brg_clk));
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#endif
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printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
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printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk));
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printf(" Local Bus Controller:%-4s MHz\n",
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strmhz(buf, gd->arch.lbiu_clk));
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printf(" Local Bus: %-4s MHz\n",
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strmhz(buf, gd->arch.lclk_clk));
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printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
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#if defined(CONFIG_MPC8360)
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printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
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printf(" DDR Secondary: %-4s MHz\n",
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strmhz(buf, gd->arch.mem_sec_clk));
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#endif
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#if !defined(CONFIG_MPC8309)
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printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk));
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printf(" SEC: %-4s MHz\n",
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strmhz(buf, gd->arch.enc_clk));
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#endif
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printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
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#if !defined(CONFIG_MPC832x)
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printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
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#endif
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#if defined(CONFIG_MPC8315)
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printf(" TDM: %-4s MHz\n", strmhz(buf, gd->tdm_clk));
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printf(" TDM: %-4s MHz\n",
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strmhz(buf, gd->arch.tdm_clk));
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#endif
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#if defined(CONFIG_FSL_ESDHC)
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printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
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#endif
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#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
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defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
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printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
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printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
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printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
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printf(" TSEC1: %-4s MHz\n",
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strmhz(buf, gd->arch.tsec1_clk));
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printf(" TSEC2: %-4s MHz\n",
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strmhz(buf, gd->arch.tsec2_clk));
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printf(" USB DR: %-4s MHz\n",
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strmhz(buf, gd->arch.usbdr_clk));
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#elif defined(CONFIG_MPC8309)
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printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
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printf(" USB DR: %-4s MHz\n",
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strmhz(buf, gd->arch.usbdr_clk));
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#endif
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#if defined(CONFIG_MPC834x)
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printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
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printf(" USB MPH: %-4s MHz\n",
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strmhz(buf, gd->arch.usbmph_clk));
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#endif
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#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
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defined(CONFIG_MPC837x)
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printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
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printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
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printf(" PCIEXP1: %-4s MHz\n",
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strmhz(buf, gd->arch.pciexp1_clk));
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printf(" PCIEXP2: %-4s MHz\n",
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strmhz(buf, gd->arch.pciexp2_clk));
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#endif
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#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
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printf(" SATA: %-4s MHz\n", strmhz(buf, gd->sata_clk));
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printf(" SATA: %-4s MHz\n",
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strmhz(buf, gd->arch.sata_clk));
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#endif
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return 0;
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}
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@ -41,6 +41,40 @@ struct arch_global_data {
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#endif
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#if defined(CONFIG_QE)
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u32 brg_clk;
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#endif
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/* TODO: sjg@chromium.org: Should these be unslgned long? */
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#if defined(CONFIG_MPC83xx)
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/* There are other clocks in the MPC83XX */
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u32 csb_clk;
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# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
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defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
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u32 tsec1_clk;
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u32 tsec2_clk;
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u32 usbdr_clk;
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# elif defined(CONFIG_MPC8309)
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u32 usbdr_clk;
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# endif
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# if defined(CONFIG_MPC834x)
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u32 usbmph_clk;
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# endif /* CONFIG_MPC834x */
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# if defined(CONFIG_MPC8315)
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u32 tdm_clk;
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# endif
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u32 core_clk;
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u32 enc_clk;
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u32 lbiu_clk;
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u32 lclk_clk;
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# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
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defined(CONFIG_MPC837x)
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u32 pciexp1_clk;
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u32 pciexp2_clk;
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# endif
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# if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
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u32 sata_clk;
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# endif
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# if defined(CONFIG_MPC8360)
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u32 mem_sec_clk;
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# endif /* CONFIG_MPC8360 */
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#endif
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};
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@ -59,47 +93,8 @@ typedef struct global_data {
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unsigned long cpu_clk; /* CPU clock in Hz! */
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unsigned long bus_clk;
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/* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
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unsigned long pci_clk;
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#if defined(CONFIG_CPM2)
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/* There are many clocks on the MPC8260 - see page 9-5 */
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unsigned long vco_out;
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unsigned long cpm_clk;
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unsigned long scc_clk;
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#endif
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unsigned long pci_clk;
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unsigned long mem_clk;
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#if defined(CONFIG_MPC83xx)
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/* There are other clocks in the MPC83XX */
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u32 csb_clk;
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#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
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defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
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u32 tsec1_clk;
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u32 tsec2_clk;
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u32 usbdr_clk;
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#elif defined(CONFIG_MPC8309)
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u32 usbdr_clk;
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#endif
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#if defined (CONFIG_MPC834x)
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u32 usbmph_clk;
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#endif /* CONFIG_MPC834x */
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#if defined(CONFIG_MPC8315)
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u32 tdm_clk;
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#endif
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u32 core_clk;
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u32 enc_clk;
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u32 lbiu_clk;
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u32 lclk_clk;
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#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
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defined(CONFIG_MPC837x)
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u32 pciexp1_clk;
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u32 pciexp2_clk;
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#endif
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#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
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u32 sata_clk;
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#endif
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#if defined(CONFIG_MPC8360)
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u32 mem_sec_clk;
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#endif /* CONFIG_MPC8360 */
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#endif
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#if defined(CONFIG_FSL_ESDHC)
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u32 sdhc_clk;
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#endif
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