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MX28: SPI: Refactor spi_xfer a bit
This makes it easier to adapt for addition of DMA support. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
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parent
e972d72bd7
commit
c7065fa824
1 changed files with 22 additions and 10 deletions
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@ -146,21 +146,33 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
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struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
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struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
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struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
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int len = bitlen / 8;
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int len = bitlen / 8;
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const char *tx = dout;
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char *rx = din;
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char dummy;
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char dummy;
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int write = 0;
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char *data = NULL;
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if (bitlen == 0) {
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if (bitlen == 0) {
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if (flags & SPI_XFER_END) {
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if (flags & SPI_XFER_END) {
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rx = &dummy;
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din = (void *)&dummy;
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len = 1;
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len = 1;
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} else
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} else
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return 0;
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return 0;
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}
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}
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if (!rx && !tx)
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/* Half-duplex only */
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if (din && dout)
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return -EINVAL;
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/* No data */
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if (!din && !dout)
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return 0;
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return 0;
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if (dout) {
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data = (char *)dout;
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write = 1;
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} else if (din) {
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data = (char *)din;
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write = 0;
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}
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if (flags & SPI_XFER_BEGIN)
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if (flags & SPI_XFER_BEGIN)
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mxs_spi_start_xfer(ssp_regs);
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mxs_spi_start_xfer(ssp_regs);
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@ -171,7 +183,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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if ((flags & SPI_XFER_END) && !len)
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if ((flags & SPI_XFER_END) && !len)
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mxs_spi_end_xfer(ssp_regs);
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mxs_spi_end_xfer(ssp_regs);
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if (tx)
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if (write)
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writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
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writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
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else
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else
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writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
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writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
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@ -184,20 +196,20 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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return -ETIMEDOUT;
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return -ETIMEDOUT;
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}
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}
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if (tx)
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if (write)
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writel(*tx++, &ssp_regs->hw_ssp_data);
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writel(*data++, &ssp_regs->hw_ssp_data);
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writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
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writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
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if (rx) {
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if (!write) {
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if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
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if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
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SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
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SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
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printf("MXS SPI: Timeout waiting for data\n");
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printf("MXS SPI: Timeout waiting for data\n");
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return -ETIMEDOUT;
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return -ETIMEDOUT;
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}
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}
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*rx = readl(&ssp_regs->hw_ssp_data);
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*data = readl(&ssp_regs->hw_ssp_data);
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rx++;
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data++;
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}
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}
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if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
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if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
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