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https://github.com/Fishwaldo/u-boot.git
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m68k: mcf5445x: move early ddr init as board-specific
For certain boot types and sbf, for V4 cpu's, an early ddr/sdram init is required. This patch moves this ddr/sdram early initalization away from start.S (to be board related). Signed-off-by: Angelo Dureghello <angelo@sysam.it>
This commit is contained in:
Angelo Dureghello
parent
336aee50cf
commit
c74dda8b44
10 changed files with 302 additions and 172 deletions
arch/m68k/cpu/mcf5445x
board/freescale
include/configs
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@ -176,177 +176,12 @@ asm_dram_init:
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#if defined(CONFIG_CF_SBF)
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move.b #23, (%a1) /* dspi */
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#endif
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move.b #46, (%a1) /* DDR */
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#endif /* CONFIG_MCF5441x */
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/* slew settings */
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move.l #0xEC094060, %a1
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move.b #0, (%a1)
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/* use vco instead of cpu*2 clock for ddr clock */
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move.l #0xEC09001A, %a1
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move.w #0xE01D, (%a1)
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/* DDR settings */
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move.l #0xFC0B8180, %a1
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move.l #0x00000000, (%a1)
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move.l #0x40000000, (%a1)
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move.l #0xFC0B81AC, %a1
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move.l #0x01030203, (%a1)
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move.l #0xFC0B8000, %a1
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move.l #0x01010101, (%a1)+ /* 0x00 */
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move.l #0x00000101, (%a1)+ /* 0x04 */
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move.l #0x01010100, (%a1)+ /* 0x08 */
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move.l #0x01010000, (%a1)+ /* 0x0C */
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move.l #0x00010101, (%a1)+ /* 0x10 */
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move.l #0xFC0B8018, %a1
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move.l #0x00010100, (%a1)+ /* 0x18 */
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move.l #0x00000001, (%a1)+ /* 0x1C */
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move.l #0x01000001, (%a1)+ /* 0x20 */
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move.l #0x00000100, (%a1)+ /* 0x24 */
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move.l #0x00010001, (%a1)+ /* 0x28 */
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move.l #0x00000200, (%a1)+ /* 0x2C */
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move.l #0x01000002, (%a1)+ /* 0x30 */
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move.l #0x00000000, (%a1)+ /* 0x34 */
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move.l #0x00000100, (%a1)+ /* 0x38 */
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move.l #0x02000100, (%a1)+ /* 0x3C */
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move.l #0x02000407, (%a1)+ /* 0x40 */
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move.l #0x02030007, (%a1)+ /* 0x44 */
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move.l #0x02000100, (%a1)+ /* 0x48 */
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move.l #0x0A030203, (%a1)+ /* 0x4C */
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move.l #0x00020708, (%a1)+ /* 0x50 */
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move.l #0x00050008, (%a1)+ /* 0x54 */
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move.l #0x04030002, (%a1)+ /* 0x58 */
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move.l #0x00000004, (%a1)+ /* 0x5C */
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move.l #0x020A0000, (%a1)+ /* 0x60 */
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move.l #0x0C00000E, (%a1)+ /* 0x64 */
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move.l #0x00002004, (%a1)+ /* 0x68 */
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move.l #0x00000000, (%a1)+ /* 0x6C */
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move.l #0x00100010, (%a1)+ /* 0x70 */
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move.l #0x00100010, (%a1)+ /* 0x74 */
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move.l #0x00000000, (%a1)+ /* 0x78 */
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move.l #0x07990000, (%a1)+ /* 0x7C */
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move.l #0xFC0B80A0, %a1
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move.l #0x00000000, (%a1)+ /* 0xA0 */
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move.l #0x00C80064, (%a1)+ /* 0xA4 */
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move.l #0x44520002, (%a1)+ /* 0xA8 */
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move.l #0x00C80023, (%a1)+ /* 0xAC */
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move.l #0xFC0B80B4, %a1
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move.l #0x0000C350, (%a1) /* 0xB4 */
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move.l #0xFC0B80E0, %a1
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move.l #0x04000000, (%a1)+ /* 0xE0 */
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move.l #0x03000304, (%a1)+ /* 0xE4 */
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move.l #0x40040000, (%a1)+ /* 0xE8 */
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move.l #0xC0004004, (%a1)+ /* 0xEC */
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move.l #0x0642C000, (%a1)+ /* 0xF0 */
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move.l #0x00000642, (%a1)+ /* 0xF4 */
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move.l #0xFC0B8024, %a1
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tpf
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move.l #0x01000100, (%a1) /* 0x24 */
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move.l #0x2000, %d1
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jsr asm_delay
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#endif /* CONFIG_MCF5441x */
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#ifdef CONFIG_MCF5445x
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/* Dram Initialization a1, a2, and d0 */
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/* mscr sdram */
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move.l #0xFC0A4074, %a1
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move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
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nop
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/* SDRAM Chip 0 and 1 */
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move.l #0xFC0B8110, %a1
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move.l #0xFC0B8114, %a2
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/* calculate the size */
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move.l #0x13, %d1
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move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
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#ifdef CONFIG_SYS_SDRAM_BASE1
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lsr.l #1, %d2
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#endif
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dramsz_loop:
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lsr.l #1, %d2
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add.l #1, %d1
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cmp.l #1, %d2
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bne dramsz_loop
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#ifdef CONFIG_SYS_NAND_BOOT
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beq asm_nand_chk_status
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#endif
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/* SDRAM Chip 0 and 1 */
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move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
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or.l %d1, (%a1)
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#ifdef CONFIG_SYS_SDRAM_BASE1
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move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
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or.l %d1, (%a2)
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#endif
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nop
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/* dram cfg1 and cfg2 */
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move.l #0xFC0B8008, %a1
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move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
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nop
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move.l #0xFC0B800C, %a2
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move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
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nop
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move.l #0xFC0B8000, %a1 /* Mode */
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move.l #0xFC0B8004, %a2 /* Ctrl */
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/* Issue PALL */
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move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
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nop
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#ifdef CONFIG_M54455EVB
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/* Issue LEMR */
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move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
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nop
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move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
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nop
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#endif
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move.l #1000, %d1
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jsr asm_delay
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/* Issue PALL */
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move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
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nop
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/* Perform two refresh cycles */
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move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
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nop
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move.l %d0, (%a2)
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move.l %d0, (%a2)
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nop
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#ifdef CONFIG_M54455EVB
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move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
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nop
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#elif defined(CONFIG_M54451EVB)
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/* Issue LEMR */
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move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
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nop
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move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
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#endif
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move.l #500, %d1
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jsr asm_delay
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move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
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and.l #0x7FFFFFFF, %d1
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#ifdef CONFIG_M54455EVB
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or.l #0x10000C00, %d1
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#elif defined(CONFIG_M54451EVB)
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or.l #0x10000C00, %d1
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#endif
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move.l %d1, (%a2)
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nop
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move.l #2000, %d1
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jsr asm_delay
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#endif /* CONFIG_MCF5445x */
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/* mandatory board level ddr-sdram init,
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* for both 5441x and 5445x
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*/
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bsr sbf_dram_init
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#ifdef CONFIG_CF_SBF
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/*
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@ -537,7 +372,7 @@ asm_nand_init:
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move.l #0x000e0000, (%a1)
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move.l #0x2000, %d1
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jsr asm_delay
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bsr asm_delay
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/* setup nand */
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move.l #0xFC0FFF00, %a1
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@ -565,7 +400,7 @@ asm_nand_read:
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move.l %d0, (%a0)
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move.l #0x200, %d1
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jsr asm_delay
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bsr asm_delay
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asm_nand_chk_status:
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move.l #0xFC0FFF38, %a4 /* isr */
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@ -595,6 +430,7 @@ asm_nand_copy:
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#endif /* CONFIG_SYS_NAND_BOOT */
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.globl asm_delay
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asm_delay:
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nop
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subq.l #1, %d1
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@ -5,3 +5,5 @@
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#
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obj-y = m54418twr.o
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extra-y += sbf_dram_init.o
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86
board/freescale/m54418twr/sbf_dram_init.S
Normal file
86
board/freescale/m54418twr/sbf_dram_init.S
Normal file
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@ -0,0 +1,86 @@
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/*
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* Board-specific sbf ddr/sdram init.
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*
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* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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.global sbf_dram_init
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.text
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sbf_dram_init:
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move.l #0xFC04002D, %a1
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move.b #46, (%a1) /* DDR */
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/* slew settings */
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move.l #0xEC094060, %a1
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move.b #0, (%a1)
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/* use vco instead of cpu*2 clock for ddr clock */
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move.l #0xEC09001A, %a1
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move.w #0xE01D, (%a1)
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/* DDR settings */
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move.l #0xFC0B8180, %a1
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move.l #0x00000000, (%a1)
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move.l #0x40000000, (%a1)
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move.l #0xFC0B81AC, %a1
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move.l #0x01030203, (%a1)
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move.l #0xFC0B8000, %a1
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move.l #0x01010101, (%a1)+ /* 0x00 */
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move.l #0x00000101, (%a1)+ /* 0x04 */
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move.l #0x01010100, (%a1)+ /* 0x08 */
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move.l #0x01010000, (%a1)+ /* 0x0C */
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move.l #0x00010101, (%a1)+ /* 0x10 */
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move.l #0xFC0B8018, %a1
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move.l #0x00010100, (%a1)+ /* 0x18 */
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move.l #0x00000001, (%a1)+ /* 0x1C */
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move.l #0x01000001, (%a1)+ /* 0x20 */
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move.l #0x00000100, (%a1)+ /* 0x24 */
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move.l #0x00010001, (%a1)+ /* 0x28 */
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move.l #0x00000200, (%a1)+ /* 0x2C */
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move.l #0x01000002, (%a1)+ /* 0x30 */
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move.l #0x00000000, (%a1)+ /* 0x34 */
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move.l #0x00000100, (%a1)+ /* 0x38 */
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move.l #0x02000100, (%a1)+ /* 0x3C */
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move.l #0x02000407, (%a1)+ /* 0x40 */
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move.l #0x02030007, (%a1)+ /* 0x44 */
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move.l #0x02000100, (%a1)+ /* 0x48 */
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move.l #0x0A030203, (%a1)+ /* 0x4C */
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move.l #0x00020708, (%a1)+ /* 0x50 */
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move.l #0x00050008, (%a1)+ /* 0x54 */
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move.l #0x04030002, (%a1)+ /* 0x58 */
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move.l #0x00000004, (%a1)+ /* 0x5C */
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move.l #0x020A0000, (%a1)+ /* 0x60 */
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move.l #0x0C00000E, (%a1)+ /* 0x64 */
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move.l #0x00002004, (%a1)+ /* 0x68 */
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move.l #0x00000000, (%a1)+ /* 0x6C */
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move.l #0x00100010, (%a1)+ /* 0x70 */
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move.l #0x00100010, (%a1)+ /* 0x74 */
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move.l #0x00000000, (%a1)+ /* 0x78 */
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move.l #0x07990000, (%a1)+ /* 0x7C */
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move.l #0xFC0B80A0, %a1
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move.l #0x00000000, (%a1)+ /* 0xA0 */
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move.l #0x00C80064, (%a1)+ /* 0xA4 */
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move.l #0x44520002, (%a1)+ /* 0xA8 */
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move.l #0x00C80023, (%a1)+ /* 0xAC */
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move.l #0xFC0B80B4, %a1
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move.l #0x0000C350, (%a1) /* 0xB4 */
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move.l #0xFC0B80E0, %a1
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move.l #0x04000000, (%a1)+ /* 0xE0 */
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move.l #0x03000304, (%a1)+ /* 0xE4 */
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move.l #0x40040000, (%a1)+ /* 0xE8 */
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move.l #0xC0004004, (%a1)+ /* 0xEC */
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move.l #0x0642C000, (%a1)+ /* 0xF0 */
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move.l #0x00000642, (%a1)+ /* 0xF4 */
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move.l #0xFC0B8024, %a1
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tpf
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move.l #0x01000100, (%a1) /* 0x24 */
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move.l #0x2000, %d1
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bsr asm_delay
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rts
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@ -6,3 +6,4 @@
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#
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obj-y = m54451evb.o
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extra-y += sbf_dram_init.o
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97
board/freescale/m54451evb/sbf_dram_init.S
Normal file
97
board/freescale/m54451evb/sbf_dram_init.S
Normal file
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@ -0,0 +1,97 @@
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/*
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* Board-specific sbf ddr/sdram init.
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*
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* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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.global sbf_dram_init
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.text
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sbf_dram_init:
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/* Dram Initialization a1, a2, and d0 */
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/* mscr sdram */
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move.l #0xFC0A4074, %a1
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move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
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nop
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/* SDRAM Chip 0 and 1 */
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move.l #0xFC0B8110, %a1
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move.l #0xFC0B8114, %a2
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/* calculate the size */
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move.l #0x13, %d1
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move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
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#ifdef CONFIG_SYS_SDRAM_BASE1
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lsr.l #1, %d2
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#endif
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dramsz_loop:
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lsr.l #1, %d2
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add.l #1, %d1
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cmp.l #1, %d2
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bne dramsz_loop
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#ifdef CONFIG_SYS_NAND_BOOT
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beq asm_nand_chk_status
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#endif
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/* SDRAM Chip 0 and 1 */
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move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
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or.l %d1, (%a1)
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#ifdef CONFIG_SYS_SDRAM_BASE1
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move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
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or.l %d1, (%a2)
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#endif
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nop
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/* dram cfg1 and cfg2 */
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move.l #0xFC0B8008, %a1
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move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
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nop
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move.l #0xFC0B800C, %a2
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move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
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nop
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move.l #0xFC0B8000, %a1 /* Mode */
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move.l #0xFC0B8004, %a2 /* Ctrl */
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/* Issue PALL */
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move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
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nop
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move.l #1000, %d1
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bsr asm_delay
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/* Issue PALL */
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move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
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nop
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/* Perform two refresh cycles */
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move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
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nop
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move.l %d0, (%a2)
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move.l %d0, (%a2)
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nop
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/* Issue LEMR */
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move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
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nop
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move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
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move.l #500, %d1
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bsr asm_delay
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move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
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and.l #0x7FFFFFFF, %d1
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or.l #0x10000C00, %d1
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move.l %d1, (%a2)
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nop
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move.l #2000, %d1
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bsr asm_delay
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rts
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@ -6,3 +6,4 @@
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#
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obj-y = m54455evb.o
|
||||
extra-y += sbf_dram_init.o
|
||||
|
|
|
|||
101
board/freescale/m54455evb/sbf_dram_init.S
Normal file
101
board/freescale/m54455evb/sbf_dram_init.S
Normal file
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* Board-specific sbf ddr/sdram init.
|
||||
*
|
||||
* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
.global sbf_dram_init
|
||||
.text
|
||||
|
||||
sbf_dram_init:
|
||||
/* Dram Initialization a1, a2, and d0 */
|
||||
/* mscr sdram */
|
||||
move.l #0xFC0A4074, %a1
|
||||
move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
|
||||
nop
|
||||
|
||||
/* SDRAM Chip 0 and 1 */
|
||||
move.l #0xFC0B8110, %a1
|
||||
move.l #0xFC0B8114, %a2
|
||||
|
||||
/* calculate the size */
|
||||
move.l #0x13, %d1
|
||||
move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
|
||||
#ifdef CONFIG_SYS_SDRAM_BASE1
|
||||
lsr.l #1, %d2
|
||||
#endif
|
||||
|
||||
dramsz_loop:
|
||||
lsr.l #1, %d2
|
||||
add.l #1, %d1
|
||||
cmp.l #1, %d2
|
||||
bne dramsz_loop
|
||||
#ifdef CONFIG_SYS_NAND_BOOT
|
||||
beq asm_nand_chk_status
|
||||
#endif
|
||||
/* SDRAM Chip 0 and 1 */
|
||||
move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
|
||||
or.l %d1, (%a1)
|
||||
#ifdef CONFIG_SYS_SDRAM_BASE1
|
||||
move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
|
||||
or.l %d1, (%a2)
|
||||
#endif
|
||||
nop
|
||||
|
||||
/* dram cfg1 and cfg2 */
|
||||
move.l #0xFC0B8008, %a1
|
||||
move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
|
||||
nop
|
||||
move.l #0xFC0B800C, %a2
|
||||
move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
|
||||
nop
|
||||
|
||||
move.l #0xFC0B8000, %a1 /* Mode */
|
||||
move.l #0xFC0B8004, %a2 /* Ctrl */
|
||||
|
||||
/* Issue PALL */
|
||||
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
|
||||
nop
|
||||
|
||||
/* Issue LEMR */
|
||||
move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
|
||||
nop
|
||||
move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
|
||||
nop
|
||||
|
||||
move.l #1000, %d1
|
||||
bsr asm_delay
|
||||
|
||||
/* Issue PALL */
|
||||
move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
|
||||
nop
|
||||
|
||||
/* Perform two refresh cycles */
|
||||
move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
|
||||
nop
|
||||
move.l %d0, (%a2)
|
||||
move.l %d0, (%a2)
|
||||
nop
|
||||
|
||||
move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
|
||||
nop
|
||||
|
||||
move.l #500, %d1
|
||||
bsr asm_delay
|
||||
|
||||
move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
|
||||
and.l #0x7FFFFFFF, %d1
|
||||
|
||||
or.l #0x10000C00, %d1
|
||||
|
||||
move.l %d1, (%a2)
|
||||
nop
|
||||
|
||||
move.l #2000, %d1
|
||||
bsr asm_delay
|
||||
|
||||
rts
|
||||
|
|
@ -24,6 +24,8 @@
|
|||
#define CONFIG_SYS_UART_PORT (0)
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
|
||||
|
||||
#define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*)
|
||||
|
||||
#undef CONFIG_WATCHDOG
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
|
|
|||
|
|
@ -23,6 +23,8 @@
|
|||
#define CONFIG_MCFUART
|
||||
#define CONFIG_SYS_UART_PORT (0)
|
||||
|
||||
#define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*)
|
||||
|
||||
#undef CONFIG_WATCHDOG
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
|
|
|||
|
|
@ -23,6 +23,8 @@
|
|||
#define CONFIG_MCFUART
|
||||
#define CONFIG_SYS_UART_PORT (0)
|
||||
|
||||
#define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*)
|
||||
|
||||
#undef CONFIG_WATCHDOG
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue