GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-18 13:11:31 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge branch 'master' of git://git.denx.de/u-boot-arm

Browse source 
* 'master' of git://git.denx.de/u-boot-arm:
  davinci: Remove unwanted memsize.c from hawkboard's nand spl build
  devkit8000: Move CONFIG_SYS_TEXT_BASE out of bss
  da850evm: pass board revision info to kernel
  arch/arm/include/asm/arch-omap5/clocks.h: Fix GCC 4.2 warnings
  arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix GCC 4.6 warnings
  arch/arm/cpu/armv7/omap-common/spl.c: Fix GCC 4.2 warnings
  MX35: flea3: changes due to hardware revision B
  MX: serial_mxc: cleanup removing nasty #ifdef
  M28: Fix OB1 bug in GPIO driver
  MXS: Add static annotations to dma driver
  apbh_dma: return error value on timeout
  Efika: Configure additional regulators for HDMI output
  mx5: Correct a warning in clock.c
  MC13892: Add REGMODE0 bits definitions
  mx51evk: Configure the pins as GPIOs prior to using gpio_get_value
  mx53smd: Configure the pins as GPIOs prior to using gpio_get_value
  mx53evk: Configure the pins as GPIOs prior to using gpio_get_value
  mx53ard: Configure the pins as GPIOs prior to using gpio_get_value
  mx53loco: Configure the pins as GPIOs prior to using gpio_get_value
  OMAP3: Add SPL_BOARD_INIT hook
  AM3517 CraneBoard: Add SPL support
  AM3517: Add SPL support
  OMAP3: Add SPL support to omap3_evm
  OMAP3: Add SPL support to Beagleboard
  OMAP3 SPL: Add identify_nand_chip function
  OMAP3 SPL: Rework memory initalization and devkit8000 support
  OMAP3: Suffix all Micron memory timing parts with their speed
  OMAP3: Add optimal SDRC autorefresh control values
  omap3: mem: Add MCFG helper macro
  OMAP3: Remove get_mem_type prototype
  OMAP3: Change mem_ok to clear again after reading back
  OMAP3: Add a helper function to set timings in SDRC
  OMAP3: Update SDRC dram_init to always call make_cs1_contiguous()
  omap3: mem: Comment enable_gpmc_cs_config more
  ARM: davici_emac: Fix condition for number of phy detects
  arm: printf() is not available in some SPL configurations
  arm, davinci: add support for am1808 based enbw_cmc board
  arm, davinci: move misc function in arch tree
  arm, board/davinci/common/misc.c: Codingstyle cleanup
  arm, davinci, da850: add uart1 tx rx pinmux config
  arm, davinci: move davinci_rtc struct to hardware.h
  arm, davinci: Remove duplication of pinmux configuration code
  arm, hawkboard: Use the pinmux configurations defined in the arch tree
  arm, da850evm: Use the pinmux configurations defined in the arch tree
  arm, da850: Add pinmux configurations to the arch tree
  arm, da850evm: Do pinmux configuration for EMAC together with other pinmuxes
  arm, hawkboard: Remove obsolete struct pinmux_config i2c_pins
  arm, davinci: Move pinmux functions from board to arch tree
  arm, arm926ejs: always do cpu critical inits
  omap_gpmc: use SOFTECC in SPL if it's enabled
  nand_spl_simple: add support for software ECC
  AM3517: move AM3517 specific mux defines to generic header
  AM35xx: add EMAC support
  davinci_emac: hardcode 100Mbps for AM35xx and RMII
  davinci_emac: fix for running with dcache enabled
  arm926ejs: add noop implementation for dcache ops
  davinci_emac: conditionally compile specific PHY support
  davinci_emac: use internal addresses in buffer descriptors
  davinci_emac: move arch-independent defines to separate header
  BeagleBoard: config: Really switch to ttyO2
  ARM: davinci_dm6467Tevm: Fix build breakage
  ARM: OMAP: Remove STACKSIZE for IRQ and FIQ if unused
  ARM: OMAP3: Remove unused define SDRC_R_C_B
  ARM: OMAP3: Remove unused define CONFIG_OMAP3430
  omap4: fix IO setting
  omap4+: streamline CONFIG_SYS_TEXT_BASE and other SDRAM addresses
  omap4460: add ES1.1 identification
  omap4: emif: fix error in driver
  omap: remove I2C from SPL
  omap4460: fix TPS initialization
  omap: fix cache line size for omap3/omap4 boards
  omap4: ttyO2 instead of ttyS2 in default bootargs
  omap: Improve PLL parameter calculation tool
  start.S: remove omap3 specific code from start.S
  armv7: setup vector
  armv7: include armv7/cpu.c in SPL build
  armv7: disable L2 cache in cleanup_before_linux()
  arm, arm926ejs: Fix clear bss loop for zero length bss
  PXA: Move colibri_pxa270 to board/toradex/
  PXA: Flip colibri_pxa27x to pxa-common.h
  PXA: Introduce common configuration header for PXA
  PXA: Rename pxa_dram_init to pxa2xx_dram_init
  PXA: Squash extern pxa_dram_init()
  PXA: Export cpu_is_ and pxa_dram_init functions
  PXA: Cleanup Colibri PXA270
  PXA: Replace timer driver
  PXA: Add cpuinfo display for PXA2xx
  PXA: Separate PXA2xx CPU init
  PXA: Rename CONFIG_PXA2[57]X to CONFIG_CPU_PXA2[57]X
  PXA: Unify vpac270 environment size
  PXA: Enable command line editing for vpac270
  PXA: Adapt Voipac PXA270 to OneNAND SPL
  PXA: Drop Voipac PXA270 OneNAND IPL
  PXA: Fixup PXA25x boards after start.S update
  PXA: Re-add the Dcache locking as RAM for pxa250
  PXA: Rework start.S to be closer to other ARMs
  PXA: Drop XM250 board
  PXA: Drop PLEB2 board
  PXA: Drop CRADLE board
  PXA: Drop CERF250 board
  Fix regression in SMDK6400
  nand: Add common functions to linux/mtd/nand.h
  Ethernut 5 board support
  net: Armada100: Fix compilation warnings
  ARM: remove duplicated code for LaCie boards
  ARM: add support for LaCie 2Big Network v2
  mvsata: fix ide_preinit for missing disks
  netspace_v2: Read Ethernet MAC address from EEPROM
  omap3evm: Add support for EFI partitions
  part_efi: Fix compile errors
This commit is contained in:
Wolfgang Denk 2011-12-07 09:09:58 +01:00
commit c786f54b9a
219 changed files with 5433 additions and 6288 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
MAINTAINERS
View file

@ -142,6 +142,10 @@ Phil Edworthy <phil.edworthy@renesas.com>
rsk7264 SH7264
egnite GmbH <info@egnite.de>
ethernut5 ARM926EJS (AT91SAM9XE SoC)
Dirk Eibach <eibach@gdsys.de>
devconcenter PPC460EX
@ -651,6 +655,7 @@ Simon Guinot <simon.guinot@sequanux.org>
inetspace_v2 ARM926EJS (Kirkwood SoC)
netspace_v2 ARM926EJS (Kirkwood SoC)
netspace_max_v2 ARM926EJS (Kirkwood SoC)
net2big_v2 ARM926EJS (Kirkwood SoC)
Igor Grinberg <grinberg@compulab.co.il>
@ -707,10 +712,6 @@ Sergey Kubushyn <ksi@koi8.net>
SONATA ARM926EJS
SCHMOOGIE ARM926EJS
Prakash Kumar <prakash@embedx.com>
cerf250 xscale/pxa
Vipin Kumar <vipin.kumar@st.com>
spear300 ARM926EJS (spear300 Soc)
@ -811,6 +812,7 @@ Jens Scharsig <esw@bus-elektronik.de>
Heiko Schocher <hs@denx.de>
enbw_cmc ARM926EJS (AM1808 SoC)
magnesium i.MX27
mgcoge3un ARM926EJS (Kirkwood SoC)
@ -904,7 +906,6 @@ Sughosh Ganu <urwithsughosh@gmail.com>
Unknown / orphaned boards:
Board CPU Last known maintainer / Comment
.........................................................................
cradle xscale/pxa Kyle Harris <kharris@nexus-tech.net> / dead address
lubbock xscale/pxa Kyle Harris <kharris@nexus-tech.net> / dead address
imx31_phycore_eet i.MX31 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned

4
arch/arm/cpu/arm1136/mx31/devices.c
View file

@ -27,7 +27,6 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#ifdef CONFIG_SYS_MX31_UART1
void mx31_uart1_hw_init(void)
{
/* setup pins for UART1 */
@ -36,9 +35,7 @@ void mx31_uart1_hw_init(void)
mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
}
#endif
#ifdef CONFIG_SYS_MX31_UART2
void mx31_uart2_hw_init(void)
{
/* setup pins for UART2 */
@ -47,7 +44,6 @@ void mx31_uart2_hw_init(void)
mx31_gpio_mux(MUX_RTS2__UART2_RTS_B);
mx31_gpio_mux(MUX_CTS2__UART2_CTS_B);
}
#endif
#ifdef CONFIG_MXC_SPI
/*

2
arch/arm/cpu/arm926ejs/Makefile
View file

@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).o
START = start.o
COBJS = cpu.o
COBJS = cpu.o cache.o
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_NO_CPU_SUPPORT_CODE

75
arch/arm/cpu/arm926ejs/cache.c Normal file
View file

@ -0,0 +1,75 @@
/*
* (C) Copyright 2011
* Ilya Yanok, EmCraft Systems
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <linux/types.h>
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
static inline void dcache_noop(void)
{
if (dcache_status()) {
puts("WARNING: cache operations are not implemented!\n"
"WARNING: disabling D-Cache now, you can re-enable it"
"later with 'dcache on' command\n");
dcache_disable();
}
}
void invalidate_dcache_all(void)
{
dcache_noop();
}
void flush_dcache_all(void)
{
dcache_noop();
}
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
dcache_noop();
}
void flush_dcache_range(unsigned long start, unsigned long stop)
{
dcache_noop();
}
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
{
}
void flush_dcache_all(void)
{
}
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
}
void flush_dcache_range(unsigned long start, unsigned long stop)
{
}
void flush_cache(unsigned long start, unsigned long size)
{
}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */

3
arch/arm/cpu/arm926ejs/davinci/Makefile
View file

@ -27,12 +27,13 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS-y += cpu.o timer.o psc.o
COBJS-y += cpu.o misc.o timer.o psc.o pinmux.o
COBJS-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o
COBJS-$(CONFIG_SOC_DM355) += dm355.o
COBJS-$(CONFIG_SOC_DM365) += dm365.o
COBJS-$(CONFIG_SOC_DM644X) += dm644x.o
COBJS-$(CONFIG_SOC_DM646X) += dm646x.o
COBJS-$(CONFIG_SOC_DA850) += da850_pinmux.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o
ifdef CONFIG_SPL_BUILD

36
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
View file

@ -27,6 +27,7 @@
#include <post.h>
#include <asm/arch/da850_lowlevel.h>
#include <asm/arch/hardware.h>
#include <asm/arch/davinci_misc.h>
#include <asm/arch/ddr2_defs.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/pll_defs.h>
@ -235,19 +236,16 @@ int da850_ddr_setup(void)
return 0;
}
void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
unsigned long value)
{
clrbits_le32(&davinci_syscfg_regs->pinmux[offset], mask);
setbits_le32(&davinci_syscfg_regs->pinmux[offset], (mask & value));
}
__attribute__((weak))
void board_gpio_init(void)
{
return;
}
/* pinmux_resource[] vector is defined in the board specific file */
extern const struct pinmux_resource pinmuxes[];
extern const int pinmuxes_size;
int arch_cpu_init(void)
{
/* Unlock kick registers */
@ -257,27 +255,9 @@ int arch_cpu_init(void)
dv_maskbits(&davinci_syscfg_regs->suspsrc,
CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
/* Setup Pinmux */
da850_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX0);
da850_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX1);
da850_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX2);
da850_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX3);
da850_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX4);
da850_pinmux_ctl(5, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX5);
da850_pinmux_ctl(6, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX6);
da850_pinmux_ctl(7, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX7);
da850_pinmux_ctl(8, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX8);
da850_pinmux_ctl(9, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX9);
da850_pinmux_ctl(10, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX10);
da850_pinmux_ctl(11, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX11);
da850_pinmux_ctl(12, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX12);
da850_pinmux_ctl(13, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX13);
da850_pinmux_ctl(14, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX14);
da850_pinmux_ctl(15, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX15);
da850_pinmux_ctl(16, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX16);
da850_pinmux_ctl(17, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX17);
da850_pinmux_ctl(18, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX18);
da850_pinmux_ctl(19, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX19);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
return 1;
/* PLL setup */
da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);

171
arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c Normal file
View file

@ -0,0 +1,171 @@
/*
* Pinmux configurations for the DA850 SoCs
*
* Copyright (C) 2011 OMICRON electronics GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <asm/arch/davinci_misc.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pinmux_defs.h>
/* SPI pin muxer settings */
const struct pinmux_config spi1_pins_base[] = {
{ pinmux(5), 1, 2 }, /* SPI1_CLK */
{ pinmux(5), 1, 4 }, /* SPI1_SOMI */
{ pinmux(5), 1, 5 }, /* SPI1_SIMO */
};
const struct pinmux_config spi1_pins_scs0[] = {
{ pinmux(5), 1, 1 }, /* SPI1_SCS[0] */
};
/* UART pin muxer settings */
const struct pinmux_config uart1_pins_txrx[] = {
{ pinmux(4), 2, 6 }, /* UART1_RXD */
{ pinmux(4), 2, 7 }, /* UART1_TXD */
};
const struct pinmux_config uart2_pins_txrx[] = {
{ pinmux(4), 2, 4 }, /* UART2_RXD */
{ pinmux(4), 2, 5 }, /* UART2_TXD */
};
const struct pinmux_config uart2_pins_rtscts[] = {
{ pinmux(0), 4, 6 }, /* UART2_RTS */
{ pinmux(0), 4, 7 }, /* UART2_CTS */
};
/* EMAC pin muxer settings*/
const struct pinmux_config emac_pins_rmii[] = {
{ pinmux(14), 8, 2 }, /* RMII_TXD[1] */
{ pinmux(14), 8, 3 }, /* RMII_TXD[0] */
{ pinmux(14), 8, 4 }, /* RMII_TXEN */
{ pinmux(14), 8, 5 }, /* RMII_RXD[1] */
{ pinmux(14), 8, 6 }, /* RMII_RXD[0] */
{ pinmux(14), 8, 7 }, /* RMII_RXER */
{ pinmux(15), 8, 1 }, /* RMII_CRS_DV */
};
const struct pinmux_config emac_pins_mii[] = {
{ pinmux(2), 8, 1 }, /* MII_TXEN */
{ pinmux(2), 8, 2 }, /* MII_TXCLK */
{ pinmux(2), 8, 3 }, /* MII_COL */
{ pinmux(2), 8, 4 }, /* MII_TXD[3] */
{ pinmux(2), 8, 5 }, /* MII_TXD[2] */
{ pinmux(2), 8, 6 }, /* MII_TXD[1] */
{ pinmux(2), 8, 7 }, /* MII_TXD[0] */
{ pinmux(3), 8, 0 }, /* MII_RXCLK */
{ pinmux(3), 8, 1 }, /* MII_RXDV */
{ pinmux(3), 8, 2 }, /* MII_RXER */
{ pinmux(3), 8, 3 }, /* MII_CRS */
{ pinmux(3), 8, 4 }, /* MII_RXD[3] */
{ pinmux(3), 8, 5 }, /* MII_RXD[2] */
{ pinmux(3), 8, 6 }, /* MII_RXD[1] */
{ pinmux(3), 8, 7 }, /* MII_RXD[0] */
};
const struct pinmux_config emac_pins_mdio[] = {
{ pinmux(4), 8, 0 }, /* MDIO_CLK */
{ pinmux(4), 8, 1 }, /* MDIO_D */
};
/* I2C pin muxer settings */
const struct pinmux_config i2c0_pins[] = {
{ pinmux(4), 2, 2 }, /* I2C0_SCL */
{ pinmux(4), 2, 3 }, /* I2C0_SDA */
};
const struct pinmux_config i2c1_pins[] = {
{ pinmux(4), 4, 4 }, /* I2C1_SCL */
{ pinmux(4), 4, 5 }, /* I2C1_SDA */
};
/* EMIFA pin muxer settings */
const struct pinmux_config emifa_pins_cs2[] = {
{ pinmux(7), 1, 0 }, /* EMA_CS2 */
};
const struct pinmux_config emifa_pins_cs3[] = {
{ pinmux(7), 1, 1 }, /* EMA_CS[3] */
};
const struct pinmux_config emifa_pins_cs4[] = {
{ pinmux(7), 1, 2 }, /* EMA_CS[4] */
};
const struct pinmux_config emifa_pins_nand[] = {
{ pinmux(7), 1, 4 }, /* EMA_WE */
{ pinmux(7), 1, 5 }, /* EMA_OE */
{ pinmux(9), 1, 0 }, /* EMA_D[7] */
{ pinmux(9), 1, 1 }, /* EMA_D[6] */
{ pinmux(9), 1, 2 }, /* EMA_D[5] */
{ pinmux(9), 1, 3 }, /* EMA_D[4] */
{ pinmux(9), 1, 4 }, /* EMA_D[3] */
{ pinmux(9), 1, 5 }, /* EMA_D[2] */
{ pinmux(9), 1, 6 }, /* EMA_D[1] */
{ pinmux(9), 1, 7 }, /* EMA_D[0] */
{ pinmux(12), 1, 5 }, /* EMA_A[2] */
{ pinmux(12), 1, 6 }, /* EMA_A[1] */
};
/* NOR pin muxer settings */
const struct pinmux_config emifa_pins_nor[] = {
{ pinmux(5), 1, 6 }, /* EMA_BA[1] */
{ pinmux(6), 1, 6 }, /* EMA_WAIT[1] */
{ pinmux(7), 1, 4 }, /* EMA_WE */
{ pinmux(7), 1, 5 }, /* EMA_OE */
{ pinmux(8), 1, 0 }, /* EMA_D[15] */
{ pinmux(8), 1, 1 }, /* EMA_D[14] */
{ pinmux(8), 1, 2 }, /* EMA_D[13] */
{ pinmux(8), 1, 3 }, /* EMA_D[12] */
{ pinmux(8), 1, 4 }, /* EMA_D[11] */
{ pinmux(8), 1, 5 }, /* EMA_D[10] */
{ pinmux(8), 1, 6 }, /* EMA_D[9] */
{ pinmux(8), 1, 7 }, /* EMA_D[8] */
{ pinmux(9), 1, 0 }, /* EMA_D[7] */
{ pinmux(9), 1, 1 }, /* EMA_D[6] */
{ pinmux(9), 1, 2 }, /* EMA_D[5] */
{ pinmux(9), 1, 3 }, /* EMA_D[4] */
{ pinmux(9), 1, 4 }, /* EMA_D[3] */
{ pinmux(9), 1, 5 }, /* EMA_D[2] */
{ pinmux(9), 1, 6 }, /* EMA_D[1] */
{ pinmux(9), 1, 7 }, /* EMA_D[0] */
{ pinmux(10), 1, 1 }, /* EMA_A[22] */
{ pinmux(10), 1, 2 }, /* EMA_A[21] */
{ pinmux(10), 1, 3 }, /* EMA_A[20] */
{ pinmux(10), 1, 4 }, /* EMA_A[19] */
{ pinmux(10), 1, 5 }, /* EMA_A[18] */
{ pinmux(10), 1, 6 }, /* EMA_A[17] */
{ pinmux(10), 1, 7 }, /* EMA_A[16] */
{ pinmux(11), 1, 0 }, /* EMA_A[15] */
{ pinmux(11), 1, 1 }, /* EMA_A[14] */
{ pinmux(11), 1, 2 }, /* EMA_A[13] */
{ pinmux(11), 1, 3 }, /* EMA_A[12] */
{ pinmux(11), 1, 4 }, /* EMA_A[11] */
{ pinmux(11), 1, 5 }, /* EMA_A[10] */
{ pinmux(11), 1, 6 }, /* EMA_A[9] */
{ pinmux(11), 1, 7 }, /* EMA_A[8] */
{ pinmux(12), 1, 0 }, /* EMA_A[7] */
{ pinmux(12), 1, 1 }, /* EMA_A[6] */
{ pinmux(12), 1, 2 }, /* EMA_A[5] */
{ pinmux(12), 1, 3 }, /* EMA_A[4] */
{ pinmux(12), 1, 4 }, /* EMA_A[3] */
{ pinmux(12), 1, 5 }, /* EMA_A[2] */
{ pinmux(12), 1, 6 }, /* EMA_A[1] */
{ pinmux(12), 1, 7 }, /* EMA_A[0] */
};

1
arch/arm/cpu/arm926ejs/davinci/dp83848.c
View file

@ -29,6 +29,7 @@
#include <net.h>
#include <dp83848.h>
#include <asm/arch/emac_defs.h>
#include "../../../../../drivers/net/davinci_emac.h"
#ifdef CONFIG_DRIVER_TI_EMAC

1
arch/arm/cpu/arm926ejs/davinci/et1011c.c
View file

@ -22,6 +22,7 @@
#include <net.h>
#include <miiphy.h>
#include <asm/arch/emac_defs.h>
#include "../../../../../drivers/net/davinci_emac.h"
#ifdef CONFIG_DRIVER_TI_EMAC

1
arch/arm/cpu/arm926ejs/davinci/ksz8873.c
View file

@ -36,6 +36,7 @@
#include <net.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include "../../../../../drivers/net/davinci_emac.h"
int ksz8873_is_phy_connected(int phy_addr)
{

1
arch/arm/cpu/arm926ejs/davinci/lxt972.c
View file

@ -30,6 +30,7 @@
#include <miiphy.h>
#include <lxt971a.h>
#include <asm/arch/emac_defs.h>
#include "../../../../../drivers/net/davinci_emac.h"
#ifdef CONFIG_DRIVER_TI_EMAC

19
board/davinci/common/misc.c → arch/arm/cpu/arm926ejs/davinci/misc.c
View file

@ -51,16 +51,16 @@ void dram_init_banksize(void)
#endif
#ifdef CONFIG_DRIVER_TI_EMAC
/* Read ethernet MAC address from EEPROM for DVEVM compatible boards.
/*
* Read ethernet MAC address from EEPROM for DVEVM compatible boards.
* Returns 1 if found, 0 otherwise.
*/
int dvevm_read_mac_address(uint8_t *buf)
{
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
/* Read MAC address. */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(uint8_t *) &buf[0], 6))
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))
goto i2cerr;
/* Check that MAC address is valid. */
@ -70,7 +70,8 @@ int dvevm_read_mac_address(uint8_t *buf)
return 1; /* Found */
i2cerr:
printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR);
printf("Read from EEPROM @ 0x%02x failed\n",
CONFIG_SYS_I2C_EEPROM_ADDR);
err:
#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
@ -103,15 +104,16 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);
if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) {
/* There is no MAC address in the environment, so we initialize
* it from the value in the EEPROM. */
/*
* There is no MAC address in the environment, so we
* initialize it from the value in the EEPROM.
*/
debug("### Setting environment from EEPROM MAC address = "
"\"%pM\"\n",
env_enetaddr);
eth_setenv_enetaddr("ethaddr", rom_enetaddr);
}
}
#endif /* CONFIG_DRIVER_TI_EMAC */
#if defined(CONFIG_SOC_DA8XX)
@ -122,7 +124,6 @@ void irq_init(void)
* Mask all IRQs by clearing the global enable and setting
* the enable clear for all the 90 interrupts.
*/
writel(0, &davinci_aintc_regs->ger);
writel(0, &davinci_aintc_regs->hier);

0
board/davinci/common/davinci_pinmux.c → arch/arm/cpu/arm926ejs/davinci/pinmux.c
View file

14
arch/arm/cpu/arm926ejs/start.S
View file

@ -194,9 +194,7 @@ reset:
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
@ -301,10 +299,12 @@ clear_bss:
#endif
mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
clbss_l:cmp r0, r1 /* clear loop... */
bhs clbss_e /* if reached end of bss, exit */
str r2, [r0]
add r0, r0, #4
cmp r0, r1
bne clbss_l
b clbss_l
clbss_e:
#ifndef CONFIG_SPL_BUILD
bl coloured_LED_init
@ -353,7 +353,6 @@ _dynsym_start_ofs:
*
*************************************************************************
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
/*
* flush v4 I/D caches
@ -372,14 +371,15 @@ cpu_init_crit:
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*
* Go setup Memory and board specific bits prior to relocation.
*/
mov ip, lr /* perserve link reg across call */
bl lowlevel_init /* go setup pll,mux,memory */
mov lr, ip /* restore link */
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
mov pc, lr /* back to my caller */
#ifndef CONFIG_SPL_BUILD
/*

4
arch/arm/cpu/armv7/Makefile
View file

@ -29,10 +29,10 @@ START := start.o
ifndef CONFIG_SPL_BUILD
COBJS += cache_v7.o
COBJS += cpu.o
endif
COBJS += syslib.o
COBJS += cpu.o
COBJS += syslib.o
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

1
arch/arm/cpu/armv7/cpu.c
View file

@ -65,6 +65,7 @@ int cleanup_before_linux(void)
* dcache_disable() in turn flushes the d-cache and disables MMU
*/
dcache_disable();
v7_outer_cache_disable();
/*
* After D-cache is flushed and before it is disabled there may

2
arch/arm/cpu/armv7/mx5/clock.c
View file

@ -91,7 +91,7 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
refclk *= 2;
refclk /= pdf + 1;
do_div(refclk, pdf + 1);
temp = refclk * mfn_abs;
do_div(temp, mfd + 1);
ret = refclk * mfi;

16
arch/arm/cpu/armv7/omap-common/clocks-common.c
View file

@ -253,11 +253,10 @@ void configure_mpu_dpll(void)
static void setup_dplls(void)
{
u32 sysclk_ind, temp;
u32 temp;
const struct dpll_params *params;
debug("setup_dplls\n");
sysclk_ind = get_sys_clk_index();
debug("setup_dplls\n");
/* CORE dpll */
params = get_core_dpll_params(); /* default - safest */
@ -289,10 +288,9 @@ static void setup_dplls(void)
static void setup_non_essential_dplls(void)
{
u32 sys_clk_khz, abe_ref_clk;
u32 sysclk_ind, sd_div, num, den;
u32 sd_div, num, den;
const struct dpll_params *params;
sysclk_ind = get_sys_clk_index();
sys_clk_khz = get_sys_clk_freq() / 1000;
/* IVA */
@ -359,14 +357,6 @@ void do_scale_tps62361(u32 reg, u32 volt_mv)
step = volt_mv - TPS62361_BASE_VOLT_MV;
step /= 10;
/*
* Select SET1 in TPS62361:
* VSEL1 is grounded on board. So the following selects
* VSEL1 = 0 and VSEL0 = 1
*/
gpio_direction_output(TPS62361_VSEL0_GPIO, 0);
gpio_set_value(TPS62361_VSEL0_GPIO, 1);
temp = TPS62361_I2C_SLAVE_ADDR |
(reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
(step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |

4
arch/arm/cpu/armv7/omap-common/emif-common.c
View file

@ -903,9 +903,9 @@ static void do_sdram_init(u32 base)
*/
struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
emif_reset_phy(base);
dev_details.cs0_device_details = emif_get_device_details(base, CS0,
dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
&cs0_dev_details);
dev_details.cs1_device_details = emif_get_device_details(base, CS1,
dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
&cs1_dev_details);
emif_reset_phy(base);

10
arch/arm/cpu/armv7/omap-common/spl.c
View file

@ -100,9 +100,10 @@ static void jump_to_image_no_args(void)
debug("image entry point: 0x%X\n", spl_image.entry_point);
/* Pass the saved boot_params from rom code */
#if defined(CONFIG_VIRTIO) || defined(CONFIG_ZEBU)
image_entry = 0x80100000;
image_entry = (image_entry_noargs_t)0x80100000;
#endif
image_entry((u32 *)&boot_params_ptr);
u32 boot_params_ptr_addr = (u32)&boot_params_ptr;
image_entry((u32 *)boot_params_ptr_addr);
}
void jump_to_image_no_args(void) __attribute__ ((noreturn));
@ -115,7 +116,10 @@ void board_init_r(gd_t *id, ulong dummy)
CONFIG_SYS_SPL_MALLOC_SIZE);
timer_init();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#ifdef CONFIG_SPL_BOARD_INIT
spl_board_init();
#endif
boot_device = omap_boot_device();
debug("boot device - %d\n", boot_device);

4
arch/arm/cpu/armv7/omap3/Makefile
View file

@ -31,7 +31,11 @@ COBJS += board.o
COBJS += clock.o
COBJS += mem.o
COBJS += sys_info.o
ifdef CONFIG_SPL_BUILD
COBJS-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o
endif
COBJS-$(CONFIG_DRIVER_TI_EMAC) += emac.o
COBJS-$(CONFIG_EMIF4) += emif4.o
COBJS-$(CONFIG_SDRC) += sdrc.o

5
arch/arm/cpu/armv7/omap3/board.c
View file

@ -40,6 +40,7 @@
#include <asm/armv7.h>
#include <asm/arch/gpio.h>
#include <asm/omap_common.h>
#include <i2c.h>
/* Declarations */
extern omap3_sysinfo sysinfo;
@ -89,6 +90,10 @@ u32 omap_boot_device(void)
return omap3_boot_device;
}
void spl_board_init(void)
{
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
}
#endif /* CONFIG_SPL_BUILD */

34
onenand_ipl/board/vpac270/vpac270.c → arch/arm/cpu/armv7/omap3/emac.c
View file

@ -1,13 +1,8 @@
/*
* (C) Copyright 2004
* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
* DaVinci EMAC initialization.
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
* (C) Copyright 2011, Ilya Yanok, Emcraft Systems
*
* See file CREDITS for list of people who contributed to this
* project.
@ -24,19 +19,26 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc.
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/am35x_def.h>
int board_init (void)
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(bd_t *bis)
{
return 0;
}
u32 reset;
int s_init(int skip)
{
return 0;
/* ensure that the module is out of reset */
reset = readl(&am35x_scm_general_regs->ip_sw_reset);
reset &= ~CPGMACSS_SW_RST;
writel(reset, &am35x_scm_general_regs->ip_sw_reset);
return davinci_emac_initialize();
}

8
arch/arm/cpu/armv7/omap3/lowlevel_init.S
View file

@ -216,6 +216,14 @@ lowlevel_init:
ldr sp, SRAM_STACK
str ip, [sp] /* stash old link register */
mov ip, lr /* save link reg across call */
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
/*
* No need to copy/exec the clock code - DPLL adjust already done
* in NAND/oneNAND Boot.
*/
ldr r1, =SRAM_CLK_CODE
bl cpy_clk_code
#endif /* NAND Boot */
bl s_init /* go setup pll, mux, memory */
ldr ip, [sp] /* restore save ip */
mov lr, ip /* restore link reg */

13
arch/arm/cpu/armv7/omap3/mem.c
View file

@ -86,6 +86,7 @@ u32 mem_ok(u32 cs)
writel(0x0, addr + 4); /* remove pattern off the bus */
val1 = readl(addr + 0x400); /* get pos A value */
val2 = readl(addr); /* get val2 */
writel(0x0, addr + 0x400); /* clear pos A */
if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
return 0;
@ -105,9 +106,15 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
writel(gpmc_config[3], &cs->config4);
writel(gpmc_config[4], &cs->config5);
writel(gpmc_config[5], &cs->config6);
/* Enable the config */
writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
(1 << 6)), &cs->config7);
/*
* Enable the config. size is the CS size and goes in
* bits 11:8. We set bit 6 to enable this CS and the base
* address goes into bits 5:0.
*/
writel((size << 8) | (GPMC_CS_ENABLE << 6) |
((base >> 24) & GPMC_BASEADDR_MASK),
&cs->config7);
sdelay(2000);
}

147
arch/arm/cpu/armv7/omap3/sdrc.c
View file

@ -58,10 +58,9 @@ u32 is_mem_sdr(void)
/*
* make_cs1_contiguous -
* - For es2 and above remap cs1 behind cs0 to allow command line
* mem=xyz use all memory with out discontinuous support compiled in.
* Could do it at the ATAG, but there really is two banks...
* - Called as part of 2nd phase DDR init.
* - When we have CS1 populated we want to have it mapped after cs0 to allow
* command line mem=xyz use all memory with out discontinuous support
* compiled in. We could do it in the ATAG, but there really is two banks...
*/
void make_cs1_contiguous(void)
{
@ -108,16 +107,59 @@ u32 get_sdr_cs_offset(u32 cs)
return offset;
}
/*
* write_sdrc_timings -
* - Takes CS and associated timings and initalize SDRAM
* - Test CS to make sure it's OK for use
*/
static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr)
{
/* Setup timings we got from the board. */
writel(mcfg, &sdrc_base->cs[cs].mcfg);
writel(ctrla, &sdrc_actim_base->ctrla);
writel(ctrlb, &sdrc_actim_base->ctrlb);
writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
writel(CMD_NOP, &sdrc_base->cs[cs].manual);
writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
writel(mr, &sdrc_base->cs[cs].mr);
/*
* Test ram in this bank
* Disable if bad or not present
*/
if (!mem_ok(cs))
writel(0, &sdrc_base->cs[cs].mcfg);
}
/*
* do_sdrc_init -
* - Initialize the SDRAM for use.
* - code called once in C-Stack only context for CS0 and a possible 2nd
* time depending on memory configuration from stack+global context
* - Code called once in C-Stack only context for CS0 and with early being
* true and a possible 2nd time depending on memory configuration from
* stack+global context.
*/
void do_sdrc_init(u32 cs, u32 early)
{
struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr;
sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
/*
* When called in the early context this may be SPL and we will
* need to set all of the timings. This ends up being board
* specific so we call a helper function to take care of this
* for us. Otherwise, to be safe, we need to copy the settings
* from the first bank to the second. We will setup CS0,
* then set cs_cfg to the appropriate value then try and
* setup CS1.
*/
#ifdef CONFIG_SPL_BUILD
get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr);
#endif
if (early) {
/* reset sdrc controller */
writel(SOFTRESET, &sdrc_base->sysconfig);
@ -128,73 +170,38 @@ void do_sdrc_init(u32 cs, u32 early)
/* setup sdrc to ball mux */
writel(SDRC_SHARING, &sdrc_base->sharing);
/* Disable Power Down of CKE cuz of 1 CKE on combo part */
/* Disable Power Down of CKE because of 1 CKE on combo part */
writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
&sdrc_base->power);
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x20000);
}
/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
* to prevent this to be build in non-SPL build */
#ifdef CONFIG_SPL_BUILD
/* If we use a SPL there is no x-loader nor config header so we have
* to do the job ourselfs
*/
if (cs == CS0) {
sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
/* General SDRC config */
writel(V_MCFG, &sdrc_base->cs[cs].mcfg);
writel(V_RFR_CTRL, &sdrc_base->cs[cs].rfr_ctrl);
/* AC timings */
writel(V_ACTIMA_165, &sdrc_actim_base0->ctrla);
writel(V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
/* Initialize */
writel(CMD_NOP, &sdrc_base->cs[cs].manual);
writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
writel(V_MR, &sdrc_base->cs[cs].mr);
}
write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
rfr_ctrl, mr);
make_cs1_contiguous();
write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb,
rfr_ctrl, mr);
#endif
/*
* SDRC timings are set up by x-load or config header
* We don't need to redo them here.
* Older x-loads configure only CS0
* configure CS1 to handle this ommission
*/
if (cs == CS1) {
sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
writel(readl(&sdrc_base->cs[CS0].mcfg),
&sdrc_base->cs[CS1].mcfg);
writel(readl(&sdrc_base->cs[CS0].rfr_ctrl),
&sdrc_base->cs[CS1].rfr_ctrl);
writel(readl(&sdrc_actim_base0->ctrla),
&sdrc_actim_base1->ctrla);
writel(readl(&sdrc_actim_base0->ctrlb),
&sdrc_actim_base1->ctrlb);
writel(CMD_NOP, &sdrc_base->cs[cs].manual);
writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
writel(readl(&sdrc_base->cs[CS0].mr),
&sdrc_base->cs[CS1].mr);
}
/*
* Test ram in this bank
* Disable if bad or not present
* If we aren't using SPL we have been loaded by some
* other means which may not have correctly initialized
* both CS0 and CS1 (such as some older versions of x-loader)
* so we may be asked now to setup CS1.
*/
if (!mem_ok(cs))
writel(0, &sdrc_base->cs[cs].mcfg);
if (cs == CS1) {
mcfg = readl(&sdrc_base->cs[CS0].mcfg),
rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
ctrla = readl(&sdrc_actim_base0->ctrla),
ctrlb = readl(&sdrc_actim_base0->ctrlb);
mr = readl(&sdrc_base->cs[CS0].mr);
write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb,
rfr_ctrl, mr);
}
}
/*
@ -207,16 +214,16 @@ int dram_init(void)
size0 = get_sdr_cs_size(CS0);
/*
* If a second bank of DDR is attached to CS1 this is
* where it can be started. Early init code will init
* memory on CS0.
* We always need to have cs_cfg point at where the second
* bank would be, if present. Failure to do so can lead to
* strange situations where memory isn't detected and
* configured correctly. CS0 will already have been setup
* at this point.
*/
if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
do_sdrc_init(CS1, NOT_EARLY);
make_cs1_contiguous();
make_cs1_contiguous();
do_sdrc_init(CS1, NOT_EARLY);
size1 = get_sdr_cs_size(CS1);
size1 = get_sdr_cs_size(CS1);
}
gd->ram_size = size0 + size1;
return 0;

87
arch/arm/cpu/armv7/omap3/spl_id_nand.c Normal file
View file

@ -0,0 +1,87 @@
/*
* (C) Copyright 2011
* Texas Instruments, <www.ti.com>
*
* Author :
* Tom Rini <trini@ti.com>
*
* Initial Code from:
* Richard Woodruff <r-woodruff2@ti.com>
* Jian Zhang <jzhang@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/mtd/nand.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE;
/* nand_command: Send a flash command to the flash chip */
static void nand_command(u8 command)
{
writeb(command, &gpmc_config->cs[0].nand_cmd);
if (command == NAND_CMD_RESET) {
unsigned char ret_val;
writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd);
do {
/* Wait until ready */
ret_val = readl(&gpmc_config->cs[0].nand_dat);
} while ((ret_val & NAND_STATUS_READY) != NAND_STATUS_READY);
}
}
/*
* Many boards will want to know the results of the NAND_CMD_READID command
* in order to decide what to do about DDR initialization. This function
* allows us to do that very early and to pass those results back to the
* board so it can make whatever decisions need to be made.
*/
void identify_nand_chip(int *mfr, int *id)
{
/* Make sure that we have setup GPMC for NAND correctly. */
writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1);
writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2);
writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3);
writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4);
writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5);
writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6);
/*
* Enable the config. The CS size goes in bits 11:8. We set
* bit 6 to enable the CS and the base address goes into bits 5:0.
*/
writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) |
((NAND_BASE >> 24) & GPMC_BASEADDR_MASK),
&gpmc_config->cs[0].config7);
sdelay(2000);
/* Issue a RESET and then READID */
nand_command(NAND_CMD_RESET);
nand_command(NAND_CMD_READID);
/* Set the address to read to 0x0 */
writeb(0x0, &gpmc_config->cs[0].nand_adr);
/* Read off the manufacturer and device id. */
*mfr = readb(&gpmc_config->cs[0].nand_dat);
*id = readb(&gpmc_config->cs[0].nand_dat);
}

17
arch/arm/cpu/armv7/omap4/hwinit.c
View file

@ -105,7 +105,12 @@ void do_io_settings(void)
&ctrl->control_ldosram_core_voltage_ctrl);
}
if (!readl(&ctrl->control_efuse_1))
/*
* Over-ride the register
* i. unconditionally for all 4430
* ii. only if un-trimmed for 4460
*/
if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_1))
writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
if (!readl(&ctrl->control_efuse_2))
@ -146,7 +151,15 @@ void init_omap_revision(void)
*omap4_revision = OMAP4430_ES2_3;
break;
case MIDR_CORTEX_A9_R2P10:
*omap4_revision = OMAP4460_ES1_0;
switch (readl(CONTROL_ID_CODE)) {
case OMAP4460_CONTROL_ID_CODE_ES1_1:
*omap4_revision = OMAP4460_ES1_1;
break;
case OMAP4460_CONTROL_ID_CODE_ES1_0:
default:
*omap4_revision = OMAP4460_ES1_0;
break;
}
break;
default:
*omap4_revision = OMAP4430_SILICON_ID_INVALID;

38
arch/arm/cpu/armv7/start.S
View file

@ -32,6 +32,7 @@
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/system.h>
.globl _start
_start: b reset
@ -143,29 +144,22 @@ reset:
orr r0, r0, #0xd3
msr cpsr,r0
#if defined(CONFIG_OMAP34XX)
/* Copy vectors to mask ROM indirect addr */
adr r0, _start @ r0 <- current position of code
add r0, r0, #4 @ skip reset vector
mov r2, #64 @ r2 <- size to copy
add r2, r0, r2 @ r2 <- source end address
mov r1, #SRAM_OFFSET0 @ build vect addr
mov r3, #SRAM_OFFSET1
add r1, r1, r3
mov r3, #SRAM_OFFSET2
add r1, r1, r3
next:
ldmia r0!, {r3 - r10} @ copy from source address [r0]
stmia r1!, {r3 - r10} @ copy to target address [r1]
cmp r0, r2 @ until source end address [r2]
bne next @ loop until equal */
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
/* No need to copy/exec the clock code - DPLL adjust already done
* in NAND/oneNAND Boot.
*/
bl cpy_clk_code @ put dpll adjust code behind vectors
#endif /* NAND Boot */
/*
* Setup vector:
* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
* Continue to use ROM code vector only in OMAP4 spl)
*/
#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
bic r0, #CR_V @ V = 0
mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
/* Set vector address in CP15 VBAR register */
ldr r0, =_start
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit

7
arch/arm/cpu/pxa/Makefile
View file

@ -27,7 +27,12 @@ LIB = $(obj)lib$(CPU).o
START = start.o
COBJS += cpu.o
COBJS-$(CONFIG_CPU_PXA25X) = pxa2xx.o
COBJS-$(CONFIG_CPU_PXA27X) = pxa2xx.o
COBJS-y += cpuinfo.o
COBJS = $(COBJS-y)
COBJS += pxafb.o
COBJS += timer.o
COBJS += usb.o

132
arch/arm/cpu/pxa/cpuinfo.c Normal file
View file

@ -0,0 +1,132 @@
/*
* PXA CPU information display
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <errno.h>
#include <linux/compiler.h>
#define CPU_MASK_PXA_REVID 0x00f
#define CPU_MASK_PXA_PRODID 0x3f0
#define CPU_VALUE_PXA25X 0x100
#define CPU_VALUE_PXA27X 0x110
static uint32_t pxa_get_cpuid(void)
{
uint32_t cpuid;
asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid));
return cpuid;
}
int cpu_is_pxa25x(void)
{
uint32_t id = pxa_get_cpuid();
id &= CPU_MASK_PXA_PRODID;
return id == CPU_VALUE_PXA25X;
}
int cpu_is_pxa27x(void)
{
uint32_t id = pxa_get_cpuid();
id &= CPU_MASK_PXA_PRODID;
return id == CPU_VALUE_PXA27X;
}
#ifdef CONFIG_DISPLAY_CPUINFO
static const char *pxa25x_get_revision(void)
{
static __maybe_unused const char * const revs_25x[] = { "A0" };
static __maybe_unused const char * const revs_26x[] = {
"A0", "B0", "B1"
};
static const char *unknown = "Unknown";
uint32_t id;
if (!cpu_is_pxa25x())
return unknown;
id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
/* PXA26x is a sick special case as it can't be told apart from PXA25x :-( */
#ifdef CONFIG_CPU_PXA26X
switch (id) {
case 3: return revs_26x[0];
case 5: return revs_26x[1];
case 6: return revs_26x[2];
}
#else
if (id == 6)
return revs_25x[0];
#endif
return unknown;
}
static const char *pxa27x_get_revision(void)
{
static const char *const rev[] = { "A0", "A1", "B0", "B1", "C0", "C5" };
static const char *unknown = "Unknown";
uint32_t id;
if (!cpu_is_pxa27x())
return unknown;
id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
if ((id == 5) || (id == 6) || (id > 7))
return unknown;
/* Cap the special PXA270 C5 case. */
if (id == 7)
id = 5;
return rev[id];
}
static int print_cpuinfo_pxa2xx(void)
{
if (cpu_is_pxa25x()) {
puts("Marvell PXA25x rev. ");
puts(pxa25x_get_revision());
} else if (cpu_is_pxa27x()) {
puts("Marvell PXA27x rev. ");
puts(pxa27x_get_revision());
} else
return -EINVAL;
puts("\n");
return 0;
}
int print_cpuinfo(void)
{
int ret;
puts("CPU: ");
ret = print_cpuinfo_pxa2xx();
if (!ret)
return ret;
return ret;
}
#endif

121
arch/arm/cpu/pxa/cpu.c → arch/arm/cpu/pxa/pxa2xx.c
View file

@ -26,88 +26,52 @@
* MA 02111-1307 USA
*/
/*
* CPU specific code
*/
#include <asm/io.h>
#include <asm/system.h>
#include <command.h>
#include <common.h>
#include <asm/arch/pxa-regs.h>
static void cache_flush(void);
int cleanup_before_linux (void)
{
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* just disable everything that can disturb booting linux
*/
disable_interrupts ();
/* turn off I-cache */
icache_disable();
dcache_disable();
/* flush I-cache */
cache_flush();
return (0);
}
/* flush I/D-cache */
static void cache_flush (void)
/* Flush I/D-cache */
static void cache_flush(void)
{
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
}
#ifndef CONFIG_CPU_MONAHANS
void set_GPIO_mode(int gpio_mode)
int cleanup_before_linux(void)
{
int gpio = gpio_mode & GPIO_MD_MASK_NR;
int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
int val;
/*
* This function is called just before we call Linux. It prepares
* the processor for Linux by just disabling everything that can
* disturb booting Linux.
*/
/* This below changes direction setting of GPIO "gpio" */
val = readl(GPDR(gpio));
disable_interrupts();
icache_disable();
dcache_disable();
cache_flush();
if (gpio_mode & GPIO_MD_MASK_DIR)
val |= GPIO_bit(gpio);
else
val &= ~GPIO_bit(gpio);
writel(val, GPDR(gpio));
/* This below updates only AF of GPIO "gpio" */
val = readl(GAFR(gpio));
val &= ~(0x3 << (((gpio) & 0xf) * 2));
val |= fn << (((gpio) & 0xf) * 2);
writel(val, GAFR(gpio));
return 0;
}
#endif /* CONFIG_CPU_MONAHANS */
void pxa_wait_ticks(int ticks)
{
writel(0, OSCR);
while (readl(OSCR) < ticks)
asm volatile("":::"memory");
asm volatile("" : : : "memory");
}
inline void writelrb(uint32_t val, uint32_t addr)
{
writel(val, addr);
asm volatile("":::"memory");
asm volatile("" : : : "memory");
readl(addr);
asm volatile("":::"memory");
asm volatile("" : : : "memory");
}
void pxa_dram_init(void)
void pxa2xx_dram_init(void)
{
uint32_t tmp;
int i;
@ -201,7 +165,7 @@ void pxa_dram_init(void)
*/
for (i = 9; i >= 0; i--) {
writel(i, 0xa0000000);
asm volatile("":::"memory");
asm volatile("" : : : "memory");
}
/*
* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
@ -234,21 +198,21 @@ void pxa_gpio_setup(void)
writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
#endif
writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
#endif
writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
#endif
@ -258,7 +222,7 @@ void pxa_gpio_setup(void)
writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
#endif
@ -270,7 +234,7 @@ void pxa_interrupt_setup(void)
{
writel(0, ICLR);
writel(0, ICMR);
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#if defined(CONFIG_CPU_PXA27X)
writel(0, ICLR2);
writel(0, ICMR2);
#endif
@ -278,18 +242,14 @@ void pxa_interrupt_setup(void)
void pxa_clock_setup(void)
{
#ifndef CONFIG_CPU_MONAHANS
writel(CONFIG_SYS_CKEN, CKEN);
writel(CONFIG_SYS_CCCR, CCCR);
asm volatile("mcr p14, 0, %0, c6, c0, 0"::"r"(2));
#else
/* Set CKENA/CKENB/ACCR for MH */
#endif
asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(2));
/* enable the 32Khz oscillator for RTC and PowerManager */
writel(OSCC_OON, OSCC);
while(!(readl(OSCC) & OSCC_OOK))
asm volatile("":::"memory");
while (!(readl(OSCC) & OSCC_OOK))
asm volatile("" : : : "memory");
}
void pxa_wakeup(void)
@ -302,17 +262,16 @@ void pxa_wakeup(void)
/* Wakeup */
if (rcsr & RCSR_SMR) {
writel(PSSR_PH, PSSR);
pxa_dram_init();
pxa2xx_dram_init();
icache_disable();
dcache_disable();
asm volatile("mov pc, %0"::"r"(readl(PSPR)));
asm volatile("mov pc, %0" : : "r"(readl(PSPR)));
}
}
int arch_cpu_init(void)
{
pxa_gpio_setup();
/* pxa_wait_ticks(0x8000); */
pxa_wakeup();
pxa_interrupt_setup();
pxa_clock_setup();
@ -321,10 +280,22 @@ int arch_cpu_init(void)
void i2c_clk_enable(void)
{
/* set the global I2C clock on */
#ifdef CONFIG_CPU_MONAHANS
writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
#else
/* Set the global I2C clock on */
writel(readl(CKEN) | CKEN14_I2C, CKEN);
#endif
}
void reset_cpu(ulong ignored) __attribute__((noreturn));
void reset_cpu(ulong ignored)
{
uint32_t tmp;
setbits_le32(OWER, OWER_WME);
tmp = readl(OSCR);
tmp += 0x1000;
writel(tmp, OSMR3);
for (;;)
;
}

456
arch/arm/cpu/pxa/start.S
View file

@ -1,14 +1,20 @@
/*
* armboot - Startup Code for XScale
* armboot - Startup Code for XScale CPU-core
*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
* Copyright (C) 2001 Marius Groger <mag@sysgo.de>
* Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
* Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
* Copyright (c) 2010 Marek Vasut <marek.vasut@gmail.com>
* Copyright (C) 2003 Kshitij <kshitij@ti.com>
* Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@ -32,14 +38,12 @@
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
/* takes care the CP15 update has taken place */
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
#ifdef CONFIG_CPU_PXA25X
#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
#error "Init SP address must be set to 0xfffff800 for PXA250"
#endif
#endif
.globl _start
_start: b reset
@ -77,26 +81,38 @@ _data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
_pad: .word 0x12345678 /* now 16*4=64 */
#endif /* CONFIG_SPL_BUILD */
.global _end_vect
_end_vect:
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from RAM!
* - relocate armboot to RAM
* - setup stack
* - jump to second stage
* do important init only if we don't start from memory!
* setup Memory and board specific bits prior to relocation.
* relocate armboot to ram
* setup stack
*
*************************************************************************
*/
.globl _TEXT_BASE
_TEXT_BASE:
#ifdef CONFIG_SPL_BUILD
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
#endif
/*
* These are defined in the board-specific linker script.
* Subtracting _start from them lets the linker put their
* relative position in the executable instead of leaving
* them null.
*/
.globl _bss_start_ofs
_bss_start_ofs:
@ -120,9 +136,8 @@ IRQ_STACK_START:
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif /* CONFIG_USE_IRQ */
#endif
#ifndef CONFIG_SPL_BUILD
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@ -141,95 +156,23 @@ reset:
orr r0,r0,#0xd3
msr cpsr,r0
/*
* Enable MMU to use DCache as DRAM
*/
/* Domain access -- enable for all CPs */
ldr r0, =0x0000ffff
mcr p15, 0, r0, c3, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
/* Point TTBR to MMU table */
ldr r0, =mmu_table
adr r2, _start
orr r0, r2
mcr p15, 0, r0, c2, c0, 0
/* !!! Hereby, check if the code is running from SRAM !!! */
/* If the code is running from SRAM, alias SRAM to 0x0 to simulate NOR. The code
* is linked to 0x0 too, so this makes things easier. */
cmp r2, #0x5c000000
ldreq r1, [r0]
orreq r1, r2
streq r1, [r0]
/* Kick in MMU, ICache, DCache, BTB */
mrc p15, 0, r0, c1, c0, 0
bic r0, #0x1b00
bic r0, #0x0087
orr r0, #0x1800
orr r0, #0x0005
mcr p15, 0, r0, c1, c0, 0
CPWAIT r0
/* Unlock Icache, Dcache */
mcr p15, 0, r0, c9, c1, 1
mcr p15, 0, r0, c9, c2, 1
/* Flush Icache, Dcache, BTB */
mcr p15, 0, r0, c7, c7, 0
/* Unlock I-TLB, D-TLB */
mcr p15, 0, r0, c10, c4, 1
mcr p15, 0, r0, c10, c8, 1
/* Flush TLB */
mcr p15, 0, r0, c8, c7, 0
/* Allocate 4096 bytes of Dcache as RAM */
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
mov r4, #0x00
mov r5, #0x00
mov r2, #0x01
mcr p15, 0, r0, c9, c2, 0
CPWAIT r0
/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
mov r0, #128
mov r1, #0xa0000000
alloc:
mcr p15, 0, r1, c7, c2, 5
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
strd r4, [r1], #8
strd r4, [r1], #8
strd r4, [r1], #8
strd r4, [r1], #8
subs r0, #0x01
bne alloc
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
mov r2, #0x00
mcr p15, 0, r2, c9, c2, 0
CPWAIT r0
/* Jump to 0x0 ( + offset) if running from SRAM */
adr r0, zerojmp
bic r0, #0x5c000000
mov pc, r0
zerojmp:
#ifdef CONFIG_CPU_PXA25X
bl lock_cache_for_stack
#endif
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
ldr r0, =0x00000000
bl board_init_f
/*------------------------------------------------------------------------------*/
#ifndef CONFIG_SPL_BUILD
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
@ -247,6 +190,11 @@ relocate_code:
stack_setup:
mov sp, r4
/* Disable the Dcache RAM lock for stack now */
#ifdef CONFIG_CPU_PXA25X
bl cpu_init_crit
#endif
adr r0, _start
cmp r0, r6
beq clear_bss /* skip relocation */
@ -254,13 +202,11 @@ stack_setup:
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
stmfd sp!, {r0-r12}
copy_loop:
ldmia r0!, {r3-r5, r7-r11} /* copy from source address [r0] */
stmia r1!, {r3-r5, r7-r11} /* copy to target address [r1] */
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
ldmfd sp!, {r0-r12}
#ifndef CONFIG_SPL_BUILD
/*
@ -275,13 +221,13 @@ copy_loop:
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r9 /* r0 <- location to fix up in RAM */
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r7, #2 /* absolute fixup? */
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -298,10 +244,10 @@ fixrel:
add r1, r1, r9
fixnext:
str r1, [r0]
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
blo fixloop
#endif /* #ifndef CONFIG_SPL_BUILD */
#endif
clear_bss:
#ifndef CONFIG_SPL_BUILD
@ -322,15 +268,16 @@ clbss_l:str r2, [r0] /* clear loop... */
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
#ifdef CONFIG_ONENAND_IPL
ldr r0, _start_oneboot_ofs
#ifdef CONFIG_ONENAND_SPL
ldr r0, _onenand_boot_ofs
mov pc, r0
_start_oneboot_ofs
: .word start_oneboot
_onenand_boot_ofs:
.word onenand_boot
#else
jump_2_ram:
ldr r0, _board_init_r_ofs
adr r1, _start
ldr r1, _TEXT_BASE
add lr, r0, r1
add lr, lr, r9
/* setup parameters for board_init_r */
@ -341,7 +288,7 @@ _start_oneboot_ofs
_board_init_r_ofs:
.word board_init_r - _start
#endif /* CONFIG_ONENAND_IPL */
#endif
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
@ -349,43 +296,50 @@ _rel_dyn_end_ofs:
.word __rel_dyn_end - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
#else /* CONFIG_SPL_BUILD */
/****************************************************************************/
/* */
/* the actual reset code for OneNAND IPL */
/* */
/****************************************************************************/
#ifndef CONFIG_PXA27X
#error OneNAND IPL is not supported on PXA25x and 26x due to lack of SRAM
#endif
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
cpu_init_crit:
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
reset:
/* Set CPU to SVC32 mode */
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0x13
msr cpsr,r0
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
/* Point stack at the end of SRAM and leave 32 words for abort-stack */
ldr sp, =0x5c03ff80
/* Start OneNAND IPL */
ldr pc, =start_oneboot
#endif /* CONFIG_SPL_BUILD */
mov pc, lr /* back to my caller */
#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
#ifndef CONFIG_SPL_BUILD
/****************************************************************************/
/* */
/* Interrupt handling */
/* */
/****************************************************************************/
/* IRQ stack frame */
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
@ -409,37 +363,36 @@ reset:
#define S_R0 0
#define MODE_SVC 0x13
#define I_BIT 0x80
/* use bad_save_user_regs for abort/prefetch/undef/swi ... */
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
*/
.macro bad_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} /* Calling r0-r12 */
add r8, sp, #S_PC
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, IRQ_STACK_START_IN
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
add r5, sp, #S_SP
mov r1, lr
stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
mov r0, sp
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
mov r0, sp @ save current stack into r0 (param register)
.endm
/* use irq_save_user_regs / irq_restore_user_regs for */
/* IRQ/FIQ handling */
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} /* Calling r0-r12 */
add r8, sp, #S_PC
stmdb r8, {sp, lr}^ /* Calling SP, LR */
str lr, [r8, #0] /* Save calling PC */
stmia sp, {r0 - r12} @ Calling r0-r12
add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
stmdb r8, {sp, lr}^ @ Calling SP, LR
str lr, [r8, #0] @ Save calling PC
mrs r6, spsr
str r6, [r8, #4] /* Save CPSR */
str r0, [r8, #8] /* Save OLD_R0 */
str r6, [r8, #4] @ Save CPSR
str r0, [r8, #8] @ Save OLD_R0
mov r0, sp
.endm
@ -452,16 +405,28 @@ reset:
.endm
.macro get_bad_stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
str lr, [r13, #4]
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
str lr, [r13, #4] @ save spsr in position 1 of saved stack
mov r13, #MODE_SVC @ prepare SVC-Mode
msr spsr_c, r13
mov lr, pc
movs pc, lr
@ msr spsr_c, r13
msr spsr, r13 @ switch modes, make sure moves will execute
mov lr, pc @ capture return pc
movs pc, lr @ jump to next instruction & switch modes.
.endm
.macro get_bad_stack_swi
sub r13, r13, #4 @ space on current stack for scratch reg.
str r0, [r13] @ save R0's value.
ldr r0, IRQ_STACK_START_IN @ get data regions start
str lr, [r0] @ save caller lr in position 0 of saved stack
mrs r0, spsr @ get the spsr
str lr, [r0, #4] @ save spsr in position 1 of saved stack
ldr r0, [r13] @ restore r0
add r13, r13, #4 @ pop stack entry
.endm
.macro get_irq_stack @ setup IRQ stack
@ -471,21 +436,17 @@ reset:
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
#endif /* CONFIG_SPL_BUILD
/****************************************************************************/
/* */
/* exception handlers */
/* */
/****************************************************************************/
#endif /* CONFIG_SPL_BUILD */
/*
* exception handlers
*/
#ifdef CONFIG_SPL_BUILD
.align 5
do_hang:
ldr sp, _TEXT_BASE /* use 32 words abort stack */
ldr sp, _TEXT_BASE /* use 32 words about stack */
bl hang /* hang and never return */
#else
#else /* !CONFIG_SPL_BUILD */
.align 5
undefined_instruction:
get_bad_stack
@ -494,7 +455,7 @@ undefined_instruction:
.align 5
software_interrupt:
get_bad_stack
get_bad_stack_swi
bad_save_user_regs
bl do_software_interrupt
@ -528,11 +489,12 @@ irq:
.align 5
fiq:
get_fiq_stack
irq_save_user_regs /* someone ought to write a more */
bl do_fiq /* effiction fiq_save_user_regs */
/* someone ought to write a more effiction fiq_save_user_regs */
irq_save_user_regs
bl do_fiq
irq_restore_user_regs
#else /* !CONFIG_USE_IRQ */
#else
.align 5
irq:
@ -545,63 +507,99 @@ fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif
.align 5
#endif /* CONFIG_SPL_BUILD */
#endif /* CONFIG_USE_IRQ */
/****************************************************************************/
/* */
/* Reset function: the PXA250 doesn't have a reset function, so we have to */
/* perform a watchdog timeout for a soft reset. */
/* */
/****************************************************************************/
/* Operating System Timer */
.align 5
.globl reset_cpu
/* FIXME: this code is PXA250 specific. How is this handled on */
/* other XScale processors? */
/*
* Enable MMU to use DCache as DRAM.
*
* This is useful on PXA25x and PXA26x in early bootstages, where there is no
* other possible memory available to hold stack.
*/
#ifdef CONFIG_CPU_PXA25X
.macro CPWAIT reg
mrc p15, 0, \reg, c2, c0, 0
mov \reg, \reg
sub pc, pc, #4
.endm
lock_cache_for_stack:
/* Domain access -- enable for all CPs */
ldr r0, =0x0000ffff
mcr p15, 0, r0, c3, c0, 0
reset_cpu:
/* Point TTBR to MMU table */
ldr r0, =mmutable
mcr p15, 0, r0, c2, c0, 0
/* We set OWE:WME (watchdog enable) and wait until timeout happens */
/* Kick in MMU, ICache, DCache, BTB */
mrc p15, 0, r0, c1, c0, 0
bic r0, #0x1b00
bic r0, #0x0087
orr r0, #0x1800
orr r0, #0x0005
mcr p15, 0, r0, c1, c0, 0
CPWAIT r0
ldr r0, =OWER
ldr r1, [r0]
orr r1, r1, #0x0001 /* bit0: WME */
str r1, [r0]
/* Unlock Icache, Dcache */
mcr p15, 0, r0, c9, c1, 1
mcr p15, 0, r0, c9, c2, 1
/* OS timer does only wrap every 1165 seconds, so we have to set */
/* the match register as well. */
/* Flush Icache, Dcache, BTB */
mcr p15, 0, r0, c7, c7, 0
ldr r0, =OSCR
ldr r1, [r0] /* read OS timer */
add r1, r1, #0x800 /* let OSMR3 match after */
add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
ldr r0, =OSMR3
str r1, [r0]
/* Unlock I-TLB, D-TLB */
mcr p15, 0, r0, c10, c4, 1
mcr p15, 0, r0, c10, c8, 1
reset_endless:
/* Flush TLB */
mcr p15, 0, r0, c8, c7, 0
b reset_endless
/* Allocate 4096 bytes of Dcache as RAM */
#ifndef CONFIG_SPL_BUILD
.section .mmudata, "a"
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
mov r4, #0x00
mov r5, #0x00
mov r2, #0x01
mcr p15, 0, r0, c9, c2, 0
CPWAIT r0
/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
mov r0, #128
ldr r1, =0xfffff000
alloc:
mcr p15, 0, r1, c7, c2, 5
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
strd r4, [r1], #8
strd r4, [r1], #8
strd r4, [r1], #8
strd r4, [r1], #8
subs r0, #0x01
bne alloc
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
mov r2, #0x00
mcr p15, 0, r2, c9, c2, 0
CPWAIT r0
mov pc, lr
.section .mmutable, "a"
mmutable:
.align 14
.globl mmu_table
mmu_table:
/* 0x00000000 - 0xa0000000 : 1:1, uncached mapping */
/* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
.set __base, 0
.rept 0xa00
.rept 0xfff
.word (__base << 20) | 0xc12
.set __base, __base + 1
.endr
/* 0xa0000000 - 0xa0100000 : 1:1, cached mapping */
.word (0xa00 << 20) | 0x1c1e
.set __base, 0xa01
.rept 0x1000 - 0xa01
.word (__base << 20) | 0xc12
.set __base, __base + 1
.endr
#endif /* CONFIG_SPL_BUILD */
/* 0xfff00000 : 1:1, cached mapping */
.word (0xfff << 20) | 0x1c1e
#endif /* CONFIG_CPU_PXA25X */

91
arch/arm/cpu/pxa/timer.c
View file

@ -1,11 +1,7 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
* Marvell PXA2xx/3xx timer driver
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@ -31,55 +27,63 @@
#include <common.h>
#include <div64.h>
#ifdef CONFIG_USE_IRQ
#error: interrupts not implemented yet
#endif
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define TIMER_FREQ_HZ 3250000
#elif defined(CONFIG_PXA250)
#define TIMER_FREQ_HZ 3686400
#define TIMER_LOAD_VAL 0xffffffff
#define timestamp (gd->tbl)
#define lastinc (gd->lastinc)
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define TIMER_FREQ_HZ 3250000
#elif defined(CONFIG_CPU_PXA25X)
#define TIMER_FREQ_HZ 3686400
#else
#error "Timer frequency unknown - please config PXA CPU type"
#endif
static inline unsigned long long tick_to_time(unsigned long long tick)
static unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, TIMER_FREQ_HZ);
return tick;
return tick * CONFIG_SYS_HZ / TIMER_FREQ_HZ;
}
static inline unsigned long long us_to_tick(unsigned long long us)
static unsigned long long us_to_tick(unsigned long long us)
{
us = us * TIMER_FREQ_HZ + 999999;
do_div(us, 1000000);
return us;
return (us * TIMER_FREQ_HZ) / 1000000;
}
int timer_init (void)
int timer_init(void)
{
writel(0, OSCR);
return 0;
}
ulong get_timer (ulong base)
unsigned long long get_ticks(void)
{
return get_timer_masked () - base;
/* Current tick value */
uint32_t now = readl(OSCR);
if (now >= lastinc) {
/*
* Normal mode (non roll)
* Move stamp forward with absolute diff ticks
*/
timestamp += (now - lastinc);
} else {
/* We have rollover of incrementer */
timestamp += (TIMER_LOAD_VAL - lastinc) + now;
}
lastinc = now;
return timestamp;
}
void __udelay (unsigned long usec)
ulong get_timer(ulong base)
{
udelay_masked (usec);
return tick_to_time(get_ticks()) - base;
}
ulong get_timer_masked (void)
{
return tick_to_time(get_ticks());
}
void udelay_masked (unsigned long usec)
void __udelay(unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
@ -89,25 +93,4 @@ void udelay_masked (unsigned long usec)
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return readl(OSCR);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk (void)
{
ulong tbclk;
tbclk = TIMER_FREQ_HZ;
return tbclk;
}

6
arch/arm/cpu/pxa/u-boot.lds
View file

@ -63,6 +63,12 @@ SECTIONS
*(.dynsym)
}
. = ALIGN(4096);
.mmutable : {
*(.mmutable)
}
_end = .;
.bss __rel_dyn_start (OVERLAY) : {

12
arch/arm/cpu/pxa/usb.c
View file

@ -24,7 +24,7 @@
#include <common.h>
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
@ -37,7 +37,7 @@ int usb_cpu_init(void)
writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
udelay(100);
#endif
#if defined(CONFIG_PXA27X)
#if defined(CONFIG_CPU_PXA27X)
/* Enable USB host clock. */
writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
#endif
@ -58,7 +58,7 @@ int usb_cpu_init(void)
#if defined(CONFIG_CPU_MONAHANS)
writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_PXA27X)
#if defined(CONFIG_CPU_PXA27X)
writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
#endif
writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
@ -78,7 +78,7 @@ int usb_cpu_stop(void)
#if defined(CONFIG_CPU_MONAHANS)
writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_PXA27X)
#if defined(CONFIG_CPU_PXA27X)
writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
#endif
writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
@ -88,7 +88,7 @@ int usb_cpu_stop(void)
writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
udelay(100);
#endif
#if defined(CONFIG_PXA27X)
#if defined(CONFIG_CPU_PXA27X)
/* Disable USB host clock. */
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
#endif
@ -101,5 +101,5 @@ int usb_cpu_init_fail(void)
return usb_cpu_stop();
}
# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */
# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */

289
arch/arm/include/asm/arch-davinci/emac_defs.h
View file

@ -84,295 +84,6 @@
#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
#endif
/* Ethernet Min/Max packet size */
#define EMAC_MIN_ETHERNET_PKT_SIZE 60
#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */
/* Number of RX packet buffers
* NOTE: Only 1 buffer supported as of now
*/
#define EMAC_MAX_RX_BUFFERS 10
/***********************************************
******** Internally used macros ***************
***********************************************/
#define EMAC_CH_TX 1
#define EMAC_CH_RX 0
/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
* reserve space for 64 descriptors max
*/
#define EMAC_RX_DESC_BASE 0x0
#define EMAC_TX_DESC_BASE 0x1000
/* EMAC Teardown value */
#define EMAC_TEARDOWN_VALUE 0xfffffffc
/* MII Status Register */
#define MII_STATUS_REG 1
/* Number of statistics registers */
#define EMAC_NUM_STATS 36
/* EMAC Descriptor */
typedef volatile struct _emac_desc
{
u_int32_t next; /* Pointer to next descriptor in chain */
u_int8_t *buffer; /* Pointer to data buffer */
u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
} emac_desc;
/* CPPI bit positions */
#define EMAC_CPPI_SOP_BIT (0x80000000)
#define EMAC_CPPI_EOP_BIT (0x40000000)
#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
#define EMAC_CPPI_EOQ_BIT (0x10000000)
#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
#define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
#define EMAC_MAC_ADDR_MATCH (1 << 19)
#define EMAC_MAC_ADDR_IS_VALID (1 << 20)
#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
#define MDIO_CONTROL_IDLE (0x80000000)
#define MDIO_CONTROL_ENABLE (0x40000000)
#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
#define MDIO_CONTROL_FAULT (0x80000)
#define MDIO_USERACCESS0_GO (0x80000000)
#define MDIO_USERACCESS0_WRITE_READ (0x0)
#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
#define MDIO_USERACCESS0_ACK (0x20000000)
/* Ethernet MAC Registers Structure */
typedef struct {
dv_reg TXIDVER;
dv_reg TXCONTROL;
dv_reg TXTEARDOWN;
u_int8_t RSVD0[4];
dv_reg RXIDVER;
dv_reg RXCONTROL;
dv_reg RXTEARDOWN;
u_int8_t RSVD1[100];
dv_reg TXINTSTATRAW;
dv_reg TXINTSTATMASKED;
dv_reg TXINTMASKSET;
dv_reg TXINTMASKCLEAR;
dv_reg MACINVECTOR;
u_int8_t RSVD2[12];
dv_reg RXINTSTATRAW;
dv_reg RXINTSTATMASKED;
dv_reg RXINTMASKSET;
dv_reg RXINTMASKCLEAR;
dv_reg MACINTSTATRAW;
dv_reg MACINTSTATMASKED;
dv_reg MACINTMASKSET;
dv_reg MACINTMASKCLEAR;
u_int8_t RSVD3[64];
dv_reg RXMBPENABLE;
dv_reg RXUNICASTSET;
dv_reg RXUNICASTCLEAR;
dv_reg RXMAXLEN;
dv_reg RXBUFFEROFFSET;
dv_reg RXFILTERLOWTHRESH;
u_int8_t RSVD4[8];
dv_reg RX0FLOWTHRESH;
dv_reg RX1FLOWTHRESH;
dv_reg RX2FLOWTHRESH;
dv_reg RX3FLOWTHRESH;
dv_reg RX4FLOWTHRESH;
dv_reg RX5FLOWTHRESH;
dv_reg RX6FLOWTHRESH;
dv_reg RX7FLOWTHRESH;
dv_reg RX0FREEBUFFER;
dv_reg RX1FREEBUFFER;
dv_reg RX2FREEBUFFER;
dv_reg RX3FREEBUFFER;
dv_reg RX4FREEBUFFER;
dv_reg RX5FREEBUFFER;
dv_reg RX6FREEBUFFER;
dv_reg RX7FREEBUFFER;
dv_reg MACCONTROL;
dv_reg MACSTATUS;
dv_reg EMCONTROL;
dv_reg FIFOCONTROL;
dv_reg MACCONFIG;
dv_reg SOFTRESET;
u_int8_t RSVD5[88];
dv_reg MACSRCADDRLO;
dv_reg MACSRCADDRHI;
dv_reg MACHASH1;
dv_reg MACHASH2;
dv_reg BOFFTEST;
dv_reg TPACETEST;
dv_reg RXPAUSE;
dv_reg TXPAUSE;
u_int8_t RSVD6[16];
dv_reg RXGOODFRAMES;
dv_reg RXBCASTFRAMES;
dv_reg RXMCASTFRAMES;
dv_reg RXPAUSEFRAMES;
dv_reg RXCRCERRORS;
dv_reg RXALIGNCODEERRORS;
dv_reg RXOVERSIZED;
dv_reg RXJABBER;
dv_reg RXUNDERSIZED;
dv_reg RXFRAGMENTS;
dv_reg RXFILTERED;
dv_reg RXQOSFILTERED;
dv_reg RXOCTETS;
dv_reg TXGOODFRAMES;
dv_reg TXBCASTFRAMES;
dv_reg TXMCASTFRAMES;
dv_reg TXPAUSEFRAMES;
dv_reg TXDEFERRED;
dv_reg TXCOLLISION;
dv_reg TXSINGLECOLL;
dv_reg TXMULTICOLL;
dv_reg TXEXCESSIVECOLL;
dv_reg TXLATECOLL;
dv_reg TXUNDERRUN;
dv_reg TXCARRIERSENSE;
dv_reg TXOCTETS;
dv_reg FRAME64;
dv_reg FRAME65T127;
dv_reg FRAME128T255;
dv_reg FRAME256T511;
dv_reg FRAME512T1023;
dv_reg FRAME1024TUP;
dv_reg NETOCTETS;
dv_reg RXSOFOVERRUNS;
dv_reg RXMOFOVERRUNS;
dv_reg RXDMAOVERRUNS;
u_int8_t RSVD7[624];
dv_reg MACADDRLO;
dv_reg MACADDRHI;
dv_reg MACINDEX;
u_int8_t RSVD8[244];
dv_reg TX0HDP;
dv_reg TX1HDP;
dv_reg TX2HDP;
dv_reg TX3HDP;
dv_reg TX4HDP;
dv_reg TX5HDP;
dv_reg TX6HDP;
dv_reg TX7HDP;
dv_reg RX0HDP;
dv_reg RX1HDP;
dv_reg RX2HDP;
dv_reg RX3HDP;
dv_reg RX4HDP;
dv_reg RX5HDP;
dv_reg RX6HDP;
dv_reg RX7HDP;
dv_reg TX0CP;
dv_reg TX1CP;
dv_reg TX2CP;
dv_reg TX3CP;
dv_reg TX4CP;
dv_reg TX5CP;
dv_reg TX6CP;
dv_reg TX7CP;
dv_reg RX0CP;
dv_reg RX1CP;
dv_reg RX2CP;
dv_reg RX3CP;
dv_reg RX4CP;
dv_reg RX5CP;
dv_reg RX6CP;
dv_reg RX7CP;
} emac_regs;
/* EMAC Wrapper Registers Structure */
typedef struct {
#ifdef DAVINCI_EMAC_VERSION2
dv_reg idver;
dv_reg softrst;
dv_reg emctrl;
dv_reg c0rxthreshen;
dv_reg c0rxen;
dv_reg c0txen;
dv_reg c0miscen;
dv_reg c1rxthreshen;
dv_reg c1rxen;
dv_reg c1txen;
dv_reg c1miscen;
dv_reg c2rxthreshen;
dv_reg c2rxen;
dv_reg c2txen;
dv_reg c2miscen;
dv_reg c0rxthreshstat;
dv_reg c0rxstat;
dv_reg c0txstat;
dv_reg c0miscstat;
dv_reg c1rxthreshstat;
dv_reg c1rxstat;
dv_reg c1txstat;
dv_reg c1miscstat;
dv_reg c2rxthreshstat;
dv_reg c2rxstat;
dv_reg c2txstat;
dv_reg c2miscstat;
dv_reg c0rximax;
dv_reg c0tximax;
dv_reg c1rximax;
dv_reg c1tximax;
dv_reg c2rximax;
dv_reg c2tximax;
#else
u_int8_t RSVD0[4100];
dv_reg EWCTL;
dv_reg EWINTTCNT;
#endif
} ewrap_regs;
/* EMAC MDIO Registers Structure */
typedef struct {
dv_reg VERSION;
dv_reg CONTROL;
dv_reg ALIVE;
dv_reg LINK;
dv_reg LINKINTRAW;
dv_reg LINKINTMASKED;
u_int8_t RSVD0[8];
dv_reg USERINTRAW;
dv_reg USERINTMASKED;
dv_reg USERINTMASKSET;
dv_reg USERINTMASKCLEAR;
u_int8_t RSVD1[80];
dv_reg USERACCESS0;
dv_reg USERPHYSEL0;
dv_reg USERACCESS1;
dv_reg USERPHYSEL1;
} mdio_regs;
int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
typedef struct
{
char name[64];
int (*init)(int phy_addr);
int (*is_phy_connected)(int phy_addr);
int (*get_link_speed)(int phy_addr);
int (*auto_negotiate)(int phy_addr);
} phy_t;
#define PHY_KSZ8873 (0x00221450)
int ksz8873_is_phy_connected(int phy_addr);
int ksz8873_get_link_speed(int phy_addr);

41
arch/arm/include/asm/arch-davinci/hardware.h
View file

@ -480,6 +480,8 @@ struct davinci_syscfg_regs {
#define davinci_syscfg_regs \
((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
/* Emulation suspend bits */
#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
@ -586,4 +588,43 @@ static inline int get_async3_src(void)
#include <asm/arch/syscfg_defs.h>
#include <asm/arch/timer_defs.h>
#endif
struct davinci_rtc {
dv_reg second;
dv_reg minutes;
dv_reg hours;
dv_reg day;
dv_reg month; /* 0x10 */
dv_reg year;
dv_reg dotw;
dv_reg resv1;
dv_reg alarmsecond; /* 0x20 */
dv_reg alarmminute;
dv_reg alarmhour;
dv_reg alarmday;
dv_reg alarmmonth; /* 0x30 */
dv_reg alarmyear;
dv_reg resv2[2];
dv_reg ctrl; /* 0x40 */
dv_reg status;
dv_reg irq;
dv_reg complsb;
dv_reg compmsb; /* 0x50 */
dv_reg osc;
dv_reg resv3[2];
dv_reg scratch0; /* 0x60 */
dv_reg scratch1;
dv_reg scratch2;
dv_reg kick0r;
dv_reg kick1r; /* 0x70 */
};
#define RTC_STATE_BUSY 0x01
#define RTC_STATE_RUN 0x02
#define RTC_KICK0R_WE 0x130be783
#define RTC_KICK1R_WE 0xe0f1a495
#define davinci_rtc_base ((struct davinci_rtc *)DAVINCI_RTC_BASE)
#endif /* __ASM_ARCH_HARDWARE_H */

51
arch/arm/include/asm/arch-davinci/pinmux_defs.h Normal file
View file

@ -0,0 +1,51 @@
/*
* Pinmux configurations for the DAxxx SoCs
*
* Copyright (C) 2011 OMICRON electronics GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_PINMUX_DEFS_H
#define __ASM_ARCH_PINMUX_DEFS_H
#include <asm/arch/davinci_misc.h>
/* SPI pin muxer settings */
extern const struct pinmux_config spi1_pins_base[3];
extern const struct pinmux_config spi1_pins_scs0[1];
/* UART pin muxer settings */
extern const struct pinmux_config uart1_pins_txrx[2];
extern const struct pinmux_config uart2_pins_txrx[2];
extern const struct pinmux_config uart2_pins_rtscts[2];
/* EMAC pin muxer settings*/
extern const struct pinmux_config emac_pins_rmii[7];
extern const struct pinmux_config emac_pins_mii[15];
extern const struct pinmux_config emac_pins_mdio[2];
/* I2C pin muxer settings */
extern const struct pinmux_config i2c0_pins[2];
extern const struct pinmux_config i2c1_pins[2];
/* EMIFA pin muxer settings */
extern const struct pinmux_config emifa_pins_cs2[1];
extern const struct pinmux_config emifa_pins_cs3[1];
extern const struct pinmux_config emifa_pins_cs4[1];
extern const struct pinmux_config emifa_pins_nand[12];
extern const struct pinmux_config emifa_pins_nor[43];
#endif

10
arch/arm/include/asm/arch-mx25/imx-regs.h
View file

@ -180,8 +180,8 @@ struct aips_regs {
#define IMX_I2C3_BASE (0x43F84000)
#define IMX_CAN1_BASE (0x43F88000)
#define IMX_CAN2_BASE (0x43F8C000)
#define IMX_UART1_BASE (0x43F90000)
#define IMX_UART2_BASE (0x43F94000)
#define UART1_BASE (0x43F90000)
#define UART2_BASE (0x43F94000)
#define IMX_I2C2_BASE (0x43F98000)
#define IMX_OWIRE_BASE (0x43F9C000)
#define IMX_CSPI1_BASE (0x43FA4000)
@ -197,15 +197,15 @@ struct aips_regs {
/* SPBA */
#define IMX_SPBA_BASE (0x50000000)
#define IMX_CSPI3_BASE (0x50004000)
#define IMX_UART4_BASE (0x50008000)
#define IMX_UART3_BASE (0x5000C000)
#define UART4_BASE (0x50008000)
#define UART3_BASE (0x5000C000)
#define IMX_CSPI2_BASE (0x50010000)
#define IMX_SSI2_BASE (0x50014000)
#define IMX_ESAI_BASE (0x50018000)
#define IMX_ATA_DMA_BASE (0x50020000)
#define IMX_SIM1_BASE (0x50024000)
#define IMX_SIM2_BASE (0x50028000)
#define IMX_UART5_BASE (0x5002C000)
#define UART5_BASE (0x5002C000)
#define IMX_TSC_BASE (0x50030000)
#define IMX_SSI1_BASE (0x50034000)
#define IMX_FEC_BASE (0x50038000)

8
arch/arm/include/asm/arch-mx27/imx-regs.h
View file

@ -224,10 +224,10 @@ struct fuse_bank0_regs {
#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE)
#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE)
#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE)
#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE)
#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE)
#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE)
#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE)
#define UART1_BASE (0x0a000 + IMX_IO_BASE)
#define UART2_BASE (0x0b000 + IMX_IO_BASE)
#define UART3_BASE (0x0c000 + IMX_IO_BASE)
#define UART4_BASE (0x0d000 + IMX_IO_BASE)
#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE)
#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE)

25
arch/arm/include/asm/arch-mx28/dma.h
View file

@ -135,36 +135,11 @@ struct mxs_dma_chan {
struct list_head done;
};
/* Hardware management ops */
int mxs_dma_enable(int channel);
int mxs_dma_disable(int channel);
int mxs_dma_reset(int channel);
int mxs_dma_freeze(int channel);
int mxs_dma_unfreeze(int channel);
int mxs_dma_read_semaphore(int channel);
int mxs_dma_enable_irq(int channel, int enable);
int mxs_dma_irq_is_pending(int channel);
int mxs_dma_ack_irq(int channel);
/* Channel management ops */
int mxs_dma_request(int channel);
int mxs_dma_release(int channel);
/* Descriptor management ops */
struct mxs_dma_desc *mxs_dma_desc_alloc(void);
void mxs_dma_desc_free(struct mxs_dma_desc *);
unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc);
int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc);
int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
int mxs_dma_get_finished(int channel, struct list_head *head);
int mxs_dma_finish(int channel, struct list_head *head);
int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan);
int mxs_dma_go(int chan);
int mxs_dma_init(void);
#endif /* __DMA_H__ */

6
arch/arm/include/asm/arch-mx31/imx-regs.h
View file

@ -600,6 +600,12 @@ struct esdc_regs {
#define WEIM_ESDCFG1 0xB800100C
#define WEIM_ESDMISC 0xB8001010
#define UART1_BASE 0x43F90000
#define UART2_BASE 0x43F94000
#define UART3_BASE 0x5000C000
#define UART4_BASE 0x43FB0000
#define UART5_BASE 0x43FB4000
#define ESDCTL_SDE (1 << 31)
#define ESDCTL_CMD_RW (0 << 28)
#define ESDCTL_CMD_PRECHARGE (1 << 28)

6
arch/arm/include/asm/arch-mx35/imx-regs.h
View file

@ -42,8 +42,8 @@
#define I2C_BASE_ADDR 0x43F80000
#define I2C3_BASE_ADDR 0x43F84000
#define ATA_BASE_ADDR 0x43F8C000
#define UART1_BASE_ADDR 0x43F90000
#define UART2_BASE_ADDR 0x43F94000
#define UART1_BASE 0x43F90000
#define UART2_BASE 0x43F94000
#define I2C2_BASE_ADDR 0x43F98000
#define CSPI1_BASE_ADDR 0x43FA4000
#define IOMUXC_BASE_ADDR 0x43FAC000
@ -52,7 +52,7 @@
* SPBA
*/
#define SPBA_BASE_ADDR 0x50000000
#define UART3_BASE_ADDR 0x5000C000
#define UART3_BASE 0x5000C000
#define CSPI2_BASE_ADDR 0x50010000
#define ATA_DMA_BASE_ADDR 0x50020000
#define FEC_BASE_ADDR 0x50038000

6
arch/arm/include/asm/arch-mx5/imx-regs.h
View file

@ -54,7 +54,7 @@
*/
#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
#define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000)
#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
@ -83,8 +83,8 @@
#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
#define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000)
#define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000)
#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)

3
arch/arm/include/asm/arch-omap3/am35x_def.h
View file

@ -32,6 +32,9 @@
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
/* IP_SW_RESET bits */
#define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */
/* General register mappings of system control module */
#define AM35X_SCM_GEN_BASE 0x48002270
struct am35x_scm_general {

56
arch/arm/include/asm/arch-omap3/emac_defs.h Normal file
View file

@ -0,0 +1,56 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Based on:
*
* ----------------------------------------------------------------------------
*
* dm644x_emac.h
*
* TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
*
* Copyright (C) 2005 Texas Instruments.
*
* ----------------------------------------------------------------------------
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
* ----------------------------------------------------------------------------
* Modifications:
* ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
*
*/
#ifndef _AM3517_EMAC_H_
#define _AM3517_EMAC_H_
#define EMAC_BASE_ADDR 0x5C010000
#define EMAC_WRAPPER_BASE_ADDR 0x5C000000
#define EMAC_WRAPPER_RAM_ADDR 0x5C020000
#define EMAC_MDIO_BASE_ADDR 0x5C030000
#define EMAC_HW_RAM_ADDR 0x01E20000
#define EMAC_MDIO_BUS_FREQ 166000000 /* 166 MHZ check */
#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 2.0 MHz */
/* SOFTRESET macro definition interferes with emac_regs structure definition */
#undef SOFTRESET
typedef volatile unsigned int dv_reg;
typedef volatile unsigned int *dv_reg_p;
#define DAVINCI_EMAC_VERSION2
#endif /* _AM3517_EMAC_H_ */

152
arch/arm/include/asm/arch-omap3/mem.h
View file

@ -39,10 +39,26 @@ enum {
#define EARLY_INIT 1
/*
* For a full explanation of these registers and values please see
* the Technical Reference Manual (TRM) for any of the processors in
* this family.
*/
/* Slower full frequency range default timings for x32 operation*/
#define SDRC_SHARING 0x00000100
#define SDRC_MR_0_SDR 0x00000031
/*
* SDRC autorefresh control values. This register consists of autorefresh
* enable at bits 0:1 and an autorefresh counter value in bits 8:23. The
* counter is a result of ( tREFI / tCK ) - 50.
*/
#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01
#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
#define DLL_OFFSET 0
#define DLL_WRITEDDRCLKX2DIS 1
#define DLL_ENADLL 1
@ -86,6 +102,53 @@ enum {
ACTIM_CTRLB_TXP(b) | \
ACTIM_CTRLB_TXSR(d)
/*
* Values used in the MCFG register. Only values we use today
* are defined and the rest can be found in the TRM. Unless otherwise
* noted all fields are one bit.
*/
#define V_MCFG_RAMTYPE_DDR (0x1)
#define V_MCFG_DEEPPD_EN (0x1 << 3)
#define V_MCFG_B32NOT16_32 (0x1 << 4)
#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */
#define V_MCFG_RAMSIZE(a) ((((a)/(1024*1024))/2) << 8) /* 8:17 */
#define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19)
#define V_MCFG_CASWIDTH_10B (0x5 << 20) /* 20:22 */
#define V_MCFG_RASWIDTH(a) ((a) << 24) /* 24:26 */
/* Macro to construct MCFG */
#define MCFG(a, b) \
V_MCFG_RASWIDTH(b) | V_MCFG_CASWIDTH_10B | \
V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(a) | \
V_MCFG_BANKALLOCATION_RBC | \
V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
/* Hynix part of AM/DM37xEVM (200MHz optimized) */
#define HYNIX_TDAL_200 6
#define HYNIX_TDPL_200 3
#define HYNIX_TRRD_200 2
#define HYNIX_TRCD_200 4
#define HYNIX_TRP_200 3
#define HYNIX_TRAS_200 8
#define HYNIX_TRC_200 11
#define HYNIX_TRFC_200 18
#define HYNIX_V_ACTIMA_200 \
ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \
HYNIX_TRAS_200, HYNIX_TRP_200, \
HYNIX_TRCD_200, HYNIX_TRRD_200, \
HYNIX_TDPL_200, HYNIX_TDAL_200)
#define HYNIX_TWTR_200 2
#define HYNIX_TCKE_200 1
#define HYNIX_TXP_200 1
#define HYNIX_XSR_200 28
#define HYNIX_V_ACTIMB_200 \
ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \
HYNIX_TXP_200, HYNIX_XSR_200)
#define HYNIX_RASWIDTH_200 0x3
#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200)
/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
#define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
/* 15/6 + 18/6 = 5.5 -> 6 */
@ -138,32 +201,42 @@ enum {
ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \
MICRON_TXP_165, MICRON_XSR_165)
#define MICRON_RAMTYPE 0x1
#define MICRON_DDRTYPE 0x0
#define MICRON_DEEPPD 0x1
#define MICRON_B32NOT16 0x1
#define MICRON_BANKALLOCATION 0x2
#define MICRON_RAMSIZE ((PHYS_SDRAM_1_SIZE/(1024*1024))/2)
#define MICRON_ADDRMUXLEGACY 0x1
#define MICRON_CASWIDTH 0x5
#define MICRON_RASWIDTH 0x2
#define MICRON_LOCKSTATUS 0x0
#define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \
(MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \
(MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \
(MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \
(MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE))
#define MICRON_RASWIDTH_165 0x2
#define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165)
#define MICRON_ARCV 2030
#define MICRON_ARE 0x1
#define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE))
#define MICRON_BL_165 0x2
#define MICRON_SIL_165 0x0
#define MICRON_CASL_165 0x3
#define MICRON_WBST_165 0x0
#define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \
(MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
(MICRON_BL_165))
#define MICRON_BL 0x2
#define MICRON_SIL 0x0
#define MICRON_CASL 0x3
#define MICRON_WBST 0x0
#define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \
(MICRON_SIL << 3) | (MICRON_BL))
/* Micron part (200MHz optimized) 5 ns */
#define MICRON_TDAL_200 6
#define MICRON_TDPL_200 3
#define MICRON_TRRD_200 2
#define MICRON_TRCD_200 3
#define MICRON_TRP_200 3
#define MICRON_TRAS_200 8
#define MICRON_TRC_200 11
#define MICRON_TRFC_200 15
#define MICRON_V_ACTIMA_200 \
ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \
MICRON_TRAS_200, MICRON_TRP_200, \
MICRON_TRCD_200, MICRON_TRRD_200, \
MICRON_TDPL_200, MICRON_TDAL_200)
#define MICRON_TWTR_200 2
#define MICRON_TCKE_200 4
#define MICRON_TXP_200 2
#define MICRON_XSR_200 23
#define MICRON_V_ACTIMB_200 \
ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \
MICRON_TXP_200, MICRON_XSR_200)
#define MICRON_RASWIDTH_200 0x3
#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200)
/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
@ -191,31 +264,8 @@ enum {
ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
NUMONYX_TXP_165, NUMONYX_XSR_165)
#ifdef CONFIG_OMAP3_INFINEON_DDR
#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
#endif
#ifdef CONFIG_OMAP3_MICRON_DDR
#define V_ACTIMA_165 MICRON_V_ACTIMA_165
#define V_ACTIMB_165 MICRON_V_ACTIMB_165
#define V_MCFG MICRON_V_MCFG
#define V_RFR_CTRL MICRON_V_RFR_CTRL
#define V_MR MICRON_V_MR
#endif
#ifdef CONFIG_OMAP3_NUMONYX_DDR
#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
#endif
#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
#error "Please choose the right DDR type in config header"
#endif
#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL))
#error "Please choose the right DDR type in config header"
#endif
#define NUMONYX_RASWIDTH_165 0x4
#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165)
/*
* GPMC settings -
@ -259,6 +309,10 @@ enum {
#define GPMC_SIZE_32M 0xE
#define GPMC_SIZE_16M 0xF
#define GPMC_BASEADDR_MASK 0x3F
#define GPMC_CS_ENABLE 0x1
#define SMNAND_GPMC_CONFIG1 0x00000800
#define SMNAND_GPMC_CONFIG2 0x00141400
#define SMNAND_GPMC_CONFIG3 0x00141400

41
arch/arm/include/asm/arch-omap3/mux.h
View file

@ -404,6 +404,47 @@
#define CONTROL_PADCONF_SDRC_CKE0 0x0262
#define CONTROL_PADCONF_SDRC_CKE1 0x0264
/* AM3517 specific mux configuration */
#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08
/* CCDC */
#define CONTROL_PADCONF_CCDC_PCLK 0x01E4
#define CONTROL_PADCONF_CCDC_FIELD 0x01E6
#define CONTROL_PADCONF_CCDC_HD 0x01E8
#define CONTROL_PADCONF_CCDC_VD 0x01EA
#define CONTROL_PADCONF_CCDC_WEN 0x01EC
#define CONTROL_PADCONF_CCDC_DATA0 0x01EE
#define CONTROL_PADCONF_CCDC_DATA1 0x01F0
#define CONTROL_PADCONF_CCDC_DATA2 0x01F2
#define CONTROL_PADCONF_CCDC_DATA3 0x01F4
#define CONTROL_PADCONF_CCDC_DATA4 0x01F6
#define CONTROL_PADCONF_CCDC_DATA5 0x01F8
#define CONTROL_PADCONF_CCDC_DATA6 0x01FA
#define CONTROL_PADCONF_CCDC_DATA7 0x01FC
/* RMII */
#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE
#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200
#define CONTROL_PADCONF_RMII_RXD0 0x0202
#define CONTROL_PADCONF_RMII_RXD1 0x0204
#define CONTROL_PADCONF_RMII_CRS_DV 0x0206
#define CONTROL_PADCONF_RMII_RXER 0x0208
#define CONTROL_PADCONF_RMII_TXD0 0x020A
#define CONTROL_PADCONF_RMII_TXD1 0x020C
#define CONTROL_PADCONF_RMII_TXEN 0x020E
#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210
#define CONTROL_PADCONF_USB0_DRVBUS 0x0212
/* CAN */
#define CONTROL_PADCONF_HECC1_TXD 0x0214
#define CONTROL_PADCONF_HECC1_RXD 0x0216
#define CONTROL_PADCONF_SYS_BOOT7 0x0218
#define CONTROL_PADCONF_SDRC_DQS0N 0x021A
#define CONTROL_PADCONF_SDRC_DQS1N 0x021C
#define CONTROL_PADCONF_SDRC_DQS2N 0x021E
#define CONTROL_PADCONF_SDRC_DQS3N 0x0220
#define CONTROL_PADCONF_STRBEN_DLY0 0x0222
#define CONTROL_PADCONF_STRBEN_DLY1 0x0224
#define CONTROL_PADCONF_SYS_BOOT8 0x0226
#define MUX_VAL(OFFSET,VALUE)\
writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));

1
arch/arm/include/asm/arch-omap3/omap3.h
View file

@ -153,6 +153,7 @@ struct gpio {
#define SRAM_OFFSET2 0x0000F800
#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \
SRAM_OFFSET2)
#define SRAM_CLK_CODE (SRAM_VECT_CODE + 64)
#define OMAP3_PUBLIC_SRAM_BASE 0x40208000 /* Works for GP & EMU */
#define OMAP3_PUBLIC_SRAM_END 0x40210000

4
arch/arm/include/asm/arch-omap3/sys_proto.h
View file

@ -38,6 +38,9 @@ void per_clocks_enable(void);
void memif_init(void);
void sdrc_init(void);
void do_sdrc_init(u32, u32);
void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr);
void identify_nand_chip(int *mfr, int *id);
void emif4_init(void);
void gpmc_init(void);
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
@ -49,7 +52,6 @@ void set_muxconf_regs(void);
u32 get_cpu_family(void);
u32 get_cpu_rev(void);
u32 get_sku_id(void);
u32 get_mem_type(void);
u32 get_sysboot_value(void);
u32 is_gpmc_muxed(void);
u32 get_gpmc0_type(void);

2
arch/arm/include/asm/arch-omap4/omap.h
View file

@ -63,6 +63,8 @@
#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F
#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
/* UART */
#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)

16
arch/arm/include/asm/arch-omap5/clocks.h
View file

@ -686,14 +686,14 @@ struct dpll_regs {
struct dpll_params {
u32 m;
u32 n;
u8 m2;
u8 m3;
u8 h11;
u8 h12;
u8 h13;
u8 h14;
u8 h22;
u8 h23;
s8 m2;
s8 m3;
s8 h11;
s8 h12;
s8 h13;
s8 h14;
s8 h22;
s8 h23;
};
extern struct omap5_prcm_regs *const prcm;

48
arch/arm/include/asm/arch-pxa/pxa-regs.h
View file

@ -109,7 +109,7 @@ typedef void (*ExcpHndlr) (void) ;
#define DCSR13 0x40000034 /* DMA Control / Status Register for Channel 13 */
#define DCSR14 0x40000038 /* DMA Control / Status Register for Channel 14 */
#define DCSR15 0x4000003c /* DMA Control / Status Register for Channel 15 */
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define DCSR16 0x40000040 /* DMA Control / Status Register for Channel 16 */
#define DCSR17 0x40000044 /* DMA Control / Status Register for Channel 17 */
#define DCSR18 0x40000048 /* DMA Control / Status Register for Channel 18 */
@ -126,7 +126,7 @@ typedef void (*ExcpHndlr) (void) ;
#define DCSR29 0x40000074 /* DMA Control / Status Register for Channel 29 */
#define DCSR30 0x40000078 /* DMA Control / Status Register for Channel 30 */
#define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */
#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
#define DCSR(x) (0x40000000 | ((x) << 2))
@ -134,7 +134,7 @@ typedef void (*ExcpHndlr) (void) ;
#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
#if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS)
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
@ -438,7 +438,7 @@ typedef void (*ExcpHndlr) (void) ;
/*
* USB Device Controller
*/
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define UDCCR 0x40600000 /* UDC Control Register */
#define UDCCR_UDE (1 << 0) /* UDC enable */
@ -797,9 +797,9 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
#define UDC_BCR_MASK (0x3ff)
#endif /* CONFIG_PXA27X */
#endif /* CONFIG_CPU_PXA27X */
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
/******************************************************************************/
/*
@ -870,7 +870,7 @@ typedef void (*ExcpHndlr) (void) ;
#define UP2OCR_CPVPE (1<<1)
#define UP2OCR_CPVEN (1<<0)
#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
/******************************************************************************/
/*
@ -923,7 +923,7 @@ typedef void (*ExcpHndlr) (void) ;
#define OWER 0x40A00018 /* OS Timer Watchdog Enable Register */
#define OIER 0x40A0001C /* OS Timer Interrupt Enable Register */
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define OSCR4 0x40A00040 /* OS Timer Counter Register 4 */
#define OSCR5 0x40A00044 /* OS Timer Counter Register 5 */
#define OSCR6 0x40A00048 /* OS Timer Counter Register 6 */
@ -951,7 +951,7 @@ typedef void (*ExcpHndlr) (void) ;
#define OMCR10 0x40A000D8 /* OS Match Control Register 10 */
#define OMCR11 0x40A000DC /* OS Match Control Register 11 */
#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
#define OSSR_M4 (1 << 4) /* Match status channel 4 */
#define OSSR_M3 (1 << 3) /* Match status channel 3 */
@ -1052,7 +1052,7 @@ typedef void (*ExcpHndlr) (void) ;
#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
#if !defined(CONFIG_PXA27X)
#if !defined(CONFIG_CPU_PXA27X)
#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
#endif
#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
@ -1071,7 +1071,7 @@ typedef void (*ExcpHndlr) (void) ;
#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
#if defined(CONFIG_PXA27X)
#if defined(CONFIG_CPU_PXA27X)
#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */
#endif
@ -1087,7 +1087,7 @@ typedef void (*ExcpHndlr) (void) ;
#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
#if !defined(CONFIG_PXA27X)
#if !defined(CONFIG_CPU_PXA27X)
#define CCCR_L09 (0x1F)
#define CCCR_L27 (0x1)
#define CCCR_L32 (0x2)
@ -1120,7 +1120,7 @@ typedef void (*ExcpHndlr) (void) ;
#define PWM_PWDUTY1 0x40C00004 /* PWM 1 Duty Cycle Register */
#define PWM_PERVAL1 0x40C00008 /* PWM 1 Period Control Register */
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define PWM_CTRL2 0x40B00010 /* PWM 2 Control Register */
#define PWM_PWDUTY2 0x40B00014 /* PWM 2 Duty Cycle Register */
#define PWM_PERVAL2 0x40B00018 /* PWM 2 Period Control Register */
@ -1128,7 +1128,7 @@ typedef void (*ExcpHndlr) (void) ;
#define PWM_CTRL3 0x40C00010 /* PWM 3 Control Register */
#define PWM_PWDUTY3 0x40C00014 /* PWM 3 Duty Cycle Register */
#define PWM_PERVAL3 0x40C00018 /* PWM 3 Period Control Register */
#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
/*
* Interrupt Controller
@ -1140,14 +1140,14 @@ typedef void (*ExcpHndlr) (void) ;
#define ICPR 0x40D00010 /* Interrupt Controller Pending Register */
#define ICCR 0x40D00014 /* Interrupt Controller Control Register */
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define ICHP 0x40D00018 /* Interrupt Controller Highest Priority Register */
#define ICIP2 0x40D0009C /* Interrupt Controller IRQ Pending Register 2 */
#define ICMR2 0x40D000A0 /* Interrupt Controller Mask Register 2 */
#define ICLR2 0x40D000A4 /* Interrupt Controller Level Register 2 */
#define ICFP2 0x40D000A8 /* Interrupt Controller FIQ Pending Register 2 */
#define ICPR2 0x40D000AC /* Interrupt Controller Pending Register 2 */
#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
/******************************************************************************/
/*
@ -1188,7 +1188,7 @@ typedef void (*ExcpHndlr) (void) ;
#define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */
#define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */
#define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */
#define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */
@ -1198,7 +1198,7 @@ typedef void (*ExcpHndlr) (void) ;
#define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */
#define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */
#define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */
#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
#ifdef CONFIG_CPU_MONAHANS
#define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */
@ -1244,7 +1244,7 @@ typedef void (*ExcpHndlr) (void) ;
#define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3))
#define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2))
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3))
#define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3))
#define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3))
@ -2123,7 +2123,7 @@ typedef void (*ExcpHndlr) (void) ;
#define LCCR0_PDD_S 12
#define LCCR0_BM (1 << 20) /* Branch mask */
#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
#if defined(CONFIG_PXA27X)
#if defined(CONFIG_CPU_PXA27X)
#define LCCR0_LCDT (1 << 22) /* LCD Panel Type */
#define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */
#define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */
@ -2249,7 +2249,7 @@ typedef void (*ExcpHndlr) (void) ;
#define LCSR1_IU6 (1 << 29)
#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
#if defined(CONFIG_PXA27X)
#if defined(CONFIG_CPU_PXA27X)
#define LDCMD_SOFINT (1 << 22)
#define LDCMD_EOFINT (1 << 21)
#endif
@ -2480,7 +2480,7 @@ typedef void (*ExcpHndlr) (void) ;
#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
#if defined(CONFIG_PXA27X)
#if defined(CONFIG_CPU_PXA27X)
#define ARB_CNTRL 0x48000048 /* Arbiter Control Register */
@ -2494,7 +2494,7 @@ typedef void (*ExcpHndlr) (void) ;
#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
#endif /* CONFIG_PXA27X */
#endif /* CONFIG_CPU_PXA27X */
/* LCD registers */
#define LCCR4 0x44000010 /* LCD Controller Control Register 4 */
@ -2628,6 +2628,6 @@ typedef void (*ExcpHndlr) (void) ;
#define OSCR4 0x40A00040 /* OS Timer Counter Register */
#define OMCR4 0x40A000C0 /* */
#endif /* CONFIG_PXA27X */
#endif /* CONFIG_CPU_PXA27X */
#endif /* _PXA_REGS_H_ */

40
onenand_ipl/board/vpac270/u-boot.onenand.lds → arch/arm/include/asm/arch-pxa/pxa.h
View file

@ -1,9 +1,7 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* PXA common functions
*
* See file CREDITS for list of people who contributed to this
* project.
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -12,7 +10,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -21,31 +19,11 @@
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
#ifndef __PXA_H__
#define __PXA_H__
. = ALIGN(4);
.text :
{
start.o (.text)
*(.text)
}
int cpu_is_pxa25x(void);
int cpu_is_pxa27x(void);
void pxa2xx_dram_init(void);
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) . = ALIGN(4); }
__bss_end__ = .;
}
#endif /* __PXA_H__ */

5
arch/arm/include/asm/omap_common.h
View file

@ -94,6 +94,10 @@ void spl_nand_load_image(void);
/* MMC SPL functions */
void spl_mmc_load_image(void);
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void);
#endif
/*
* silicon revisions.
* Moving this to common, so that most of code can be moved to common,
@ -108,6 +112,7 @@ void spl_mmc_load_image(void);
#define OMAP4430_ES2_2 0x44300220
#define OMAP4430_ES2_3 0x44300230
#define OMAP4460_ES1_0 0x44600100
#define OMAP4460_ES1_1 0x44600110
/* omap5 */
#define OMAP5430_SILICON_ID_INVALID 0

2
arch/arm/lib/eabi_compat.c
View file

@ -13,7 +13,9 @@
int raise (int signum)
{
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
printf("raise: Signal # %d caught\n", signum);
#endif
return 0;
}

4
board/CarMediaLab/flea3/flea3.c
View file

@ -160,7 +160,7 @@ static void board_setup_sdram(void)
writel(0x2000, &esdc->esdctl0);
writel(0x2000, &esdc->esdctl1);
board_setup_sdram_bank(CSD1_BASE_ADDR);
board_setup_sdram_bank(CSD0_BASE_ADDR);
}
static void setup_iomux_uart3(void)
@ -229,7 +229,7 @@ int board_early_init_f(void)
(struct ccm_regs *)IMX_CCM_BASE;
/* setup GPIO3_1 to set HighVCore signal */
mxc_request_iomux(MX35_PIN_ATA_DATA1, MUX_CONFIG_ALT5);
mxc_request_iomux(MX35_PIN_ATA_DA1, MUX_CONFIG_ALT5);
gpio_direction_output(65, 1);
/* initialize PLL and clock configuration */

87
board/LaCie/common/common.c Normal file
View file

@ -0,0 +1,87 @@
/*
* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#include <common.h>
#include <i2c.h>
#include <miiphy.h>
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
#define MV88E1116_LED_FCTRL_REG 10
#define MV88E1116_CPRSP_CR3_REG 21
#define MV88E1116_MAC_CTRL_REG 21
#define MV88E1116_PGADR_REG 22
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
void mv_phy_88e1116_init(const char *name)
{
u16 reg;
u16 devadr;
if (miiphy_set_current_dev(name))
return;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
printf("Err..(%s) could not read PHY dev address\n", __func__);
return;
}
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
miiphy_reset(name, devadr);
printf("88E1116 Initialized on %s\n", name);
}
#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
int lacie_read_mac_address(uchar *mac_addr)
{
int ret;
ushort version;
/* I2C-0 for on-board EEPROM */
i2c_set_bus_num(0);
/* Check layout version for EEPROM data */
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(uchar *) &version, 2);
if (ret != 0) {
printf("Error: failed to read I2C EEPROM @%02x\n",
CONFIG_SYS_I2C_EEPROM_ADDR);
return ret;
}
version = be16_to_cpu(version);
if (version < 1 || version > 3) {
printf("Error: unknown version %d for EEPROM data\n",
version);
return -1;
}
/* Read Ethernet MAC address from EEPROM */
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac_addr, 6);
if (ret != 0)
printf("Error: failed to read I2C EEPROM @%02x\n",
CONFIG_SYS_I2C_EEPROM_ADDR);
return ret;
}
#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */

20
board/LaCie/common/common.h Normal file
View file

@ -0,0 +1,20 @@
/*
* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#ifndef _LACIE_COMMON_H
#define _LACIE_COMMON_H
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
void mv_phy_88e1116_init(const char *name);
#endif
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
int lacie_read_mac_address(uchar *mac);
#endif
#endif /* _LACIE_COMMON_H */

5
board/LaCie/edminiv2/Makefile
View file

@ -26,10 +26,13 @@
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
endif
LIB = $(obj)lib$(BOARD).o
COBJS := edminiv2.o
COBJS := edminiv2.o ../common/common.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

30
board/LaCie/edminiv2/edminiv2.c
View file

@ -27,7 +27,6 @@
#include <common.h>
#include <miiphy.h>
#include <asm/arch/orion5x.h>
#include "edminiv2.h"
DECLARE_GLOBAL_DATA_PTR;
@ -96,33 +95,6 @@ int board_init(void)
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
{
u16 reg;
u16 devadr;
char *name = "egiga0";
if (miiphy_set_current_dev(name))
return;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
printf("Err..%s could not read PHY dev address\n",
__func__);
return;
}
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
miiphy_reset(name, devadr);
printf("88E1116 Initialized on %s\n", name);
mv_phy_88e1116_init("egiga0");
}
#endif /* CONFIG_RESET_PHY_R */

34
board/pleb2/Makefile → board/LaCie/net2big_v2/Makefile
View file

@ -1,7 +1,10 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
#
# Based on Kirkwood support:
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
@ -13,26 +16,31 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
endif
LIB = $(obj)lib$(BOARD).o
COBJS := pleb2.o flash.o
COBJS := $(BOARD).o ../common/common.o
SRCS := $(COBJS:.o=.c)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################

162
board/LaCie/net2big_v2/kwbimage.cfg Normal file
View file

@ -0,0 +1,162 @@
#
# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
#
# Based on Kirkwood support:
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# Refer docs/README.kwimage for more details about how-to configure
# and create kirkwood boot image
#
# Boot Media configurations
BOOT_FROM spi # Boot from SPI flash
# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xFFD100e0 0x1B1B1B9B
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xFFD01400 0x43000C30 # DDR Configuration register
# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
# bit23-14: zero
# bit24: 1= enable exit self refresh mode on DDR access
# bit25: 1 required
# bit29-26: zero
# bit31-30: 01
DATA 0xFFD01404 0x38743000 # DDR Controller Control Low
# bit 4: 0=addr/cmd in smame cycle
# bit 5: 0=clk is driven during self refresh, we don't care for APX
# bit 6: 0=use recommended falling edge of clk for addr/cmd
# bit14: 0=input buffer always powered up
# bit18: 1=cpu lock transaction enabled
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 3 required
# bit31: 0=no additional STARTBURST delay
DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
# bit7-4: TRCD
# bit11- 8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20: TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP
DATA 0xFFD0140C 0x00000A32 # DDR Timing (High)
# bit6-0: TRFC
# bit8-7: TR2R
# bit10-9: TR2W
# bit12-11: TW2W
# bit31-13: zero required
DATA 0xFFD01410 0x0000CCCC # DDR Address Control
# bit1-0: 01, Cs0width=x16
# bit3-2: 11, Cs0size=1Gb
# bit5-4: 00, Cs2width=nonexistent
# bit7-6: 00, Cs1size =nonexistent
# bit9-8: 00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
# bit15-14: 00, Cs3size =nonexistent
# bit16: 0, Cs0AddrSel
# bit17: 0, Cs1AddrSel
# bit18: 0, Cs2AddrSel
# bit19: 0, Cs3AddrSel
# bit31-20: 0 required
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
# bit0: 0, OpenPage enabled
# bit31-1: 0 required
DATA 0xFFD01418 0x00000000 # DDR Operation
# bit3-0: 0x0, DDR cmd
# bit31-4: 0 required
DATA 0xFFD0141C 0x00000662 # DDR Mode
# bit2-0: 2, BurstLen=2 required
# bit3: 0, BurstType=0 required
# bit6-4: 4, CL=5
# bit7: 0, TestMode=0 normal
# bit8: 0, DLL reset=0 normal
# bit11-9: 6, auto-precharge write recovery ????????????
# bit12: 0, PD must be zero
# bit31-13: 0 required
DATA 0xFFD01420 0x00000044 # DDR Extended Mode
# bit0: 0, DDR DLL enabled
# bit1: 1, DDR drive strenght reduced
# bit2: 1, DDR ODT control lsd enabled
# bit5-3: 000, required
# bit6: 1, DDR ODT control msb, enabled
# bit9-7: 000, required
# bit10: 0, differential DQS enabled
# bit11: 0, required
# bit12: 0, DDR output buffer enabled
# bit31-13: 0 required
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
# bit2-0: 111, required
# bit3 : 1 , MBUS Burst Chop disabled
# bit6-4: 111, required
# bit7 : 1 , D2P Latency enabled
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
# bit9 : 0 , no half clock cycle addition to dataout
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
# bit15-12: 1111 required
# bit31-16: 0 required
DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
# bit0: 1, Window enabled
# bit1: 0, Write Protect disabled
# bit3-2: 00, CS0 hit selected
# bit23-4: ones, required
# bit31-24: 0x07, Size (i.e. 128MB)
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
# bit3-2: 01, ODT1 active NEVER!
# bit31-4: zero, required
DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
# bit11-10:1, DQ_ODTSel. ODT select turned on
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
#bit0=1, enable DDR init upon this register write
# End of Header extension
DATA 0x0 0x0

126
board/LaCie/net2big_v2/net2big_v2.c Normal file
View file

@ -0,0 +1,126 @@
/*
* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
*
* Based on Kirkwood support:
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <command.h>
#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
#include <asm/arch/gpio.h>
#include "net2big_v2.h"
#include "../common/common.h"
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/* GPIO configuration */
kw_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
u32 kwmpp_config[] = {
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
MPP3_SPI_MISO,
MPP6_SYSRST_OUTn,
MPP7_GPO, /* Request power-off */
MPP8_TW_SDA,
MPP9_TW_SCK,
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP13_GPIO, /* Rear power switch (on|auto) */
MPP14_GPIO, /* USB fuse alarm */
MPP15_GPIO, /* Rear power switch (auto|off) */
MPP16_GPIO, /* SATA HDD1 power */
MPP17_GPIO, /* SATA HDD2 power */
MPP20_SATA1_ACTn,
MPP21_SATA0_ACTn,
MPP24_GPIO, /* USB mode select */
MPP26_GPIO, /* USB device vbus */
MPP28_GPIO, /* USB enable host vbus */
MPP29_GPIO, /* GPIO extension ALE */
MPP34_GPIO, /* Rear Push button 0=on 1=off */
MPP35_GPIO, /* Inhibit switch power-off */
MPP36_GPIO, /* SATA HDD1 presence */
MPP37_GPIO, /* SATA HDD2 presence */
MPP40_GPIO, /* eSATA presence */
MPP44_GPIO, /* GPIO extension (data 0) */
MPP45_GPIO, /* GPIO extension (data 1) */
MPP46_GPIO, /* GPIO extension (data 2) */
MPP47_GPIO, /* GPIO extension (addr 0) */
MPP48_GPIO, /* GPIO extension (addr 1) */
MPP49_GPIO, /* GPIO extension (addr 2) */
0
};
kirkwood_mpp_conf(kwmpp_config);
return 0;
}
int board_init(void)
{
/* Machine number */
gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2;
/* Boot parameters address */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
return 0;
}
#if defined(CONFIG_MISC_INIT_R)
int misc_init_r(void)
{
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
if (!getenv("ethaddr")) {
uchar mac[6];
if (lacie_read_mac_address(mac) == 0)
eth_setenv_enetaddr("ethaddr", mac);
}
#endif
return 0;
}
#endif
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
/* Configure and initialize PHY */
void reset_phy(void)
{
mv_phy_88e1116_init("egiga0");
}
#endif
#if defined(CONFIG_KIRKWOOD_GPIO)
/* Return GPIO push button status */
static int
do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON);
}
U_BOOT_CMD(button, 1, 1, do_read_push_button,
"Return GPIO push button status 0=off 1=on", "");
#endif

32
board/LaCie/edminiv2/edminiv2.h → board/LaCie/net2big_v2/net2big_v2.h
View file

@ -1,9 +1,7 @@
/*
* (C) Copyright 2009
* Net Insight <www.netinsight.net>
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
*
* Based on sheevaplug.h:
* Based on Kirkwood support:
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
@ -20,22 +18,18 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __EDMINIV2_BASE_H
#define __EDMINIV2_BASE_H
#ifndef NET2BIG_V2_H
#define NET2BIG_V2_H
/* PHY related */
#define MV88E1116_LED_FCTRL_REG 10
#define MV88E1116_CPRSP_CR3_REG 21
#define MV88E1116_MAC_CTRL_REG 21
#define MV88E1116_PGADR_REG 22
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
/* GPIO configuration */
#define NET2BIG_V2_OE_LOW 0x0600E000
#define NET2BIG_V2_OE_HIGH 0x00000134
#define NET2BIG_V2_OE_VAL_LOW 0x10030000
#define NET2BIG_V2_OE_VAL_HIGH 0x00000000
#endif /* __EDMINIV2_BASE_H */
/* Buttons */
#define NET2BIG_V2_GPIO_PUSH_BUTTON 34
#endif /* NET2BIG_V2_H */

5
board/LaCie/netspace_v2/Makefile
View file

@ -21,10 +21,13 @@
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
endif
LIB = $(obj)lib$(BOARD).o
COBJS := netspace_v2.o
COBJS := $(BOARD).o ../common/common.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

51
board/LaCie/netspace_v2/netspace_v2.c
View file

@ -21,14 +21,14 @@
*/
#include <common.h>
#include <miiphy.h>
#include <netdev.h>
#include <command.h>
#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
#include <asm/arch/gpio.h>
#include "netspace_v2.h"
#include "../common/common.h"
DECLARE_GLOBAL_DATA_PTR;
@ -89,49 +89,29 @@ int board_init(void)
return 0;
}
void mv_phy_88e1116_init(char *name)
#if defined(CONFIG_MISC_INIT_R)
int misc_init_r(void)
{
u16 reg;
u16 devadr;
if (miiphy_set_current_dev(name))
return;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
printf("Err..(%s) could not read PHY dev address\n", __func__);
return;
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
if (!getenv("ethaddr")) {
uchar mac[6];
if (lacie_read_mac_address(mac) == 0)
eth_setenv_enetaddr("ethaddr", mac);
}
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
if (miiphy_read(name, devadr, MII_BMCR, &reg) != 0) {
printf("Err..(%s) PHY status read failed\n", __func__);
return;
}
if (miiphy_write(name, devadr, MII_BMCR, reg | 0x8000) != 0) {
printf("Err..(%s) PHY reset failed\n", __func__);
return;
}
debug("88E1116 Initialized on %s\n", name);
#endif
return 0;
}
#endif
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
/* Configure and initialize PHY */
void reset_phy(void)
{
mv_phy_88e1116_init("egiga0");
}
#endif
#if defined(CONFIG_KIRKWOOD_GPIO)
/* Return GPIO button status */
static int
do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@ -141,3 +121,4 @@ do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
U_BOOT_CMD(button, 1, 1, do_read_button,
"Return GPIO button status 0=off 1=on", "");
#endif

8
board/LaCie/netspace_v2/netspace_v2.h
View file

@ -31,12 +31,4 @@
#define NETSPACE_V2_GPIO_BUTTON 32
/* PHY related */
#define MV88E1116_LED_FCTRL_REG 10
#define MV88E1116_CPRSP_CR3_REG 21
#define MV88E1116_MAC_CTRL_REG 21
#define MV88E1116_PGADR_REG 22
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
#endif /* NETSPACE_V2_H */

15
board/ait/cam_enc_4xx/cam_enc_4xx.c
View file

@ -36,21 +36,6 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPL_BUILD
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
}
static struct davinci_timer *timer =
(struct davinci_timer *)DAVINCI_TIMER3_BASE;

4
board/balloon3/balloon3.c
View file

@ -21,6 +21,7 @@
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pxa.h>
#include <serial.h>
#include <asm/io.h>
#include <spartan3.h>
@ -57,10 +58,9 @@ struct serial_device *default_serial_console(void)
return &serial_stuart_device;
}
extern void pxa_dram_init(void);
int dram_init(void)
{
pxa_dram_init();
pxa2xx_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}

43
board/cerf250/Makefile
View file

@ -1,43 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := cerf250.o flash.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

85
board/cerf250/cerf250.c
View file

@ -1,85 +0,0 @@
/*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
int board_init (void)
{
/* We have RAM, disable cache */
dcache_disable();
icache_disable();
/* arch number of cerf PXA Board */
gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0xa0000100;
return 0;
}
int board_late_init(void)
{
setenv("stdout", "serial");
setenv("stderr", "serial");
return 0;
}
extern void pxa_dram_init(void);
int dram_init(void)
{
pxa_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
return rc;
}
#endif

429
board/cerf250/flash.c
View file

@ -1,429 +0,0 @@
/*
* (C) Copyright 2001
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/byteorder/swab.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Board support for 1 or 2 flash devices */
#define FLASH_PORT_WIDTH32
#undef FLASH_PORT_WIDTH16
#ifdef FLASH_PORT_WIDTH16
#define FLASH_PORT_WIDTH ushort
#define FLASH_PORT_WIDTHV vu_short
#define SWAP(x) __swab16(x)
#else
#define FLASH_PORT_WIDTH ulong
#define FLASH_PORT_WIDTHV vu_long
#define SWAP(x) __swab32(x)
#endif
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define mb() __asm__ __volatile__ ("" : : : "memory")
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (FPW *addr, flash_info_t *info);
static int write_data (flash_info_t *info, ulong dest, FPW data);
static void flash_get_offsets (ulong base, flash_info_t *info);
void inline spin_wheel (void);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
int i;
ulong size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
break;
case 1:
flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
break;
default:
panic ("configured too many flash banks!\n");
break;
}
size += flash_info[i].size;
}
/* Protect monitor and environment sectors
*/
flash_protect ( FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
&flash_info[0] );
flash_protect ( FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
return size;
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
return;
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
info->protect[i] = 0;
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL:
printf ("INTEL ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F128J3A:
printf ("28F128J3A\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (FPW *addr, flash_info_t *info)
{
volatile FPW value;
/* Write auto select command: read Manufacturer ID */
addr[0x5555] = (FPW) 0x00AA00AA;
addr[0x2AAA] = (FPW) 0x00550055;
addr[0x5555] = (FPW) 0x00900090;
mb ();
value = addr[0];
switch (value) {
case (FPW) INTEL_MANUFACT:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
return (0); /* no or unknown flash */
}
mb ();
value = addr[1]; /* device ID */
switch (value) {
case (FPW) INTEL_ID_28F128J3A:
info->flash_id += FLASH_28F128J3A;
info->sector_count = 128;
info->size = 0x02000000;
break; /* => 16 MB */
default:
info->flash_id = FLASH_UNKNOWN;
break;
}
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
type = (info->flash_id & FLASH_VENDMASK);
if ((type != FLASH_MAN_INTEL)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
FPWV *addr = (FPWV *) (info->start[sect]);
FPW status;
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
rcode = 1;
break;
}
}
*addr = 0x00500050; /* clear status register cmd. */
*addr = 0x00FF00FF; /* resest to read mode */
printf (" done\n");
}
}
return rcode;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
* 4 - Flash not identified
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp;
FPW data;
int count, i, l, rc, port_width;
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
}
/* get lower word aligned address */
#ifdef FLASH_PORT_WIDTH16
wp = (addr & ~1);
port_width = 2;
#else
wp = (addr & ~3);
port_width = 4;
#endif
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < port_width && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
return (rc);
}
wp += port_width;
}
/*
* handle word aligned part
*/
count = 0;
while (cnt >= port_width) {
data = 0;
for (i = 0; i < port_width; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
return (rc);
}
wp += port_width;
cnt -= port_width;
if (count++ > 0x800) {
spin_wheel ();
count = 0;
}
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i < port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_data (info, wp, SWAP (data)));
}
/*-----------------------------------------------------------------------
* Write a word or halfword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_data (flash_info_t *info, ulong dest, FPW data)
{
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
*addr = (FPW) 0x00400040; /* write setup */
*addr = data;
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
}
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (0);
}
void inline spin_wheel (void)
{
static int p = 0;
static char w[] = "\\/-";
printf ("\010%c", w[p]);
(++p == 3) ? (p = 0) : 0;
}

236
board/cradle/cradle.c
View file

@ -1,236 +0,0 @@
/*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/arch/pxa-regs.h>
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/* local prototypes */
void set_led (int led, int color);
void error_code_halt (int code);
int init_sio (int led, unsigned long base);
inline void cradle_outb (unsigned short val, unsigned long base,
unsigned long reg);
inline unsigned char cradle_inb (unsigned long base, unsigned long reg);
inline void sleep (int i);
inline void
/**********************************************************/
sleep (int i)
/**********************************************************/
{
while (i--) {
udelay (1000000);
}
}
void
/**********************************************************/
error_code_halt (int code)
/**********************************************************/
{
while (1) {
led_code (code, RED);
sleep (1);
led_code (0, OFF);
sleep (1);
}
}
void
/**********************************************************/
led_code (int code, int color)
/**********************************************************/
{
int i;
code &= 0xf; /* only 4 leds */
for (i = 0; i < 4; i++) {
if (code & (1 << i)) {
set_led (i, color);
} else {
set_led (i, OFF);
}
}
}
void
/**********************************************************/
set_led (int led, int color)
/**********************************************************/
{
int shift = led * 2;
unsigned long mask = 0x3 << shift;
writel(mask, GPCR2); /* clear bits */
writel((color << shift), GPSR2); /* set bits */
udelay (5000);
}
inline void
/**********************************************************/
cradle_outb (unsigned short val, unsigned long base, unsigned long reg)
/**********************************************************/
{
*(volatile unsigned short *) (base + (reg * 2)) = val;
}
inline unsigned char
/**********************************************************/
cradle_inb (unsigned long base, unsigned long reg)
/**********************************************************/
{
unsigned short val;
val = *(volatile unsigned short *) (base + (reg * 2));
return (val & 0xff);
}
int
/**********************************************************/
init_sio (int led, unsigned long base)
/**********************************************************/
{
unsigned char val;
set_led (led, YELLOW);
val = cradle_inb (base, CRADLE_SIO_INDEX);
val = cradle_inb (base, CRADLE_SIO_INDEX);
if (val != 0) {
set_led (led, RED);
return -1;
}
/* map SCC2 to COM1 */
cradle_outb (0x01, base, CRADLE_SIO_INDEX);
cradle_outb (0x00, base, CRADLE_SIO_DATA);
/* enable SCC2 extended regs */
cradle_outb (0x40, base, CRADLE_SIO_INDEX);
cradle_outb (0xa0, base, CRADLE_SIO_DATA);
/* enable SCC2 clock multiplier */
cradle_outb (0x51, base, CRADLE_SIO_INDEX);
cradle_outb (0x04, base, CRADLE_SIO_DATA);
/* enable SCC2 */
cradle_outb (0x00, base, CRADLE_SIO_INDEX);
cradle_outb (0x04, base, CRADLE_SIO_DATA);
/* map SCC2 DMA to channel 0 */
cradle_outb (0x4f, base, CRADLE_SIO_INDEX);
cradle_outb (0x09, base, CRADLE_SIO_DATA);
/* read ID from SIO to check operation */
cradle_outb (0xe4, base, 0x3f8 + 0x3);
val = cradle_inb (base, 0x3f8 + 0x0);
if ((val & 0xf0) != 0x20) {
set_led (led, RED);
/* disable SCC2 */
cradle_outb (0, base, CRADLE_SIO_INDEX);
cradle_outb (0, base, CRADLE_SIO_DATA);
return -1;
}
/* set back to bank 0 */
cradle_outb (0, base, 0x3f8 + 0x3);
set_led (led, GREEN);
return 0;
}
/*
* Miscelaneous platform dependent initialisations
*/
int
/**********************************************************/
board_late_init (void)
/**********************************************************/
{
return (0);
}
int
/**********************************************************/
board_init (void)
/**********************************************************/
{
/* We have RAM, disable cache */
dcache_disable();
icache_disable();
led_code (0xf, YELLOW);
/* arch number of HHP Cradle */
gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0xa0000100;
/* Init SIOs to enable SCC2 */
udelay (100000); /* delay makes it look neat */
init_sio (0, CRADLE_SIO1_PHYS);
udelay (100000);
init_sio (1, CRADLE_SIO2_PHYS);
udelay (100000);
init_sio (2, CRADLE_SIO3_PHYS);
udelay (100000);
set_led (3, GREEN);
return 1;
}
extern void pxa_dram_init(void);
int dram_init(void)
{
pxa_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
return rc;
}
#endif

361
board/cradle/flash.c
View file

@ -1,361 +0,0 @@
/*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#define FLASH_BANK_SIZE 0x400000
#define MAIN_SECT_SIZE 0x20000
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
/*-----------------------------------------------------------------------
*/
ulong flash_init (void)
{
int i, j;
ulong size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
flash_info[i].flash_id =
(INTEL_MANUFACT & FLASH_VENDMASK) |
(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
switch (i) {
case 0:
flashbase = PHYS_FLASH_1;
break;
case 1:
flashbase = PHYS_FLASH_2;
break;
default:
panic ("configured too many flash banks!\n");
break;
}
for (j = 0; j < flash_info[i].sector_count; j++) {
flash_info[i].start[j] =
flashbase + j * MAIN_SECT_SIZE;
}
size += flash_info[i].size;
}
/* Protect monitor and environment sectors
*/
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
&flash_info[0]);
flash_protect (FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
return size;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i, j;
for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) {
switch (info->flash_id & FLASH_VENDMASK) {
case (INTEL_MANUFACT & FLASH_VENDMASK):
printf ("Intel: ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case (INTEL_ID_28F320J3A & FLASH_TYPEMASK):
printf ("28F320J3A (32Mbit)\n");
break;
case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
printf ("28F128J3 (128Mbit)\n");
break;
default:
printf ("Unknown Chip Type\n");
goto Done;
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 5) == 0) {
printf ("\n ");
}
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
info++;
}
Done: ;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
int rc = ERR_OK;
ulong start;
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
if ((s_first < 0) || (s_first > s_last)) {
return ERR_INVAL;
}
if ((info->flash_id & FLASH_VENDMASK) !=
(INTEL_MANUFACT & FLASH_VENDMASK)) {
return ERR_UNKNOWN_FLASH_VENDOR;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot)
return ERR_PROTECTED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
flag = disable_interrupts ();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
vu_short *addr = (vu_short *) (info->start[sect]);
*addr = 0x20; /* erase setup */
*addr = 0xD0; /* erase confirm */
while ((*addr & 0x80) != 0x80) {
if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = 0xB0; /* suspend erase */
*addr = 0xFF; /* reset to read mode */
rc = ERR_TIMOUT;
goto outahere;
}
}
/* clear status register command */
*addr = 0x50;
/* reset to read mode */
*addr = 0xFF;
}
printf ("ok.\n");
}
if (ctrlc ())
printf ("User Interrupt!\n");
outahere:
/* allow flash to settle - wait 10 ms */
udelay_masked (10000);
if (flag)
enable_interrupts ();
return rc;
}
/*-----------------------------------------------------------------------
* Copy memory to flash
*/
static int write_word (flash_info_t * info, ulong dest, ushort data)
{
vu_short *addr = (vu_short *) dest, val;
int rc = ERR_OK;
int flag;
ulong start;
/* Check if Flash is (sufficiently) erased
*/
if ((*addr & data) != data)
return ERR_NOT_ERASED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
flag = disable_interrupts ();
/* clear status register command */
*addr = 0x50;
/* program set-up command */
*addr = 0x40;
/* latch address/data */
*addr = data;
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
/* wait while polling the status register */
while (((val = *addr) & 0x80) != 0x80) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
rc = ERR_TIMOUT;
/* suspend program command */
*addr = 0xB0;
goto outahere;
}
}
if (val & 0x1A) { /* check for error */
printf ("\nFlash write error %02x at address %08lx\n",
(int) val, (unsigned long) dest);
if (val & (1 << 3)) {
printf ("Voltage range error.\n");
rc = ERR_PROG_ERROR;
goto outahere;
}
if (val & (1 << 1)) {
printf ("Device protect error.\n");
rc = ERR_PROTECTED;
goto outahere;
}
if (val & (1 << 4)) {
printf ("Programming error.\n");
rc = ERR_PROG_ERROR;
goto outahere;
}
rc = ERR_PROG_ERROR;
goto outahere;
}
outahere:
/* read array command */
*addr = 0xFF;
if (flag)
enable_interrupts ();
return rc;
}
/*-----------------------------------------------------------------------
* Copy memory to flash.
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp;
ushort data;
int l;
int i, rc;
wp = (addr & ~1); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data >> 8) | (*(uchar *) cp << 8);
}
for (; i < 2 && cnt > 0; ++i) {
data = (data >> 8) | (*src++ << 8);
--cnt;
++cp;
}
for (; cnt == 0 && i < 2; ++i, ++cp) {
data = (data >> 8) | (*(uchar *) cp << 8);
}
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
wp += 2;
}
/*
* handle word aligned part
*/
while (cnt >= 2) {
data = *((vu_short *) src);
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
src += 2;
wp += 2;
cnt -= 2;
}
if (cnt == 0) {
return ERR_OK;
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
data = (data >> 8) | (*src++ << 8);
--cnt;
}
for (; i < 2; ++i, ++cp) {
data = (data >> 8) | (*(uchar *) cp << 8);
}
return write_word (info, wp, data);
}

2
board/davinci/da8xxevm/da830evm.c
View file

@ -46,8 +46,6 @@
DECLARE_GLOBAL_DATA_PTR;
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
/* SPI0 pin muxer settings */
static const struct pinmux_config spi0_pins[] = {
{ pinmux(7), 1, 3 },

165
board/davinci/da8xxevm/da850evm.c
View file

@ -28,137 +28,14 @@
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/emac_defs.h>
#include <asm/arch/pinmux_defs.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
#include <hwconfig.h>
DECLARE_GLOBAL_DATA_PTR;
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
/* SPI0 pin muxer settings */
static const struct pinmux_config spi1_pins[] = {
{ pinmux(5), 1, 1 },
{ pinmux(5), 1, 2 },
{ pinmux(5), 1, 4 },
{ pinmux(5), 1, 5 }
};
/* UART pin muxer settings */
static const struct pinmux_config uart_pins[] = {
{ pinmux(0), 4, 6 },
{ pinmux(0), 4, 7 },
{ pinmux(4), 2, 4 },
{ pinmux(4), 2, 5 }
};
#ifdef CONFIG_DRIVER_TI_EMAC
static const struct pinmux_config emac_pins[] = {
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
{ pinmux(14), 8, 2 },
{ pinmux(14), 8, 3 },
{ pinmux(14), 8, 4 },
{ pinmux(14), 8, 5 },
{ pinmux(14), 8, 6 },
{ pinmux(14), 8, 7 },
{ pinmux(15), 8, 1 },
#else /* ! CONFIG_DRIVER_TI_EMAC_USE_RMII */
{ pinmux(2), 8, 1 },
{ pinmux(2), 8, 2 },
{ pinmux(2), 8, 3 },
{ pinmux(2), 8, 4 },
{ pinmux(2), 8, 5 },
{ pinmux(2), 8, 6 },
{ pinmux(2), 8, 7 },
{ pinmux(3), 8, 0 },
{ pinmux(3), 8, 1 },
{ pinmux(3), 8, 2 },
{ pinmux(3), 8, 3 },
{ pinmux(3), 8, 4 },
{ pinmux(3), 8, 5 },
{ pinmux(3), 8, 6 },
{ pinmux(3), 8, 7 },
#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
{ pinmux(4), 8, 0 },
{ pinmux(4), 8, 1 }
};
/* I2C pin muxer settings */
static const struct pinmux_config i2c_pins[] = {
{ pinmux(4), 2, 2 },
{ pinmux(4), 2, 3 }
};
#ifdef CONFIG_NAND_DAVINCI
const struct pinmux_config nand_pins[] = {
{ pinmux(7), 1, 1 },
{ pinmux(7), 1, 2 },
{ pinmux(7), 1, 4 },
{ pinmux(7), 1, 5 },
{ pinmux(9), 1, 0 },
{ pinmux(9), 1, 1 },
{ pinmux(9), 1, 2 },
{ pinmux(9), 1, 3 },
{ pinmux(9), 1, 4 },
{ pinmux(9), 1, 5 },
{ pinmux(9), 1, 6 },
{ pinmux(9), 1, 7 },
{ pinmux(12), 1, 5 },
{ pinmux(12), 1, 6 }
};
#elif defined(CONFIG_USE_NOR)
/* NOR pin muxer settings */
const struct pinmux_config nor_pins[] = {
/* GP0[11] is required for NOR to work on Rev 3 EVMs */
{ pinmux(0), 8, 4 }, /* GP0[11] */
{ pinmux(5), 1, 6 },
{ pinmux(6), 1, 6 },
{ pinmux(7), 1, 0 },
{ pinmux(7), 1, 4 },
{ pinmux(7), 1, 5 },
{ pinmux(8), 1, 0 },
{ pinmux(8), 1, 1 },
{ pinmux(8), 1, 2 },
{ pinmux(8), 1, 3 },
{ pinmux(8), 1, 4 },
{ pinmux(8), 1, 5 },
{ pinmux(8), 1, 6 },
{ pinmux(8), 1, 7 },
{ pinmux(9), 1, 0 },
{ pinmux(9), 1, 1 },
{ pinmux(9), 1, 2 },
{ pinmux(9), 1, 3 },
{ pinmux(9), 1, 4 },
{ pinmux(9), 1, 5 },
{ pinmux(9), 1, 6 },
{ pinmux(9), 1, 7 },
{ pinmux(10), 1, 0 },
{ pinmux(10), 1, 1 },
{ pinmux(10), 1, 2 },
{ pinmux(10), 1, 3 },
{ pinmux(10), 1, 4 },
{ pinmux(10), 1, 5 },
{ pinmux(10), 1, 6 },
{ pinmux(10), 1, 7 },
{ pinmux(11), 1, 0 },
{ pinmux(11), 1, 1 },
{ pinmux(11), 1, 2 },
{ pinmux(11), 1, 3 },
{ pinmux(11), 1, 4 },
{ pinmux(11), 1, 5 },
{ pinmux(11), 1, 6 },
{ pinmux(11), 1, 7 },
{ pinmux(12), 1, 0 },
{ pinmux(12), 1, 1 },
{ pinmux(12), 1, 2 },
{ pinmux(12), 1, 3 },
{ pinmux(12), 1, 4 },
{ pinmux(12), 1, 5 },
{ pinmux(12), 1, 6 },
{ pinmux(12), 1, 7 }
};
#endif
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
#define HAS_RMII 1
#else
@ -224,17 +101,38 @@ int misc_init_r(void)
return 0;
}
static const struct pinmux_config gpio_pins[] = {
#ifdef CONFIG_USE_NOR
/* GP0[11] is required for NOR to work on Rev 3 EVMs */
{ pinmux(0), 8, 4 }, /* GP0[11] */
#endif
};
static const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_DRIVER_TI_EMAC
PINMUX_ITEM(emac_pins_mdio),
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
PINMUX_ITEM(emac_pins_rmii),
#else
PINMUX_ITEM(emac_pins_mii),
#endif
#endif
#ifdef CONFIG_SPI_FLASH
PINMUX_ITEM(spi1_pins),
PINMUX_ITEM(spi1_pins_base),
PINMUX_ITEM(spi1_pins_scs0),
#endif
PINMUX_ITEM(uart_pins),
PINMUX_ITEM(i2c_pins),
PINMUX_ITEM(uart2_pins_txrx),
PINMUX_ITEM(uart2_pins_rtscts),
PINMUX_ITEM(i2c0_pins),
#ifdef CONFIG_NAND_DAVINCI
PINMUX_ITEM(nand_pins),
PINMUX_ITEM(emifa_pins_cs3),
PINMUX_ITEM(emifa_pins_cs4),
PINMUX_ITEM(emifa_pins_nand),
#elif defined(CONFIG_USE_NOR)
PINMUX_ITEM(nor_pins),
PINMUX_ITEM(emifa_pins_cs2),
PINMUX_ITEM(emifa_pins_nor),
#endif
PINMUX_ITEM(gpio_pins),
};
static const struct lpsc_resource lpsc[] = {
@ -249,6 +147,8 @@ static const struct lpsc_resource lpsc[] = {
#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
#endif
#define REV_AM18X_EVM 0x100
/*
* get_board_rev() - setup to pass kernel board revision information
* Returns:
@ -274,7 +174,9 @@ u32 get_board_rev(void)
rev = 2;
else if (maxcpuclk >= 372000000)
rev = 1;
#ifdef CONFIG_DA850_AM18X_EVM
rev |= REV_AM18X_EVM;
#endif
return rev;
}
@ -346,9 +248,6 @@ int board_init(void)
#endif
#ifdef CONFIG_DRIVER_TI_EMAC
if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
return 1;
davinci_emac_mii_mode_sel(HAS_RMII);
#endif /* CONFIG_DRIVER_TI_EMAC */

59
board/davinci/da8xxevm/hawkboard_nand_spl.c
View file

@ -27,63 +27,20 @@
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
#include <asm/arch/pinmux_defs.h>
#include <ns16550.h>
#include <nand.h>
DECLARE_GLOBAL_DATA_PTR;
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
static const struct pinmux_config mii_pins[] = {
{ pinmux(2), 8, 1 },
{ pinmux(2), 8, 2 },
{ pinmux(2), 8, 3 },
{ pinmux(2), 8, 4 },
{ pinmux(2), 8, 5 },
{ pinmux(2), 8, 6 },
{ pinmux(2), 8, 7 }
};
static const struct pinmux_config mdio_pins[] = {
{ pinmux(4), 8, 0 },
{ pinmux(4), 8, 1 }
};
static const struct pinmux_config nand_pins[] = {
{ pinmux(7), 1, 1 },
{ pinmux(7), 1, 2 },
{ pinmux(7), 1, 4 },
{ pinmux(7), 1, 5 },
{ pinmux(9), 1, 0 },
{ pinmux(9), 1, 1 },
{ pinmux(9), 1, 2 },
{ pinmux(9), 1, 3 },
{ pinmux(9), 1, 4 },
{ pinmux(9), 1, 5 },
{ pinmux(9), 1, 6 },
{ pinmux(9), 1, 7 },
{ pinmux(12), 1, 5 },
{ pinmux(12), 1, 6 }
};
static const struct pinmux_config uart2_pins[] = {
{ pinmux(0), 4, 6 },
{ pinmux(0), 4, 7 },
{ pinmux(4), 2, 4 },
{ pinmux(4), 2, 5 }
};
static const struct pinmux_config i2c_pins[] = {
{ pinmux(4), 2, 4 },
{ pinmux(4), 2, 5 }
};
static const struct pinmux_resource pinmuxes[] = {
PINMUX_ITEM(mii_pins),
PINMUX_ITEM(mdio_pins),
PINMUX_ITEM(i2c_pins),
PINMUX_ITEM(nand_pins),
PINMUX_ITEM(uart2_pins),
PINMUX_ITEM(emac_pins_mii),
PINMUX_ITEM(emac_pins_mdio),
PINMUX_ITEM(emifa_pins_cs3),
PINMUX_ITEM(emifa_pins_cs4),
PINMUX_ITEM(emifa_pins_nand),
PINMUX_ITEM(uart2_pins_txrx),
PINMUX_ITEM(uart2_pins_rtscts),
};
static const struct lpsc_resource lpsc[] = {

2
board/davinci/ea20/ea20.c
View file

@ -40,8 +40,6 @@
DECLARE_GLOBAL_DATA_PTR;
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
static const struct da8xx_panel lcd_panel = {
/* Casio COM57H531x */
.name = "Casio_COM57H531x",

15
board/efikamx/efikamx.c
View file

@ -226,7 +226,7 @@ static void power_init(void)
/* Set core voltage to 1.1V */
pmic_reg_read(p, REG_SW_0, &val);
val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
val = (val & ~SWx_VOLT_MASK) | SWx_1_200V;
pmic_reg_write(p, REG_SW_0, val);
/* Setup VCC (SW2) to 1.25 */
@ -260,18 +260,23 @@ static void power_init(void)
(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
pmic_reg_write(p, REG_SW_5, val);
/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
/* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
pmic_reg_read(p, REG_SETTING_0, &val);
val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
pmic_reg_write(p, REG_SETTING_0, val);
/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
pmic_reg_read(p, REG_SETTING_1, &val);
val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
pmic_reg_write(p, REG_SETTING_1, val);
/* Enable VGEN1, VGEN2, VDIG, VPLL */
pmic_reg_read(p, REG_MODE_0, &val);
val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
pmic_reg_write(p, REG_MODE_0, val);
/* Configure VGEN3 and VCAM regulators to use external PNP */
val = VGEN3CONFIG | VCAMCONFIG;
pmic_reg_write(p, REG_MODE_1, val);
@ -279,7 +284,7 @@ static void power_init(void)
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
VVIDEOEN | VAUDIOEN | VSDEN;
VVIDEOEN | VAUDIOEN | VSDEN;
pmic_reg_write(p, REG_MODE_1, val);
pmic_reg_read(p, REG_POWER_CTL2, &val);

19
board/cradle/Makefile → board/egnite/ethernut5/Makefile
View file

@ -1,7 +1,10 @@
#
# (C) Copyright 2000-2006
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2010
# egnite GmbH
#
# See file CREDITS for list of people who contributed to this
# project.
#
@ -12,7 +15,7 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
@ -25,13 +28,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := cradle.o flash.o
COBJS-y += $(BOARD).o
COBJS-y += $(BOARD)_pwrman.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################

270
board/egnite/ethernut5/ethernut5.c Normal file
View file

@ -0,0 +1,270 @@
/*
* (C) Copyright 2011
* egnite GmbH <info@egnite.de>
*
* (C) Copyright 2010
* Ole Reinhardt <ole.reinhardt@thermotemp.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Ethernut 5 general board support
*
* Ethernut is an open source hardware and software project for
* embedded Ethernet devices. Hardware layouts and CAD files are
* freely available under BSD-like license.
*
* Ethernut 5 is the first member of the Ethernut board family
* with U-Boot and Linux support. This implementation is based
* on the original work done by Ole Reinhardt, but heavily modified
* to support additional features and the latest board revision 5.0F.
*
* Main board components are by default:
*
* Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash
* 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM
* 512 MBytes Micron MT29F4G08ABADA NAND Flash
* 4 MBytes Atmel AT45DB321D DataFlash
* SMSC LAN8710 Ethernet PHY
* Atmel ATmega168 MCU used for power management
* Linear Technology LTC4411 PoE controller
*
* U-Boot relevant board interfaces are:
*
* 100 Mbit Ethernet with IEEE 802.3af PoE
* RS-232 serial port
* USB host and device
* MMC/SD-Card slot
* Expansion port with I2C, SPI and more...
*
* Typically the U-Boot image is loaded from serial DataFlash into
* SDRAM by the samboot boot loader, which is located in internal
* NOR Flash and provides all essential initializations like CPU
* and peripheral clocks and, of course, the SDRAM configuration.
*
* For testing purposes it is also possibly to directly transfer
* the image into SDRAM via JTAG. A tested configuration exists
* for the Turtelizer 2 hardware dongle and the OpenOCD software.
* In this case the latter will do the basic hardware configuration
* via its reset-init script.
*
* For additional information visit the project home page at
* http://www.ethernut.de/
*/
#include <common.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#include <spi.h>
#include <dataflash.h>
#include <mmc.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_spi.h>
#include <asm/arch/gpio.h>
#include <asm/io.h>
#include "ethernut5_pwrman.h"
DECLARE_GLOBAL_DATA_PTR;
AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}
};
/*
* In fact we have 7 partitions, but u-boot supports 5 only. This is
* no big deal, because the first partition is reserved for applications
* and the last one is used by Nut/OS. Both need not to be visible here.
*/
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{ 0x00021000, 0x00041FFF, FLAG_PROTECT_SET, 0, "setup" },
{ 0x00042000, 0x000C5FFF, FLAG_PROTECT_SET, 0, "uboot" },
{ 0x000C6000, 0x00359FFF, FLAG_PROTECT_SET, 0, "kernel" },
{ 0x0035A000, 0x003DDFFF, FLAG_PROTECT_SET, 0, "nutos" },
{ 0x003DE000, 0x003FEFFF, FLAG_PROTECT_CLEAR, 0, "env" }
};
/*
* This is called last during early initialization. Most of the basic
* hardware interfaces are up and running.
*
* The SDRAM hardware has been configured by the first stage boot loader.
* We only need to announce its size, using u-boot's memory check.
*/
int dram_init(void)
{
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
#ifdef CONFIG_CMD_NAND
static void ethernut5_nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
unsigned long csa;
/* Assign CS3 to NAND/SmartMedia Interface */
csa = readl(&matrix->ebicsa);
csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
AT91_SMC_MODE_DBW_8 |
AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
#ifdef CONFIG_SYS_NAND_READY_PIN
/* Ready pin is optional. */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
#endif
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
/*
* This is called first during late initialization.
*/
int board_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/* Enable clocks for all PIOs */
writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
(1 << ATMEL_ID_PIOC),
&pmc->pcer);
/* Set adress of boot parameters. */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
/* Initialize UARTs and power management. */
at91_seriald_hw_init();
ethernut5_power_init();
#ifdef CONFIG_CMD_NAND
ethernut5_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
at91_spi0_hw_init(1 << 0);
#endif
return 0;
}
#ifdef CONFIG_MACB
/*
* This is optionally called last during late initialization.
*/
int board_eth_init(bd_t *bis)
{
const char *devname;
unsigned short mode;
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/* Enable on-chip EMAC clock. */
writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
/* Need to reset PHY via power management. */
ethernut5_phy_reset();
/* Set peripheral pins. */
at91_macb_hw_init();
/* Basic EMAC initialization. */
if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID))
return -1;
/*
* Early board revisions have a pull-down at the PHY's MODE0
* strap pin, which forces the PHY into power down. Here we
* switch to all-capable mode.
*/
devname = miiphy_get_current_dev();
if (miiphy_read(devname, 0, 18, &mode) == 0) {
/* Set mode[2:0] to 0b111. */
mode |= 0x00E0;
miiphy_write(devname, 0, 18, mode);
/* Soft reset overrides strap pins. */
miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
}
/* Sync environment with network devices, needed for nfsroot. */
return eth_init(gd->bd);
}
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
int board_mmc_init(bd_t *bd)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/* Enable MCI clock. */
writel(1 << ATMEL_ID_MCI, &pmc->pcer);
/* Initialize MCI hardware. */
at91_mci_hw_init();
/* Register the device. */
return atmel_mci_init((void *)ATMEL_BASE_MCI);
}
int board_mmc_getcd(u8 *cd, struct mmc *mmc)
{
*cd = at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN) ? 1 : 0;
return 0;
}
#endif
#ifdef CONFIG_ATMEL_SPI
/*
* Note, that u-boot uses different code for SPI bus access. While
* memory routines use automatic chip select control, the serial
* flash support requires 'manual' GPIO control. Thus, we switch
* modes.
*/
void spi_cs_activate(struct spi_slave *slave)
{
/* Enable NPCS0 in GPIO mode. This disables peripheral control. */
at91_set_pio_output(AT91_PIO_PORTA, 3, 0);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
/* Disable NPCS0 in GPIO mode. */
at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
/* Switch back to peripheral chip select control. */
at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
#endif

338
board/egnite/ethernut5/ethernut5_pwrman.c Normal file
View file

@ -0,0 +1,338 @@
/*
* (C) Copyright 2011
* egnite GmbH <info@egnite.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Ethernut 5 power management support
*
* This board may be supplied via USB, IEEE 802.3af PoE or an
* auxiliary DC input. An on-board ATmega168 microcontroller,
* the so called power management controller or PMC, is used
* to select the supply source and to switch on and off certain
* energy consuming board components. This allows to reduce the
* total stand-by consumption to less than 70mW.
*
* The main CPU communicates with the PMC via I2C. When
* CONFIG_CMD_BSP is defined in the board configuration file,
* then the board specific command 'pwrman' becomes available,
* which allows to manually deal with the PMC.
*
* Two distinct registers are provided by the PMC for enabling
* and disabling specific features. This avoids the often seen
* read-modify-write cycle or shadow register requirement.
* Additional registers are available to query the board
* status and temperature, the auxiliary voltage and to control
* the green user LED that is integrated in the reset switch.
*
* Note, that the AVR firmware of the PMC is released under BSDL.
*
* For additional information visit the project home page at
* http://www.ethernut.de/
*/
#include <common.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/gpio.h>
#include <asm/io.h>
#include <i2c.h>
#include "ethernut5_pwrman.h"
/* PMC firmware version */
static int pwrman_major;
static int pwrman_minor;
/*
* Enable Ethernut 5 power management.
*
* This function must be called during board initialization.
* While we are using u-boot's I2C subsystem, it may be required
* to enable the serial port before calling this function,
* in particular when debugging is enabled.
*
* If board specific commands are not available, we will activate
* all board components.
*/
void ethernut5_power_init(void)
{
pwrman_minor = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VERS);
pwrman_major = pwrman_minor >> 4;
pwrman_minor &= 15;
#ifndef CONFIG_CMD_BSP
/* Do not modify anything, if we do not have a known version. */
if (pwrman_major == 2) {
/* Without board specific commands we enable all features. */
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, ~PWRMAN_ETHRST);
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST);
}
#endif
}
/*
* Reset Ethernet PHY.
*
* This function allows the re-configure the PHY after
* changing its strap pins.
*/
void ethernut5_phy_reset(void)
{
/* Do not modify anything, if we do not have a known version. */
if (pwrman_major != 2)
return;
/*
* Make sure that the Ethernet clock is enabled and the PHY reset
* is disabled for at least 100 us.
*/
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHCLK);
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST);
udelay(100);
/*
* LAN8710 strap pins are
* PA14 => PHY MODE0
* PA15 => PHY MODE1
* PA17 => PHY MODE2 => 111b all capable
* PA18 => PHY ADDR0 => 0b
*/
at91_set_pio_input(AT91_PIO_PORTA, 14, 1);
at91_set_pio_input(AT91_PIO_PORTA, 15, 1);
at91_set_pio_input(AT91_PIO_PORTA, 17, 1);
at91_set_pio_input(AT91_PIO_PORTA, 18, 0);
/* Activate PHY reset for 100 us. */
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHRST);
udelay(100);
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST);
at91_set_pio_input(AT91_PIO_PORTA, 14, 1);
}
/*
* Output the firmware version we got during initialization.
*/
void ethernut5_print_version(void)
{
printf("%u.%u\n", pwrman_major, pwrman_minor);
}
/*
* All code below this point is optional and implements
* the 'pwrman' command.
*/
#ifdef CONFIG_CMD_BSP
/* Human readable names of PMC features */
char *pwrman_feat[8] = {
"board", "vbin", "vbout", "mmc",
"rs232", "ethclk", "ethrst", "wakeup"
};
/*
* Print all feature names, that have its related flags enabled.
*/
static void print_flagged_features(u8 flags)
{
int i;
for (i = 0; i < 8; i++) {
if (flags & (1 << i))
printf("%s ", pwrman_feat[i]);
}
}
/*
* Return flags of a given list of feature names.
*
* The function stops at the first unknown list entry and
* returns the number of detected names as a function result.
*/
static int feature_flags(char * const names[], int num, u8 *flags)
{
int i, j;
*flags = 0;
for (i = 0; i < num; i++) {
for (j = 0; j < 8; j++) {
if (strcmp(pwrman_feat[j], names[i]) == 0) {
*flags |= 1 << j;
break;
}
}
if (j > 7)
break;
}
return i;
}
void ethernut5_print_power(void)
{
u8 flags;
int i;
flags = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA);
for (i = 0; i < 2; i++) {
if (flags) {
print_flagged_features(flags);
printf("%s\n", i ? "off" : "on");
}
flags = ~flags;
}
}
void ethernut5_print_celsius(void)
{
int val;
/* Read ADC value from LM50 and return Celsius degrees. */
val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_TEMP);
val *= 5000; /* 100mV/degree with 5V reference */
val += 128; /* 8 bit resolution */
val /= 256;
val -= 450; /* Celsius offset, still x10 */
/* Output full degrees. */
printf("%d\n", (val + 5) / 10);
}
void ethernut5_print_voltage(void)
{
int val;
/* Read ADC value from divider and return voltage. */
val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VAUX);
/* Resistors are 100k and 12.1k */
val += 5;
val *= 180948;
val /= 100000;
val++;
/* Calculation was done in 0.1V units. */
printf("%d\n", (val + 5) / 10);
}
/*
* Process the board specific 'pwrman' command.
*/
int do_pwrman(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u8 val;
int i;
if (argc == 1) {
ethernut5_print_power();
} else if (argc == 2 && strcmp(argv[1], "reset") == 0) {
at91_set_pio_output(AT91_PIO_PORTB, 8, 1);
udelay(100);
at91_set_pio_output(AT91_PIO_PORTB, 8, 0);
udelay(100000);
} else if (argc == 2 && strcmp(argv[1], "temp") == 0) {
ethernut5_print_celsius();
} else if (argc == 2 && strcmp(argv[1], "vaux") == 0) {
ethernut5_print_voltage();
} else if (argc == 2 && strcmp(argv[1], "version") == 0) {
ethernut5_print_version();
} else if (strcmp(argv[1], "led") == 0) {
/* Control the green status LED. Blink frequency unit
** is 0.1s, very roughly. */
if (argc == 2) {
/* No more arguments, output current settings. */
val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL);
printf("led %u %u\n", val >> 4, val & 15);
} else {
/* First argument specifies the on-time. */
val = (u8) simple_strtoul(argv[2], NULL, 0);
val <<= 4;
if (argc > 3) {
/* Second argument specifies the off-time. */
val |= (u8) (simple_strtoul(argv[3], NULL, 0)
& 15);
}
/* Update the LED control register. */
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL, val);
}
} else {
/* We expect a list of features followed an optional status. */
argc--;
i = feature_flags(&argv[1], argc, &val);
if (argc == i) {
/* We got a list only, print status. */
val &= i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_STA);
if (val) {
if (i > 1)
print_flagged_features(val);
printf("active\n");
} else {
printf("inactive\n");
}
} else {
/* More arguments. */
if (i == 0) {
/* No given feature, use despensibles. */
val = PWRMAN_DISPENSIBLE;
}
if (strcmp(argv[i + 1], "on") == 0) {
/* Enable features. */
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA,
val);
} else if (strcmp(argv[i + 1], "off") == 0) {
/* Disable features. */
i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS,
val);
} else {
printf("Bad parameter %s\n", argv[i + 1]);
return 1;
}
}
}
return 0;
}
U_BOOT_CMD(
pwrman, CONFIG_SYS_MAXARGS, 1, do_pwrman,
"power management",
"- print settings\n"
"pwrman feature ...\n"
" - print status\n"
"pwrman [feature ...] on|off\n"
" - enable/disable specified or all dispensible features\n"
"pwrman led [on-time [off-time]]\n"
" - print or set led blink timer\n"
"pwrman temp\n"
" - print board temperature (Celsius)\n"
"pwrman vaux\n"
" - print auxiliary input voltage\n"
"pwrman reset\n"
" - reset power management controller\n"
"pwrman version\n"
" - print firmware version\n"
"\n"
" features, (*)=dispensible:\n"
" board - 1.8V and 3.3V supply\n"
" vbin - supply via USB device connector\n"
" vbout - USB host connector supply(*)\n"
" mmc - MMC slot supply(*)\n"
" rs232 - RS232 driver\n"
" ethclk - Ethernet PHY clock(*)\n"
" ethrst - Ethernet PHY reset\n"
" wakeup - RTC alarm"
);
#endif /* CONFIG_CMD_BSP */

68
board/egnite/ethernut5/ethernut5_pwrman.h Normal file
View file

@ -0,0 +1,68 @@
/*
* (C) Copyright 2011
* egnite GmbH <info@egnite.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Ethernut 5 power management support
*
* For additional information visit the project home page at
* http://www.ethernut.de/
*/
/* I2C address of the PMC */
#define PWRMAN_I2C_ADDR 0x22
/* PMC registers */
#define PWRMAN_REG_VERS 0 /* Version register */
#define PWRMAN_REG_STA 1 /* Feature status register */
#define PWRMAN_REG_ENA 2 /* Feature enable register */
#define PWRMAN_REG_DIS 3 /* Feature disable register */
#define PWRMAN_REG_TEMP 4 /* Board temperature */
#define PWRMAN_REG_VAUX 6 /* Auxiliary input voltage */
#define PWRMAN_REG_LEDCTL 8 /* LED blinking timer. */
/* Feature flags used in status, enable and disable registers */
#define PWRMAN_BOARD 0x01 /* 1.8V and 3.3V supply */
#define PWRMAN_VBIN 0x02 /* VBUS input at device connector */
#define PWRMAN_VBOUT 0x04 /* VBUS output at host connector */
#define PWRMAN_MMC 0x08 /* Memory card supply */
#define PWRMAN_RS232 0x10 /* RS-232 driver shutdown */
#define PWRMAN_ETHCLK 0x20 /* Ethernet clock enable */
#define PWRMAN_ETHRST 0x40 /* Ethernet PHY reset */
#define PWRMAN_WAKEUP 0x80 /* RTC wake-up */
/* Features, which are not essential to keep u-boot alive */
#define PWRMAN_DISPENSIBLE (PWRMAN_VBOUT | PWRMAN_MMC | PWRMAN_ETHCLK)
/* Enable Ethernut 5 power management. */
extern void ethernut5_power_init(void);
/* Reset Ethernet PHY. */
extern void ethernut5_phy_reset(void);
extern void ethernut5_print_version(void);
#ifdef CONFIG_CMD_BSP
extern void ethernut5_print_power(void);
extern void ethernut5_print_celsius(void);
extern void ethernut5_print_voltage(void);
#endif

12
board/davinci/common/Makefile → board/enbw/enbw_cmc/Makefile
View file

@ -1,7 +1,9 @@
#
# (C) Copyright 2006
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# See file CREDITS for list of people who contributed to this
# project.
#
@ -23,13 +25,9 @@
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)board/$(VENDOR)/common)
endif
LIB = $(obj)lib$(BOARD).o
LIB = $(obj)lib$(VENDOR).o
COBJS := misc.o davinci_pinmux.o
COBJS := $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

607
board/enbw/enbw_cmc/enbw_cmc.c Normal file
View file

@ -0,0 +1,607 @@
/*
* (C) Copyright 2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
* Based on da830evm.c. Original Copyrights follow:
*
* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <command.h>
#include <environment.h>
#include <hwconfig.h>
#include <i2c.h>
#include <malloc.h>
#include <miiphy.h>
#include <mmc.h>
#include <net.h>
#include <netdev.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/da850_lowlevel.h>
#include <asm/arch/davinci_misc.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/emac_defs.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux_defs.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sdmmc_defs.h>
#include <asm/arch/timer_defs.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct lpsc_resource lpsc[] = {
{ DAVINCI_LPSC_AEMIF },
{ DAVINCI_LPSC_SPI1 },
{ DAVINCI_LPSC_ARM_RAM_ROM },
{ DAVINCI_LPSC_UART0 },
{ DAVINCI_LPSC_EMAC },
{ DAVINCI_LPSC_UART0 },
{ DAVINCI_LPSC_GPIO },
{ DAVINCI_LPSC_DDR_EMIF },
{ DAVINCI_LPSC_UART1 },
{ DAVINCI_LPSC_UART2 },
{ DAVINCI_LPSC_MMC_SD1 },
{ DAVINCI_LPSC_USB20 },
{ DAVINCI_LPSC_USB11 },
};
static const struct pinmux_config enbw_pins[] = {
{ pinmux(0), 8, 0 },
{ pinmux(0), 8, 1 },
{ pinmux(0), 8, 2 },
{ pinmux(0), 8, 3 },
{ pinmux(0), 8, 4 },
{ pinmux(0), 8, 5 },
{ pinmux(1), 4, 0 },
{ pinmux(1), 8, 1 },
{ pinmux(1), 8, 2 },
{ pinmux(1), 8, 3 },
{ pinmux(1), 8, 4 },
{ pinmux(1), 8, 5 },
{ pinmux(1), 8, 6 },
{ pinmux(1), 4, 7 },
{ pinmux(2), 8, 0 },
{ pinmux(5), 1, 0 },
{ pinmux(5), 1, 3 },
{ pinmux(5), 1, 7 },
{ pinmux(6), 1, 0 },
{ pinmux(6), 1, 1 },
{ pinmux(6), 8, 2 },
{ pinmux(6), 8, 3 },
{ pinmux(6), 1, 4 },
{ pinmux(6), 8, 5 },
{ pinmux(6), 1, 7 },
{ pinmux(7), 8, 2 },
{ pinmux(7), 1, 3 },
{ pinmux(7), 1, 6 },
{ pinmux(7), 1, 7 },
{ pinmux(13), 8, 2 },
{ pinmux(13), 8, 3 },
{ pinmux(13), 8, 4 },
{ pinmux(13), 8, 5 },
{ pinmux(13), 8, 6 },
{ pinmux(13), 8, 7 },
{ pinmux(14), 8, 0 },
{ pinmux(14), 8, 1 },
{ pinmux(16), 8, 1 },
{ pinmux(16), 8, 2 },
{ pinmux(16), 8, 3 },
{ pinmux(16), 8, 4 },
{ pinmux(16), 8, 5 },
{ pinmux(16), 8, 6 },
{ pinmux(16), 8, 7 },
{ pinmux(17), 1, 0 },
{ pinmux(17), 1, 1 },
{ pinmux(17), 1, 2 },
{ pinmux(17), 8, 3 },
{ pinmux(17), 8, 4 },
{ pinmux(17), 8, 5 },
{ pinmux(17), 8, 6 },
{ pinmux(17), 8, 7 },
{ pinmux(18), 8, 0 },
{ pinmux(18), 8, 1 },
{ pinmux(18), 2, 2 },
{ pinmux(18), 2, 3 },
{ pinmux(18), 2, 4 },
{ pinmux(18), 8, 6 },
{ pinmux(18), 8, 7 },
{ pinmux(19), 8, 0 },
{ pinmux(19), 2, 1 },
{ pinmux(19), 2, 2 },
{ pinmux(19), 2, 3 },
{ pinmux(19), 2, 4 },
{ pinmux(19), 8, 5 },
{ pinmux(19), 8, 6 },
};
const struct pinmux_resource pinmuxes[] = {
PINMUX_ITEM(emac_pins_mii),
PINMUX_ITEM(emac_pins_mdio),
PINMUX_ITEM(i2c0_pins),
PINMUX_ITEM(emifa_pins_cs2),
PINMUX_ITEM(emifa_pins_cs3),
PINMUX_ITEM(emifa_pins_cs4),
PINMUX_ITEM(emifa_pins_nand),
PINMUX_ITEM(emifa_pins_nor),
PINMUX_ITEM(spi1_pins_base),
PINMUX_ITEM(spi1_pins_scs0),
PINMUX_ITEM(uart1_pins_txrx),
PINMUX_ITEM(uart2_pins_txrx),
PINMUX_ITEM(uart2_pins_rtscts),
PINMUX_ITEM(enbw_pins),
};
const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
struct gpio_config {
char name[GPIO_NAME_SIZE];
unsigned char bank;
unsigned char gpio;
unsigned char out;
unsigned char value;
};
static const struct gpio_config enbw_gpio_config[] = {
{ "RS485 enable", 8, 11, 1, 0 },
{ "RS485 iso", 8, 10, 1, 0 },
{ "W2HUT RS485 Rx ena", 8, 9, 1, 0 },
{ "W2HUT RS485 iso", 8, 8, 1, 0 },
{ "LAN reset", 7, 15, 1, 1 },
{ "ena 11V PLC", 7, 14, 1, 0 },
{ "ena 1.5V PLC", 7, 13, 1, 0 },
{ "disable VBUS", 7, 12, 1, 1 },
{ "PLC reset", 6, 13, 1, 1 },
{ "LCM RS", 6, 12, 1, 0 },
{ "LCM R/W", 6, 11, 1, 0 },
{ "PLC pairing", 6, 10, 1, 1 },
{ "PLC MDIO CLK", 6, 9, 1, 0 },
{ "HK218", 6, 8, 1, 0 },
{ "HK218 Rx", 6, 1, 1, 1 },
{ "TPM reset", 6, 0, 1, 1 },
{ "LCM E", 2, 2, 1, 1 },
{ "PV-IF RxD ena", 0, 15, 1, 1 },
{ "LED1", 1, 15, 1, 1 },
{ "LED2", 0, 1, 1, 1 },
{ "LED3", 0, 2, 1, 1 },
{ "LED4", 0, 3, 1, 1 },
{ "LED5", 0, 4, 1, 1 },
{ "LED6", 0, 5, 1, 0 },
{ "LED7", 0, 6, 1, 0 },
{ "LED8", 0, 14, 1, 0 },
{ "USER1", 0, 12, 0, 0 },
{ "USER2", 0, 13, 0, 0 },
};
#define PHY_POWER 0x0800
static void enbw_cmc_switch(int port, int on)
{
const char *devname;
unsigned char phyaddr = 3;
unsigned char reg = 0;
unsigned short data;
if (port == 1)
phyaddr = 2;
devname = miiphy_get_current_dev();
if (!devname) {
printf("Error: no mii device\n");
return;
}
if (miiphy_read(devname, phyaddr, reg, &data) != 0) {
printf("Error reading from the PHY addr=%02x reg=%02x\n",
phyaddr, reg);
return;
}
if (on)
data &= ~PHY_POWER;
else
data |= PHY_POWER;
if (miiphy_write(devname, phyaddr, reg, data) != 0) {
printf("Error writing to the PHY addr=%02x reg=%02x\n",
phyaddr, reg);
return;
}
}
int board_init(void)
{
int i, ret;
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
/* address of boot parameters, not used as booting with DTT */
gd->bd->bi_boot_params = 0;
for (i = 0; i < ARRAY_SIZE(enbw_gpio_config); i++) {
int gpio = enbw_gpio_config[i].bank * 16 +
enbw_gpio_config[i].gpio;
ret = gpio_request(gpio, enbw_gpio_config[i].name);
if (ret) {
printf("%s: Could not get %s gpio\n", __func__,
enbw_gpio_config[i].name);
return -1;
}
if (enbw_gpio_config[i].out)
gpio_direction_output(gpio,
enbw_gpio_config[i].value);
else
gpio_direction_input(gpio);
}
/* setup the SUSPSRC for ARM to control emulation suspend */
clrbits_le32(&davinci_syscfg_regs->suspsrc,
(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART2));
return 0;
}
#ifdef CONFIG_DRIVER_TI_EMAC
/*
* Initializes on-board ethernet controllers.
*/
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_DRIVER_TI_EMAC
davinci_emac_mii_mode_sel(0);
#endif /* CONFIG_DRIVER_TI_EMAC */
if (!davinci_emac_initialize()) {
printf("Error: Ethernet init failed!\n");
return -1;
}
if (hwconfig_subarg_cmp("switch", "lan", "on"))
/* Switch port lan on */
enbw_cmc_switch(1, 1);
else
enbw_cmc_switch(1, 0);
if (hwconfig_subarg_cmp("switch", "pwl", "on"))
/* Switch port pwl on */
enbw_cmc_switch(2, 1);
else
enbw_cmc_switch(2, 0);
return 0;
}
#endif /* CONFIG_DRIVER_TI_EMAC */
#ifdef CONFIG_PREBOOT
static uchar kbd_magic_prefix[] = "key_magic_";
static uchar kbd_command_prefix[] = "key_cmd_";
struct kbd_data_t {
char s1;
};
struct kbd_data_t *get_keys(struct kbd_data_t *kbd_data)
{
/* read SW1 + SW2 */
kbd_data->s1 = gpio_get_value(12) +
(gpio_get_value(13) << 1);
return kbd_data;
}
static int compare_magic(const struct kbd_data_t *kbd_data, char *str)
{
char s1 = str[0];
if (s1 >= '0' && s1 <= '9')
s1 -= '0';
else if (s1 >= 'a' && s1 <= 'f')
s1 = s1 - 'a' + 10;
else if (s1 >= 'A' && s1 <= 'F')
s1 = s1 - 'A' + 10;
else
return -1;
if (s1 != kbd_data->s1)
return -1;
return 0;
}
static char *key_match(const struct kbd_data_t *kbd_data)
{
char magic[sizeof(kbd_magic_prefix) + 1];
char *suffix;
char *kbd_magic_keys;
/*
* The following string defines the characters that can be appended
* to "key_magic" to form the names of environment variables that
* hold "magic" key codes, i. e. such key codes that can cause
* pre-boot actions. If the string is empty (""), then only
* "key_magic" is checked (old behaviour); the string "125" causes
* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
*/
kbd_magic_keys = getenv("magic_keys");
if (kbd_magic_keys == NULL)
kbd_magic_keys = "";
/*
* loop over all magic keys;
* use '\0' suffix in case of empty string
*/
for (suffix = kbd_magic_keys; *suffix ||
suffix == kbd_magic_keys; ++suffix) {
sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
if (compare_magic(kbd_data, getenv(magic)) == 0) {
char cmd_name[sizeof(kbd_command_prefix) + 1];
char *cmd;
sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
cmd = getenv(cmd_name);
return cmd;
}
}
return NULL;
}
#endif /* CONFIG_PREBOOT */
int misc_init_r(void)
{
char *s, buf[32];
#ifdef CONFIG_PREBOOT
struct kbd_data_t kbd_data;
/* Decode keys */
char *str = strdup(key_match(get_keys(&kbd_data)));
/* Set or delete definition */
setenv("preboot", str);
free(str);
#endif /* CONFIG_PREBOOT */
/* count all restarts, and save this in an environment var */
s = getenv("restartcount");
if (s)
sprintf(buf, "%ld", simple_strtoul(s, NULL, 10) + 1);
else
strcpy(buf, "1");
setenv("restartcount", buf);
saveenv();
#ifdef CONFIG_HW_WATCHDOG
davinci_hw_watchdog_enable();
#endif
return 0;
}
struct cmc_led {
char name[20];
unsigned char bank;
unsigned char gpio;
};
struct cmc_led led_table[] = {
{"led1", 1, 15},
{"led2", 0, 1},
{"led3", 0, 2},
{"led4", 0, 3},
{"led5", 0, 4},
{"led6", 0, 5},
{"led7", 0, 6},
{"led8", 0, 14},
};
static int cmc_get_led_state(struct cmc_led *led)
{
int value;
int gpio = led->bank * 16 + led->gpio;
value = gpio_get_value(gpio);
return value;
}
static int cmc_set_led_state(struct cmc_led *led, int state)
{
int gpio = led->bank * 16 + led->gpio;
gpio_set_value(gpio, state);
return 0;
}
static int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
struct cmc_led *led;
int found = 0;
int i = 0;
int only_print = 0;
int len = ARRAY_SIZE(led_table);
if (argc < 2)
return cmd_usage(cmdtp);
if (argc < 3)
only_print = 1;
led = led_table;
while ((!found) && (i < len)) {
if (strcmp(argv[1], led->name) == 0) {
found = 1;
} else {
led++;
i++;
}
}
if (!found)
return cmd_usage(cmdtp);
if (only_print) {
if (cmc_get_led_state(led))
printf("on\n");
else
printf("off\n");
return 0;
}
if (strcmp(argv[2], "on") == 0)
cmc_set_led_state(led, 1);
else
cmc_set_led_state(led, 0);
return 0;
}
U_BOOT_CMD(led, 3, 1, do_led,
"switch on/off board led",
"[name] [on/off]"
);
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
davinci_hw_watchdog_reset();
}
#endif
#if defined(CONFIG_POST)
void arch_memory_failure_handle(void)
{
struct davinci_gpio *gpio = davinci_gpio_bank01;
int state = 1;
/*
* if memor< failure blink with the LED 1,2 and 3
* as we running from flash, we cannot use the gpio
* api here, so access the gpio pin direct through
* the gpio register.
*/
while (1) {
if (state) {
clrbits_le32(&gpio->out_data, 0x80000006);
state = 0;
} else {
setbits_le32(&gpio->out_data, 0x80000006);
state = 1;
}
udelay(500);
}
}
#endif
#if defined(CONFIG_BOOTCOUNT_LIMIT)
void bootcount_store(ulong a)
{
struct davinci_rtc *reg =
(struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR;
/*
* write RTC kick register to enable write
* for RTC Scratch registers. Cratch0 and 1 are
* used for bootcount values.
*/
out_be32(&reg->kick0r, RTC_KICK0R_WE);
out_be32(&reg->kick1r, RTC_KICK1R_WE);
out_be32(&reg->scratch0, a);
out_be32(&reg->scratch1, BOOTCOUNT_MAGIC);
}
ulong bootcount_load(void)
{
struct davinci_rtc *reg =
(struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR;
if (in_be32(&reg->scratch1) != BOOTCOUNT_MAGIC)
return 0;
else
return in_be32(&reg->scratch0);
}
#endif
void board_gpio_init(void)
{
struct davinci_gpio *gpio = davinci_gpio_bank01;
/*
* Power on required peripherals
* ARM does not have access by default to PSC0 and PSC1
* assuming here that the DSP bootloader has set the IOPU
* such that PSC access is available to ARM
*/
if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
return;
/*
* set LED (gpio Interface not usable here)
* set LED pins to output and state 0
*/
clrbits_le32(&gpio->dir, 0x8000407e);
clrbits_le32(&gpio->out_data, 0x8000407e);
/* set LED 1 - 5 to state on */
setbits_le32(&gpio->out_data, 0x8000001e);
}
int board_late_init(void)
{
cmc_set_led_state(&led_table[4], 0);
return 0;
}
void show_boot_progress(int val)
{
switch (val) {
case 1:
cmc_set_led_state(&led_table[4], 1);
break;
case 4:
cmc_set_led_state(&led_table[4], 0);
break;
case 15:
cmc_set_led_state(&led_table[4], 1);
break;
}
}
#ifdef CONFIG_DAVINCI_MMC
static struct davinci_mmc mmc_sd1 = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
.input_clk = 228000000,
.host_caps = MMC_MODE_4BIT,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.version = MMC_CTLR_VERSION_2,
};
int board_mmc_init(bd_t *bis)
{
mmc_sd1.input_clk = clk_get(DAVINCI_MMC_CLKID);
/* Add slot-0 to mmc subsystem */
return davinci_mmc_init(bis, &mmc_sd1);
}
#endif

3
board/freescale/mx51evk/mx51evk.c
View file

@ -265,6 +265,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1);
mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
*cd = gpio_get_value(0);
else

3
board/freescale/mx53ard/mx53ard.c
View file

@ -87,6 +87,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1);
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
*cd = gpio_get_value(1); /*GPIO1_1*/
else

3
board/freescale/mx53evk/mx53evk.c
View file

@ -212,6 +212,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
*cd = gpio_get_value(77); /*GPIO3_13*/
else

3
board/freescale/mx53loco/mx53loco.c
View file

@ -140,6 +140,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
*cd = gpio_get_value(77); /*GPIO3_13*/
else

1
board/freescale/mx53smd/mx53smd.c
View file

@ -134,6 +134,7 @@ struct fsl_esdhc_cfg esdhc_cfg[1] = {
int board_mmc_getcd(u8 *cd, struct mmc *mmc)
{
mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
*cd = gpio_get_value(77); /*GPIO3_13*/
return 0;

2
board/logicpd/am3517evm/am3517evm.c
View file

@ -76,7 +76,7 @@ void set_muxconf_regs(void)
MUX_AM3517EVM();
}
#ifdef CONFIG_GENERIC_MMC
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0);

40
board/logicpd/am3517evm/am3517evm.h
View file

@ -31,46 +31,6 @@ const omap3_sysinfo sysinfo = {
"AM3517EVM Board",
"NAND",
};
/* AM3517 specific mux configuration */
#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08
/* CCDC */
#define CONTROL_PADCONF_CCDC_PCLK 0x01E4
#define CONTROL_PADCONF_CCDC_FIELD 0x01E6
#define CONTROL_PADCONF_CCDC_HD 0x01E8
#define CONTROL_PADCONF_CCDC_VD 0x01EA
#define CONTROL_PADCONF_CCDC_WEN 0x01EC
#define CONTROL_PADCONF_CCDC_DATA0 0x01EE
#define CONTROL_PADCONF_CCDC_DATA1 0x01F0
#define CONTROL_PADCONF_CCDC_DATA2 0x01F2
#define CONTROL_PADCONF_CCDC_DATA3 0x01F4
#define CONTROL_PADCONF_CCDC_DATA4 0x01F6
#define CONTROL_PADCONF_CCDC_DATA5 0x01F8
#define CONTROL_PADCONF_CCDC_DATA6 0x01FA
#define CONTROL_PADCONF_CCDC_DATA7 0x01FC
/* RMII */
#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE
#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200
#define CONTROL_PADCONF_RMII_RXD0 0x0202
#define CONTROL_PADCONF_RMII_RXD1 0x0204
#define CONTROL_PADCONF_RMII_CRS_DV 0x0206
#define CONTROL_PADCONF_RMII_RXER 0x0208
#define CONTROL_PADCONF_RMII_TXD0 0x020A
#define CONTROL_PADCONF_RMII_TXD1 0x020C
#define CONTROL_PADCONF_RMII_TXEN 0x020E
#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210
#define CONTROL_PADCONF_USB0_DRVBUS 0x0212
/* CAN */
#define CONTROL_PADCONF_HECC1_TXD 0x0214
#define CONTROL_PADCONF_HECC1_RXD 0x0216
#define CONTROL_PADCONF_SYS_BOOT7 0x0218
#define CONTROL_PADCONF_SDRC_DQS0N 0x021A
#define CONTROL_PADCONF_SDRC_DQS1N 0x021C
#define CONTROL_PADCONF_SDRC_DQS2N 0x021E
#define CONTROL_PADCONF_SDRC_DQS3N 0x0220
#define CONTROL_PADCONF_STRBEN_DLY0 0x0222
#define CONTROL_PADCONF_STRBEN_DLY1 0x0224
#define CONTROL_PADCONF_SYS_BOOT8 0x0226
/*
* IEN - Input Enable

30
board/logicpd/am3517evm/config.mk
View file

@ -1,30 +0,0 @@
#
# Author: Vaibhav Hiremath <hvaibhav@ti.com>
#
# Based on ti/evm/config.mk
#
# Copyright (C) 2010
# Texas Instruments Incorporated - http://www.ti.com/
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
# Physical Address:
# 8000'0000 (bank0)
# A000/0000 (bank1)
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
# For use with external or internal boots.
CONFIG_SYS_TEXT_BASE = 0x80008000

4
board/lubbock/lubbock.c
View file

@ -27,6 +27,7 @@
#include <common.h>
#include <netdev.h>
#include <asm/arch/pxa.h>
DECLARE_GLOBAL_DATA_PTR;
@ -56,10 +57,9 @@ int board_late_init(void)
return 0;
}
extern void pxa_dram_init(void);
int dram_init(void)
{
pxa_dram_init();
pxa2xx_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}

4
board/palmld/palmld.c
View file

@ -23,6 +23,7 @@
#include <command.h>
#include <serial.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@ -56,10 +57,9 @@ struct serial_device *default_serial_console(void)
return &serial_ffuart_device;
}
extern void pxa_dram_init(void);
int dram_init(void)
{
pxa_dram_init();
pxa2xx_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}

4
board/palmtc/palmtc.c
View file

@ -23,6 +23,7 @@
#include <command.h>
#include <serial.h>
#include <asm/io.h>
#include <asm/arch/pxa.h>
DECLARE_GLOBAL_DATA_PTR;
@ -55,10 +56,9 @@ struct serial_device *default_serial_console(void)
return &serial_ffuart_device;
}
extern void pxa_dram_init(void);
int dram_init(void)
{
pxa_dram_init();
pxa2xx_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}

814
board/pleb2/flash.c
View file

@ -1,814 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8xx.h>
/* environment.h defines the various CONFIG_ENV_... values in terms
* of whichever ones are given in the configuration file.
*/
#include <environment.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
* has nothing to do with the flash chip being 8-bit or 16-bit.
*/
#ifdef CONFIG_FLASH_16BIT
typedef unsigned short FLASH_PORT_WIDTH;
typedef volatile unsigned short FLASH_PORT_WIDTHV;
#define FLASH_ID_MASK 0xFFFF
#else
typedef unsigned long FLASH_PORT_WIDTH;
typedef volatile unsigned long FLASH_PORT_WIDTHV;
#define FLASH_ID_MASK 0xFFFFFFFF
#endif
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define ORMASK(size) ((-size) & OR_AM_MSK)
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (FPWV * addr, flash_info_t * info);
static void flash_reset (flash_info_t * info);
static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data);
static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
static void flash_get_offsets (ulong base, flash_info_t * info);
#ifdef CONFIG_SYS_FLASH_PROTECTION
static void flash_sync_real_protect (flash_info_t * info);
#endif
/*-----------------------------------------------------------------------
* flash_init()
*
* sets up flash_info and returns size of FLASH (bytes)
*/
unsigned long flash_init (void)
{
unsigned long size_b;
int i;
/* Init: no FLASHes known */
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
size_b = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
flash_info[0].size = size_b;
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n",
size_b);
}
/* Do this again (was done already in flast_get_size), just
* in case we move it when remap the FLASH.
*/
flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
#ifdef CONFIG_SYS_FLASH_PROTECTION
/* read the hardware protection status (if any) into the
* protection array in flash_info.
*/
flash_sync_real_protect (&flash_info[0]);
#endif
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[0]);
#endif
#ifdef CONFIG_ENV_ADDR
flash_protect (FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]);
#endif
#ifdef CONFIG_ENV_ADDR_REDUND
flash_protect (FLAG_PROTECT_SET,
CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
return (size_b);
}
/*-----------------------------------------------------------------------
*/
static void flash_reset (flash_info_t * info)
{
FPWV *base = (FPWV *) (info->start[0]);
/* Put FLASH back in read mode */
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
*base = (FPW) 0x00FF00FF; /* Intel Read Mode */
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
*base = (FPW) 0x00F000F0; /* AMD Read Mode */
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t * info)
{
int i;
/* set up sector start address table */
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
&& (info->flash_id & FLASH_BTYPE)) {
int bootsect_size; /* number of bytes/boot sector */
int sect_size; /* number of bytes/regular sector */
bootsect_size = 0x00002000 * (sizeof (FPW) / 2);
sect_size = 0x00010000 * (sizeof (FPW) / 2);
/* set sector offsets for bottom boot block type */
for (i = 0; i < 8; ++i) {
info->start[i] = base + (i * bootsect_size);
}
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + ((i - 7) * sect_size);
}
} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
&& (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
int sect_size; /* number of bytes/sector */
sect_size = 0x00010000 * (sizeof (FPW) / 2);
/* set up sector start address table (uniform sector type) */
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * sect_size);
} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
&& (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) {
int sect_size; /* number of bytes/sector */
sect_size = 0x00010000 * (sizeof (FPW) / 2);
/* set up sector start address table (top boot sector type) */
for (i = 0; i < info->sector_count - 3; i++)
info->start[i] = base + (i * sect_size);
i = info->sector_count - 1;
info->start[i--] =
base + (info->size - 0x00004000) * (sizeof (FPW) / 2);
info->start[i--] =
base + (info->size - 0x00006000) * (sizeof (FPW) / 2);
info->start[i--] =
base + (info->size - 0x00008000) * (sizeof (FPW) / 2);
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
uchar *boottype;
uchar *bootletter;
char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
uchar topboottype[] = "top boot sector";
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
printf ("AMD ");
break;
case FLASH_MAN_BM:
printf ("BRIGHT MICRO ");
break;
case FLASH_MAN_FUJ:
printf ("FUJITSU ");
break;
case FLASH_MAN_SST:
printf ("SST ");
break;
case FLASH_MAN_STM:
printf ("STM ");
break;
case FLASH_MAN_INTEL:
printf ("INTEL ");
break;
default:
printf ("Unknown Vendor ");
break;
}
/* check for top or bottom boot, if it applies */
if (info->flash_id & FLASH_BTYPE) {
boottype = botboottype;
bootletter = botbootletter;
} else {
boottype = topboottype;
bootletter = topbootletter;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM800T:
fmt = "29LV800B%s (8 Mbit, %s)\n";
break;
case FLASH_AM640U:
fmt = "29LV641D (64 Mbit, uniform sectors)\n";
break;
case FLASH_28F800C3B:
case FLASH_28F800C3T:
fmt = "28F800C3%s (8 Mbit, %s)\n";
break;
case FLASH_INTEL800B:
case FLASH_INTEL800T:
fmt = "28F800B3%s (8 Mbit, %s)\n";
break;
case FLASH_28F160C3B:
case FLASH_28F160C3T:
fmt = "28F160C3%s (16 Mbit, %s)\n";
break;
case FLASH_INTEL160B:
case FLASH_INTEL160T:
fmt = "28F160B3%s (16 Mbit, %s)\n";
break;
case FLASH_28F320C3B:
case FLASH_28F320C3T:
fmt = "28F320C3%s (32 Mbit, %s)\n";
break;
case FLASH_INTEL320B:
case FLASH_INTEL320T:
fmt = "28F320B3%s (32 Mbit, %s)\n";
break;
case FLASH_28F640C3B:
case FLASH_28F640C3T:
fmt = "28F640C3%s (64 Mbit, %s)\n";
break;
case FLASH_INTEL640B:
case FLASH_INTEL640T:
fmt = "28F640B3%s (64 Mbit, %s)\n";
break;
default:
fmt = "Unknown Chip Type\n";
break;
}
printf (fmt, bootletter, boottype);
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0) {
printf ("\n ");
}
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
}
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
ulong flash_get_size (FPWV * addr, flash_info_t * info)
{
/* Write auto select command: read Manufacturer ID */
/* Write auto select command sequence and test FLASH answer */
addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */
addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */
addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */
/* The manufacturer codes are only 1 byte, so just use 1 byte.
* This works for any bus width and any FLASH device width.
*/
switch (addr[0] & 0xff) {
case (uchar) AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case (uchar) INTEL_MANUFACT:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
break;
}
/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
if (info->flash_id != FLASH_UNKNOWN)
switch (addr[1]) {
case (FPW) AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000 * (sizeof (FPW) / 2);
break; /* => 1 or 2 MiB */
case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
info->flash_id += FLASH_AM640U;
info->sector_count = 128;
info->size = 0x00800000 * (sizeof (FPW) / 2);
break; /* => 8 or 16 MB */
case (FPW) INTEL_ID_28F800C3B:
info->flash_id += FLASH_28F800C3B;
info->sector_count = 23;
info->size = 0x00100000 * (sizeof (FPW) / 2);
break; /* => 1 or 2 MB */
case (FPW) INTEL_ID_28F800B3B:
info->flash_id += FLASH_INTEL800B;
info->sector_count = 23;
info->size = 0x00100000 * (sizeof (FPW) / 2);
break; /* => 1 or 2 MB */
case (FPW) INTEL_ID_28F160C3B:
info->flash_id += FLASH_28F160C3B;
info->sector_count = 39;
info->size = 0x00200000 * (sizeof (FPW) / 2);
break; /* => 2 or 4 MB */
case (FPW) INTEL_ID_28F160B3B:
info->flash_id += FLASH_INTEL160B;
info->sector_count = 39;
info->size = 0x00200000 * (sizeof (FPW) / 2);
break; /* => 2 or 4 MB */
case (FPW) INTEL_ID_28F320C3B:
info->flash_id += FLASH_28F320C3B;
info->sector_count = 71;
info->size = 0x00400000 * (sizeof (FPW) / 2);
break; /* => 4 or 8 MB */
case (FPW) INTEL_ID_28F320B3B:
info->flash_id += FLASH_INTEL320B;
info->sector_count = 71;
info->size = 0x00400000 * (sizeof (FPW) / 2);
break; /* => 4 or 8 MB */
case (FPW) INTEL_ID_28F640C3B:
info->flash_id += FLASH_28F640C3B;
info->sector_count = 135;
info->size = 0x00800000 * (sizeof (FPW) / 2);
break; /* => 8 or 16 MB */
case (FPW) INTEL_ID_28F640B3B:
info->flash_id += FLASH_INTEL640B;
info->sector_count = 135;
info->size = 0x00800000 * (sizeof (FPW) / 2);
break; /* => 8 or 16 MB */
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* => no or unknown flash */
}
flash_get_offsets ((ulong) addr, info);
/* Put FLASH back in read mode */
flash_reset (info);
return (info->size);
}
#ifdef CONFIG_SYS_FLASH_PROTECTION
/*-----------------------------------------------------------------------
*/
static void flash_sync_real_protect (flash_info_t * info)
{
FPWV *addr = (FPWV *) (info->start[0]);
FPWV *sect;
int i;
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F800C3B:
case FLASH_28F800C3T:
case FLASH_28F160C3B:
case FLASH_28F160C3T:
case FLASH_28F320C3B:
case FLASH_28F320C3T:
case FLASH_28F640C3B:
case FLASH_28F640C3T:
/* check for protected sectors */
*addr = (FPW) 0x00900090;
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02.
* D0 = 1 for each device if protected.
* If at least one device is protected the sector is marked
* protected, but mixed protected and unprotected devices
* within a sector should never happen.
*/
sect = (FPWV *) (info->start[i]);
info->protect[i] =
(sect[2] & (FPW) (0x00010001)) ? 1 : 0;
}
/* Put FLASH back in read mode */
flash_reset (info);
break;
case FLASH_AM640U:
case FLASH_AM800T:
default:
/* no hardware protect that we support */
break;
}
}
#endif
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
FPWV *addr;
int flag, prot, sect;
int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
ulong start, now, last;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_INTEL800B:
case FLASH_INTEL160B:
case FLASH_INTEL320B:
case FLASH_INTEL640B:
case FLASH_28F800C3B:
case FLASH_28F160C3B:
case FLASH_28F320C3B:
case FLASH_28F640C3B:
case FLASH_AM640U:
case FLASH_AM800T:
break;
case FLASH_UNKNOWN:
default:
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf ("\n");
}
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
if (info->protect[sect] != 0) /* protected, skip it */
continue;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
start = get_timer(0);
last = 0;
addr = (FPWV *) (info->start[sect]);
if (intel) {
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
} else {
/* must be AMD style if not Intel */
FPWV *base; /* first address in bank */
base = (FPWV *) (info->start[0]);
base[0x0555] = (FPW) 0x00AA00AA; /* unlock */
base[0x02AA] = (FPW) 0x00550055; /* unlock */
base[0x0555] = (FPW) 0x00800080; /* erase mode */
base[0x0555] = (FPW) 0x00AA00AA; /* unlock */
base[0x02AA] = (FPW) 0x00550055; /* unlock */
*addr = (FPW) 0x00300030; /* erase sector */
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
/* wait at least 50us for AMD, 80us for Intel.
* Let's wait 1 ms.
*/
udelay (1000);
while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
if ((now =
get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
if (intel) {
/* suspend erase */
*addr = (FPW) 0x00B000B0;
}
flash_reset (info); /* reset to read mode */
rcode = 1; /* failed */
break;
}
/* show that we're waiting */
if ((now - last) > 1 * CONFIG_SYS_HZ) { /* every second */
putc ('.');
last = now;
}
}
flash_reset (info); /* reset to read mode */
}
printf (" done\n");
return rcode;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
int bytes; /* number of bytes to program in current word */
int left; /* number of bytes left to program */
int i, res;
for (left = cnt, res = 0;
left > 0 && res == 0;
addr += sizeof (data), left -= sizeof (data) - bytes) {
bytes = addr & (sizeof (data) - 1);
addr &= ~(sizeof (data) - 1);
/* combine source and destination data so can program
* an entire word of 16 or 32 bits
*/
#ifdef CONFIG_SYS_LITTLE_ENDIAN
for (i = 0; i < sizeof (data); i++) {
data >>= 8;
if (i < bytes || i - bytes >= left)
data += (*((uchar *) addr + i)) << 24;
else
data += (*src++) << 24;
}
#else
for (i = 0; i < sizeof (data); i++) {
data <<= 8;
if (i < bytes || i - bytes >= left)
data += *((uchar *) addr + i);
else
data += *src++;
}
#endif
/* write one word to the flash */
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
res = write_word_amd (info, (FPWV *) addr, data);
break;
case FLASH_MAN_INTEL:
res = write_word_intel (info, (FPWV *) addr, data);
break;
default:
/* unknown flash type, error! */
printf ("missing or unknown FLASH type\n");
res = 1; /* not really a timeout, but gives error */
break;
}
}
return (res);
}
/*-----------------------------------------------------------------------
* Write a word to Flash for AMD FLASH
* A word is 16 or 32 bits, whichever the bus width of the flash bank
* (not an individual chip) is.
*
* returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
{
int flag;
int res = 0; /* result, assume success */
FPWV *base; /* first address in flash bank */
ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*dest & data) != data) {
return (2);
}
base = (FPWV *) (info->start[0]);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
base[0x0555] = (FPW) 0x00AA00AA; /* unlock */
base[0x02AA] = (FPW) 0x00550055; /* unlock */
base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */
*dest = data; /* start programming the data */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
start = get_timer(0);
/* data polling for D7 */
while (res == 0
&& (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (FPW) 0x00F000F0; /* reset bank */
res = 1;
}
}
return (res);
}
/*-----------------------------------------------------------------------
* Write a word to Flash for Intel FLASH
* A word is 16 or 32 bits, whichever the bus width of the flash bank
* (not an individual chip) is.
*
* returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data)
{
int flag;
int res = 0; /* result, assume success */
ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*dest & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
*dest = (FPW) 0x00500050; /* clear status register */
*dest = (FPW) 0x00FF00FF; /* make sure in read mode */
*dest = (FPW) 0x00400040; /* program setup */
*dest = data; /* start programming the data */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
start = get_timer(0);
while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (FPW) 0x00B000B0; /* Suspend program */
res = 1;
}
}
if (res == 0 && (*dest & (FPW) 0x00100010))
res = 1; /* write failed, time out error is close enough */
*dest = (FPW) 0x00500050; /* clear status register */
*dest = (FPW) 0x00FF00FF; /* make sure in read mode */
return (res);
}
#ifdef CONFIG_SYS_FLASH_PROTECTION
/*-----------------------------------------------------------------------
*/
int flash_real_protect (flash_info_t * info, long sector, int prot)
{
int rcode = 0; /* assume success */
FPWV *addr; /* address of sector */
FPW value;
addr = (FPWV *) (info->start[sector]);
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F800C3B:
case FLASH_28F800C3T:
case FLASH_28F160C3B:
case FLASH_28F160C3T:
case FLASH_28F320C3B:
case FLASH_28F320C3T:
case FLASH_28F640C3B:
case FLASH_28F640C3T:
flash_reset (info); /* make sure in read mode */
*addr = (FPW) 0x00600060L; /* lock command setup */
if (prot)
*addr = (FPW) 0x00010001L; /* lock sector */
else
*addr = (FPW) 0x00D000D0L; /* unlock sector */
flash_reset (info); /* reset to read mode */
/* now see if it really is locked/unlocked as requested */
*addr = (FPW) 0x00900090;
/* read sector protection at sector address, (A7 .. A0) = 0x02.
* D0 = 1 for each device if protected.
* If at least one device is protected the sector is marked
* protected, but return failure. Mixed protected and
* unprotected devices within a sector should never happen.
*/
value = addr[2] & (FPW) 0x00010001;
if (value == 0)
info->protect[sector] = 0;
else if (value == (FPW) 0x00010001)
info->protect[sector] = 1;
else {
/* error, mixed protected and unprotected */
rcode = 1;
info->protect[sector] = 1;
}
if (info->protect[sector] != prot)
rcode = 1; /* failed to protect/unprotect as requested */
/* reload all protection bits from hardware for now */
flash_sync_real_protect (info);
break;
case FLASH_AM640U:
case FLASH_AM800T:
default:
/* no hardware protect that we support */
info->protect[sector] = prot;
break;
}
return rcode;
}
#endif

71
board/pleb2/pleb2.c
View file

@ -1,71 +0,0 @@
/*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mach-types.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Miscelaneous platform dependent initialisations
*/
int board_init (void)
{
/* We have RAM, disable cache */
dcache_disable();
icache_disable();
/* arch number of Lubbock-Board */
gd->bd->bi_arch_number = MACH_TYPE_PLEB2;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0xa0000100;
return 0;
}
int board_late_init(void)
{
setenv("stdout", "serial");
setenv("stderr", "serial");
return 0;
}
extern void pxa_dram_init(void);
int dram_init(void)
{
pxa_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}

Some files were not shown because too many files have changed in this diff Show more