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am335x_evm: Add better timings for the new BeagleBoard DDR3 part

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Tested-by: Rao Bodapati <rao@circuitco.com>
Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Tom Rini 2013-03-21 04:30:02 +00:00
parent ea7b96b6aa
commit c7ba18ad4b
2 changed files with 55 additions and 1 deletions
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17
arch/arm/include/asm/arch-am33xx/ddr_defs.h
View file

@ -83,6 +83,23 @@
#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
/* Micron MT41K256M16HA-125E */
#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100006
#define MT41K256M16HA125E_EMIF_TIM1 0x0888A39B
#define MT41K256M16HA125E_EMIF_TIM2 0x26517FDA
#define MT41K256M16HA125E_EMIF_TIM3 0x501F84EF
#define MT41K256M16HA125E_EMIF_SDCFG 0x61C04BB2
#define MT41K256M16HA125E_EMIF_SDREF 0x0000093B
#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
#define MT41K256M16HA125E_RATIO 0x40
#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
#define MT41K256M16HA125E_RD_DQS 0x3C
#define MT41K256M16HA125E_WR_DQS 0x45
#define MT41K256M16HA125E_PHY_WR_DATA 0x7F
#define MT41K256M16HA125E_PHY_FIFO_WE 0x9B
#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
/* Micron MT41J512M8RH-125 on EVM v1.5 */
#define MT41J512M8RH125_EMIF_READ_LATENCY 0x06
#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B

39
board/ti/am335x/board.c
View file

@ -208,6 +208,14 @@ static const struct ddr_data ddr3_data = {
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct ddr_data ddr3_beagleblack_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct ddr_data ddr3_evm_data = {
.datardsratio0 = MT41J512M8RH125_RD_DQS,
.datawdsratio0 = MT41J512M8RH125_WR_DQS,
@ -230,6 +238,20 @@ static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
};
static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
.cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
.cmd0csratio = MT41J512M8RH125_RATIO,
.cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
@ -255,6 +277,16 @@ static struct emif_regs ddr3_emif_reg_data = {
PHY_EN_DYN_PWRDN,
};
static struct emif_regs ddr3_beagleblack_emif_reg_data = {
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};
static struct emif_regs ddr3_evm_emif_reg_data = {
.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
@ -343,9 +375,14 @@ void s_init(void)
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
if (board_is_evm_sk() || board_is_bone_lt())
if (board_is_evm_sk())
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
else if (board_is_bone_lt())
config_ddr(303, MT41K256M16HA125E_IOCTRL_VALUE,
&ddr3_beagleblack_data,
&ddr3_beagleblack_cmd_ctrl_data,
&ddr3_beagleblack_emif_reg_data, 0);
else if (board_is_evm_15_or_later())
config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);