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am33xx/ddr_defs.h: rename DDR2/DDR3 defines to their actual part numbers

Browse source 
So other parts can be added.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
This commit is contained in:
Peter Korsgaard 2012-10-18 01:21:13 +00:00 • committed by Tom Rini
parent c00f69dbcd
commit c7d35bef25
2 changed files with 94 additions and 82 deletions
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64
arch/arm/include/asm/arch-am33xx/ddr_defs.h
View file

@ -30,40 +30,40 @@
#define DDR_CKE_CTRL_NORMAL 0x1 #define DDR_CKE_CTRL_NORMAL 0x1
/* Micron MT47H128M16RT-25E */ /* Micron MT47H128M16RT-25E */
#define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */ #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
#define DDR2_EMIF_TIM1 0x0666B3C9 #define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
#define DDR2_EMIF_TIM2 0x243631CA #define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
#define DDR2_EMIF_TIM3 0x0000033F #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
#define DDR2_EMIF_SDCFG 0x41805332 #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
#define DDR2_EMIF_SDREF 0x0000081a #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
#define DDR2_DLL_LOCK_DIFF 0x0 #define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0
#define DDR2_RATIO 0x80 #define MT47H128M16RT25E_RATIO 0x80
#define DDR2_INVERT_CLKOUT 0x00 #define MT47H128M16RT25E_INVERT_CLKOUT 0x00
#define DDR2_RD_DQS 0x12 #define MT47H128M16RT25E_RD_DQS 0x12
#define DDR2_WR_DQS 0x00 #define MT47H128M16RT25E_WR_DQS 0x00
#define DDR2_PHY_WRLVL 0x00 #define MT47H128M16RT25E_PHY_WRLVL 0x00
#define DDR2_PHY_GATELVL 0x00 #define MT47H128M16RT25E_PHY_GATELVL 0x00
#define DDR2_PHY_WR_DATA 0x40 #define MT47H128M16RT25E_PHY_WR_DATA 0x40
#define DDR2_PHY_FIFO_WE 0x80 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80
#define DDR2_PHY_RANK0_DELAY 0x1 #define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1
#define DDR2_IOCTRL_VALUE 0x18B #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
/* Micron MT41J128M16JT-125 */ /* Micron MT41J128M16JT-125 */
#define DDR3_EMIF_READ_LATENCY 0x06 #define MT41J128MJT125_EMIF_READ_LATENCY 0x06
#define DDR3_EMIF_TIM1 0x0888A39B #define MT41J128MJT125_EMIF_TIM1 0x0888A39B
#define DDR3_EMIF_TIM2 0x26337FDA #define MT41J128MJT125_EMIF_TIM2 0x26337FDA
#define DDR3_EMIF_TIM3 0x501F830F #define MT41J128MJT125_EMIF_TIM3 0x501F830F
#define DDR3_EMIF_SDCFG 0x61C04AB2 #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
#define DDR3_EMIF_SDREF 0x0000093B #define MT41J128MJT125_EMIF_SDREF 0x0000093B
#define DDR3_ZQ_CFG 0x50074BE4 #define MT41J128MJT125_ZQ_CFG 0x50074BE4
#define DDR3_DLL_LOCK_DIFF 0x1 #define MT41J128MJT125_DLL_LOCK_DIFF 0x1
#define DDR3_RATIO 0x40 #define MT41J128MJT125_RATIO 0x40
#define DDR3_INVERT_CLKOUT 0x1 #define MT41J128MJT125_INVERT_CLKOUT 0x1
#define DDR3_RD_DQS 0x3B #define MT41J128MJT125_RD_DQS 0x3B
#define DDR3_WR_DQS 0x85 #define MT41J128MJT125_WR_DQS 0x85
#define DDR3_PHY_WR_DATA 0xC1 #define MT41J128MJT125_PHY_WR_DATA 0xC1
#define DDR3_PHY_FIFO_WE 0x100 #define MT41J128MJT125_PHY_FIFO_WE 0x100
#define DDR3_IOCTRL_VALUE 0x18B #define MT41J128MJT125_IOCTRL_VALUE 0x18B
/** /**
* Configure SDRAM * Configure SDRAM

112
board/ti/am335x/board.c
View file

@ -133,75 +133,87 @@ static void rtc32k_enable(void)
} }
static const struct ddr_data ddr2_data = { static const struct ddr_data ddr2_data = {
.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)), (MT47H128M16RT25E_RD_DQS<<20) |
.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) (MT47H128M16RT25E_RD_DQS<<10) |
|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)), (MT47H128M16RT25E_RD_DQS<<0)),
.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)), (MT47H128M16RT25E_WR_DQS<<20) |
.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) (MT47H128M16RT25E_WR_DQS<<10) |
|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)), (MT47H128M16RT25E_WR_DQS<<0)),
.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)), (MT47H128M16RT25E_PHY_WRLVL<<20) |
.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) (MT47H128M16RT25E_PHY_WRLVL<<10) |
|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)), (MT47H128M16RT25E_PHY_WRLVL<<0)),
.datauserank0delay = DDR2_PHY_RANK0_DELAY, .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
(MT47H128M16RT25E_PHY_GATELVL<<20) |
(MT47H128M16RT25E_PHY_GATELVL<<10) |
(MT47H128M16RT25E_PHY_GATELVL<<0)),
.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
(MT47H128M16RT25E_PHY_FIFO_WE<<20) |
(MT47H128M16RT25E_PHY_FIFO_WE<<10) |
(MT47H128M16RT25E_PHY_FIFO_WE<<0)),
.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
(MT47H128M16RT25E_PHY_WR_DATA<<20) |
(MT47H128M16RT25E_PHY_WR_DATA<<10) |
(MT47H128M16RT25E_PHY_WR_DATA<<0)),
.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
.datadldiff0 = PHY_DLL_LOCK_DIFF, .datadldiff0 = PHY_DLL_LOCK_DIFF,
}; };
static const struct cmd_control ddr2_cmd_ctrl_data = { static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = DDR2_RATIO, .cmd0csratio = MT47H128M16RT25E_RATIO,
.cmd0dldiff = DDR2_DLL_LOCK_DIFF, .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
.cmd0iclkout = DDR2_INVERT_CLKOUT, .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd1csratio = DDR2_RATIO, .cmd1csratio = MT47H128M16RT25E_RATIO,
.cmd1dldiff = DDR2_DLL_LOCK_DIFF, .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
.cmd1iclkout = DDR2_INVERT_CLKOUT, .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd2csratio = DDR2_RATIO, .cmd2csratio = MT47H128M16RT25E_RATIO,
.cmd2dldiff = DDR2_DLL_LOCK_DIFF, .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
.cmd2iclkout = DDR2_INVERT_CLKOUT, .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
}; };
static const struct emif_regs ddr2_emif_reg_data = { static const struct emif_regs ddr2_emif_reg_data = {
.sdram_config = DDR2_EMIF_SDCFG, .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
.ref_ctrl = DDR2_EMIF_SDREF, .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
.sdram_tim1 = DDR2_EMIF_TIM1, .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
.sdram_tim2 = DDR2_EMIF_TIM2, .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
.sdram_tim3 = DDR2_EMIF_TIM3, .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
.emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY, .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
}; };
static const struct ddr_data ddr3_data = { static const struct ddr_data ddr3_data = {
.datardsratio0 = DDR3_RD_DQS, .datardsratio0 = MT41J128MJT125_RD_DQS,
.datawdsratio0 = DDR3_WR_DQS, .datawdsratio0 = MT41J128MJT125_WR_DQS,
.datafwsratio0 = DDR3_PHY_FIFO_WE, .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
.datawrsratio0 = DDR3_PHY_WR_DATA, .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
.datadldiff0 = PHY_DLL_LOCK_DIFF, .datadldiff0 = PHY_DLL_LOCK_DIFF,
}; };
static const struct cmd_control ddr3_cmd_ctrl_data = { static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = DDR3_RATIO, .cmd0csratio = MT41J128MJT125_RATIO,
.cmd0dldiff = DDR3_DLL_LOCK_DIFF, .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd0iclkout = DDR3_INVERT_CLKOUT, .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
.cmd1csratio = DDR3_RATIO, .cmd1csratio = MT41J128MJT125_RATIO,
.cmd1dldiff = DDR3_DLL_LOCK_DIFF, .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd1iclkout = DDR3_INVERT_CLKOUT, .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
.cmd2csratio = DDR3_RATIO, .cmd2csratio = MT41J128MJT125_RATIO,
.cmd2dldiff = DDR3_DLL_LOCK_DIFF, .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd2iclkout = DDR3_INVERT_CLKOUT, .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
}; };
static struct emif_regs ddr3_emif_reg_data = { static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = DDR3_EMIF_SDCFG, .sdram_config = MT41J128MJT125_EMIF_SDCFG,
.ref_ctrl = DDR3_EMIF_SDREF, .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
.sdram_tim1 = DDR3_EMIF_TIM1, .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
.sdram_tim2 = DDR3_EMIF_TIM2, .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
.sdram_tim3 = DDR3_EMIF_TIM3, .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
.zq_config = DDR3_ZQ_CFG, .zq_config = MT41J128MJT125_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY, .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
}; };
#endif #endif
@ -265,10 +277,10 @@ void s_init(void)
} }
if (board_is_evm_sk() || board_is_bone_lt()) if (board_is_evm_sk() || board_is_bone_lt())
config_ddr(303, DDR3_IOCTRL_VALUE, &ddr3_data, config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data); &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
else else
config_ddr(266, DDR2_IOCTRL_VALUE, &ddr2_data, config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data); &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
#endif #endif
} }