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am33xx/ddr_defs.h: rename DDR2/DDR3 defines to their actual part numbers
So other parts can be added. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
This commit is contained in:
Peter Korsgaard
Tom Rini
parent
c00f69dbcd
commit
c7d35bef25
2 changed files with 94 additions and 82 deletions
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@ -30,40 +30,40 @@
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#define DDR_CKE_CTRL_NORMAL 0x1
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/* Micron MT47H128M16RT-25E */
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#define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */
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#define DDR2_EMIF_TIM1 0x0666B3C9
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#define DDR2_EMIF_TIM2 0x243631CA
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#define DDR2_EMIF_TIM3 0x0000033F
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#define DDR2_EMIF_SDCFG 0x41805332
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#define DDR2_EMIF_SDREF 0x0000081a
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#define DDR2_DLL_LOCK_DIFF 0x0
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#define DDR2_RATIO 0x80
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#define DDR2_INVERT_CLKOUT 0x00
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#define DDR2_RD_DQS 0x12
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#define DDR2_WR_DQS 0x00
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#define DDR2_PHY_WRLVL 0x00
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#define DDR2_PHY_GATELVL 0x00
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#define DDR2_PHY_WR_DATA 0x40
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#define DDR2_PHY_FIFO_WE 0x80
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#define DDR2_PHY_RANK0_DELAY 0x1
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#define DDR2_IOCTRL_VALUE 0x18B
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#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
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#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
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#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
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#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
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#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
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#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
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#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0
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#define MT47H128M16RT25E_RATIO 0x80
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#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
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#define MT47H128M16RT25E_RD_DQS 0x12
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#define MT47H128M16RT25E_WR_DQS 0x00
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#define MT47H128M16RT25E_PHY_WRLVL 0x00
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#define MT47H128M16RT25E_PHY_GATELVL 0x00
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#define MT47H128M16RT25E_PHY_WR_DATA 0x40
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#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
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#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1
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#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
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/* Micron MT41J128M16JT-125 */
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#define DDR3_EMIF_READ_LATENCY 0x06
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#define DDR3_EMIF_TIM1 0x0888A39B
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#define DDR3_EMIF_TIM2 0x26337FDA
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#define DDR3_EMIF_TIM3 0x501F830F
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#define DDR3_EMIF_SDCFG 0x61C04AB2
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#define DDR3_EMIF_SDREF 0x0000093B
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#define DDR3_ZQ_CFG 0x50074BE4
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#define DDR3_DLL_LOCK_DIFF 0x1
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#define DDR3_RATIO 0x40
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#define DDR3_INVERT_CLKOUT 0x1
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#define DDR3_RD_DQS 0x3B
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#define DDR3_WR_DQS 0x85
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#define DDR3_PHY_WR_DATA 0xC1
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#define DDR3_PHY_FIFO_WE 0x100
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#define DDR3_IOCTRL_VALUE 0x18B
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#define MT41J128MJT125_EMIF_READ_LATENCY 0x06
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#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
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#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
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#define MT41J128MJT125_EMIF_TIM3 0x501F830F
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#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
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#define MT41J128MJT125_EMIF_SDREF 0x0000093B
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#define MT41J128MJT125_ZQ_CFG 0x50074BE4
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#define MT41J128MJT125_DLL_LOCK_DIFF 0x1
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#define MT41J128MJT125_RATIO 0x40
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#define MT41J128MJT125_INVERT_CLKOUT 0x1
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#define MT41J128MJT125_RD_DQS 0x3B
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#define MT41J128MJT125_WR_DQS 0x85
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#define MT41J128MJT125_PHY_WR_DATA 0xC1
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#define MT41J128MJT125_PHY_FIFO_WE 0x100
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#define MT41J128MJT125_IOCTRL_VALUE 0x18B
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/**
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* Configure SDRAM
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@ -133,75 +133,87 @@ static void rtc32k_enable(void)
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}
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static const struct ddr_data ddr2_data = {
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.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
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|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
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.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
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|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
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.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
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|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
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.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
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|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
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.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
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|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
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.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
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|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
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.datauserank0delay = DDR2_PHY_RANK0_DELAY,
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.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
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(MT47H128M16RT25E_RD_DQS<<20) |
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(MT47H128M16RT25E_RD_DQS<<10) |
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(MT47H128M16RT25E_RD_DQS<<0)),
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.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
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(MT47H128M16RT25E_WR_DQS<<20) |
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(MT47H128M16RT25E_WR_DQS<<10) |
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(MT47H128M16RT25E_WR_DQS<<0)),
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.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
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(MT47H128M16RT25E_PHY_WRLVL<<20) |
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(MT47H128M16RT25E_PHY_WRLVL<<10) |
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(MT47H128M16RT25E_PHY_WRLVL<<0)),
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.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
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(MT47H128M16RT25E_PHY_GATELVL<<20) |
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(MT47H128M16RT25E_PHY_GATELVL<<10) |
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(MT47H128M16RT25E_PHY_GATELVL<<0)),
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.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
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(MT47H128M16RT25E_PHY_FIFO_WE<<20) |
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(MT47H128M16RT25E_PHY_FIFO_WE<<10) |
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(MT47H128M16RT25E_PHY_FIFO_WE<<0)),
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.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
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(MT47H128M16RT25E_PHY_WR_DATA<<20) |
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(MT47H128M16RT25E_PHY_WR_DATA<<10) |
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(MT47H128M16RT25E_PHY_WR_DATA<<0)),
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.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
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.datadldiff0 = PHY_DLL_LOCK_DIFF,
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};
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static const struct cmd_control ddr2_cmd_ctrl_data = {
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.cmd0csratio = DDR2_RATIO,
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.cmd0dldiff = DDR2_DLL_LOCK_DIFF,
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.cmd0iclkout = DDR2_INVERT_CLKOUT,
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.cmd0csratio = MT47H128M16RT25E_RATIO,
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.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
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.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
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.cmd1csratio = DDR2_RATIO,
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.cmd1dldiff = DDR2_DLL_LOCK_DIFF,
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.cmd1iclkout = DDR2_INVERT_CLKOUT,
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.cmd1csratio = MT47H128M16RT25E_RATIO,
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.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
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.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
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.cmd2csratio = DDR2_RATIO,
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.cmd2dldiff = DDR2_DLL_LOCK_DIFF,
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.cmd2iclkout = DDR2_INVERT_CLKOUT,
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.cmd2csratio = MT47H128M16RT25E_RATIO,
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.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
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.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
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};
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static const struct emif_regs ddr2_emif_reg_data = {
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.sdram_config = DDR2_EMIF_SDCFG,
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.ref_ctrl = DDR2_EMIF_SDREF,
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.sdram_tim1 = DDR2_EMIF_TIM1,
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.sdram_tim2 = DDR2_EMIF_TIM2,
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.sdram_tim3 = DDR2_EMIF_TIM3,
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.emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
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.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
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.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
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.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
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.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
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.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
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.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
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};
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = DDR3_RD_DQS,
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.datawdsratio0 = DDR3_WR_DQS,
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.datafwsratio0 = DDR3_PHY_FIFO_WE,
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.datawrsratio0 = DDR3_PHY_WR_DATA,
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.datardsratio0 = MT41J128MJT125_RD_DQS,
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.datawdsratio0 = MT41J128MJT125_WR_DQS,
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.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
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.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
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.datadldiff0 = PHY_DLL_LOCK_DIFF,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = DDR3_RATIO,
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.cmd0dldiff = DDR3_DLL_LOCK_DIFF,
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.cmd0iclkout = DDR3_INVERT_CLKOUT,
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.cmd0csratio = MT41J128MJT125_RATIO,
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.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
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.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
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.cmd1csratio = DDR3_RATIO,
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.cmd1dldiff = DDR3_DLL_LOCK_DIFF,
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.cmd1iclkout = DDR3_INVERT_CLKOUT,
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.cmd1csratio = MT41J128MJT125_RATIO,
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.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
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.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
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.cmd2csratio = DDR3_RATIO,
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.cmd2dldiff = DDR3_DLL_LOCK_DIFF,
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.cmd2iclkout = DDR3_INVERT_CLKOUT,
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.cmd2csratio = MT41J128MJT125_RATIO,
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.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
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.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = DDR3_EMIF_SDCFG,
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.ref_ctrl = DDR3_EMIF_SDREF,
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.sdram_tim1 = DDR3_EMIF_TIM1,
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.sdram_tim2 = DDR3_EMIF_TIM2,
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.sdram_tim3 = DDR3_EMIF_TIM3,
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.zq_config = DDR3_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
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.sdram_config = MT41J128MJT125_EMIF_SDCFG,
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.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
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.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
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.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
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.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
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.zq_config = MT41J128MJT125_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
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};
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#endif
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@ -265,10 +277,10 @@ void s_init(void)
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}
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if (board_is_evm_sk() || board_is_bone_lt())
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config_ddr(303, DDR3_IOCTRL_VALUE, &ddr3_data,
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config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
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&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
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else
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config_ddr(266, DDR2_IOCTRL_VALUE, &ddr2_data,
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config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
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&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
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#endif
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}
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