mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-19 05:31:32 +00:00
Merge tag 'mmc-2019-5-3' of https://github.com/MrVan/u-boot
This commit is contained in:
commit
c9baea6d0e
4 changed files with 234 additions and 55 deletions
|
@ -391,6 +391,20 @@ config MMC_SDHCI_SDMA
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This enables support for the SDMA (Single Operation DMA) defined
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This enables support for the SDMA (Single Operation DMA) defined
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in the SD Host Controller Standard Specification Version 1.00 .
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in the SD Host Controller Standard Specification Version 1.00 .
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config MMC_SDHCI_ADMA
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bool "Support SDHCI ADMA2"
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depends on MMC_SDHCI
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help
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This enables support for the ADMA (Advanced DMA) defined
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in the SD Host Controller Standard Specification Version 3.00
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config SPL_MMC_SDHCI_ADMA
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bool "Support SDHCI ADMA2 in SPL"
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depends on MMC_SDHCI
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help
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This enables support for the ADMA (Advanced DMA) defined
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in the SD Host Controller Standard Specification Version 3.00 in SPL.
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config MMC_SDHCI_ATMEL
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config MMC_SDHCI_ATMEL
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bool "Atmel SDHCI controller support"
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bool "Atmel SDHCI controller support"
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depends on ARCH_AT91
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depends on ARCH_AT91
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@ -297,6 +297,13 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
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printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
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printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
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return -ETIMEDOUT;
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return -ETIMEDOUT;
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}
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}
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} else {
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#ifdef CONFIG_DM_GPIO
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if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
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printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
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return -ETIMEDOUT;
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}
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#endif
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}
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}
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esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
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esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
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@ -614,18 +621,31 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
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#else
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#else
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int pre_div = 2;
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int pre_div = 2;
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#endif
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#endif
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int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
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int sdhc_clk = priv->sdhc_clk;
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int sdhc_clk = priv->sdhc_clk;
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uint clk;
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uint clk;
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/*
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* For ddr mode, usdhc need to enable DDR mode first, after select
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* this DDR mode, usdhc will automatically divide the usdhc clock
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*/
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if (mmc->ddr_mode) {
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writel(readl(®s->mixctrl) | MIX_CTRL_DDREN, ®s->mixctrl);
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sdhc_clk >>= 1;
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}
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if (clock < mmc->cfg->f_min)
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if (clock < mmc->cfg->f_min)
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clock = mmc->cfg->f_min;
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clock = mmc->cfg->f_min;
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while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
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if (sdhc_clk / 16 > clock) {
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pre_div *= 2;
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for (; pre_div < 256; pre_div *= 2)
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if ((sdhc_clk / pre_div) <= (clock * 16))
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break;
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} else
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pre_div = 1;
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while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
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for (div = 1; div <= 16; div++)
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div++;
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if ((sdhc_clk / (div * pre_div)) <= clock)
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break;
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pre_div >>= 1;
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pre_div >>= 1;
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div -= 1;
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div -= 1;
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@ -1489,14 +1509,15 @@ static int fsl_esdhc_probe(struct udevice *dev)
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#endif
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#endif
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}
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}
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priv->wp_enable = 1;
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if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
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priv->wp_enable = 1;
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#ifdef CONFIG_DM_GPIO
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} else {
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ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
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GPIOD_IS_IN);
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if (ret)
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priv->wp_enable = 0;
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priv->wp_enable = 0;
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#ifdef CONFIG_DM_GPIO
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gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
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GPIOD_IS_IN);
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#endif
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#endif
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}
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priv->vs18_enable = 0;
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priv->vs18_enable = 0;
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@ -67,17 +67,123 @@ static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
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}
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}
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}
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}
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static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
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#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
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unsigned int start_addr)
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static void sdhci_adma_desc(struct sdhci_host *host, char *buf, u16 len,
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bool end)
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{
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struct sdhci_adma_desc *desc;
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u8 attr;
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desc = &host->adma_desc_table[host->desc_slot];
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attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
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if (!end)
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host->desc_slot++;
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else
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attr |= ADMA_DESC_ATTR_END;
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desc->attr = attr;
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desc->len = len;
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desc->reserved = 0;
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desc->addr_lo = (dma_addr_t)buf;
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#ifdef CONFIG_DMA_ADDR_T_64BIT
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desc->addr_hi = (u64)buf >> 32;
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#endif
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}
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static void sdhci_prepare_adma_table(struct sdhci_host *host,
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struct mmc_data *data)
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{
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uint trans_bytes = data->blocksize * data->blocks;
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uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
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int i = desc_count;
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char *buf;
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host->desc_slot = 0;
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if (data->flags & MMC_DATA_READ)
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buf = data->dest;
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else
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buf = (char *)data->src;
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while (--i) {
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sdhci_adma_desc(host, buf, ADMA_MAX_LEN, false);
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buf += ADMA_MAX_LEN;
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trans_bytes -= ADMA_MAX_LEN;
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}
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sdhci_adma_desc(host, buf, trans_bytes, true);
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flush_cache((dma_addr_t)host->adma_desc_table,
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ROUND(desc_count * sizeof(struct sdhci_adma_desc),
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ARCH_DMA_MINALIGN));
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}
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#elif defined(CONFIG_MMC_SDHCI_SDMA)
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static void sdhci_prepare_adma_table(struct sdhci_host *host,
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struct mmc_data *data)
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{}
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#endif
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#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
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static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
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int *is_aligned, int trans_bytes)
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{
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{
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unsigned int stat, rdy, mask, timeout, block = 0;
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bool transfer_done = false;
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#ifdef CONFIG_MMC_SDHCI_SDMA
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unsigned char ctrl;
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unsigned char ctrl;
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if (data->flags == MMC_DATA_READ)
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host->start_addr = (dma_addr_t)data->dest;
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else
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host->start_addr = (dma_addr_t)data->src;
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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ctrl &= ~SDHCI_CTRL_DMA_MASK;
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ctrl &= ~SDHCI_CTRL_DMA_MASK;
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if (host->flags & USE_ADMA64)
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ctrl |= SDHCI_CTRL_ADMA64;
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else if (host->flags & USE_ADMA)
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ctrl |= SDHCI_CTRL_ADMA32;
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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if (host->flags & USE_SDMA) {
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if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
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(host->start_addr & 0x7) != 0x0) {
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*is_aligned = 0;
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host->start_addr = (unsigned long)aligned_buffer;
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if (data->flags != MMC_DATA_READ)
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memcpy(aligned_buffer, data->src, trans_bytes);
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}
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#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
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/*
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* Always use this bounce-buffer when
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* CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
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*/
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*is_aligned = 0;
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host->start_addr = (unsigned long)aligned_buffer;
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if (data->flags != MMC_DATA_READ)
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memcpy(aligned_buffer, data->src, trans_bytes);
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#endif
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#endif
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sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS);
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} else if (host->flags & (USE_ADMA | USE_ADMA64)) {
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sdhci_prepare_adma_table(host, data);
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sdhci_writel(host, (u32)host->adma_addr, SDHCI_ADMA_ADDRESS);
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if (host->flags & USE_ADMA64)
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sdhci_writel(host, (u64)host->adma_addr >> 32,
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SDHCI_ADMA_ADDRESS_HI);
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}
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flush_cache(host->start_addr, ROUND(trans_bytes, ARCH_DMA_MINALIGN));
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}
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#else
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static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
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int *is_aligned, int trans_bytes)
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|
{}
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|
#endif
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static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
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|
{
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|
dma_addr_t start_addr = host->start_addr;
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|
unsigned int stat, rdy, mask, timeout, block = 0;
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|
bool transfer_done = false;
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|
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timeout = 1000000;
|
timeout = 1000000;
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rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
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rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
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|
@ -104,14 +210,17 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
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continue;
|
continue;
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}
|
}
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}
|
}
|
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#ifdef CONFIG_MMC_SDHCI_SDMA
|
if ((host->flags & USE_DMA) && !transfer_done &&
|
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if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
|
(stat & SDHCI_INT_DMA_END)) {
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sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
|
sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
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start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
|
if (host->flags & USE_SDMA) {
|
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start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
|
start_addr &=
|
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sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
|
~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
|
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|
start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
|
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|
sdhci_writel(host, start_addr,
|
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|
SDHCI_DMA_ADDRESS);
|
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|
}
|
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}
|
}
|
||||||
#endif
|
|
||||||
if (timeout-- > 0)
|
if (timeout-- > 0)
|
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udelay(10);
|
udelay(10);
|
||||||
else {
|
else {
|
||||||
|
@ -149,10 +258,11 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
int trans_bytes = 0, is_aligned = 1;
|
int trans_bytes = 0, is_aligned = 1;
|
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u32 mask, flags, mode;
|
u32 mask, flags, mode;
|
||||||
unsigned int time = 0, start_addr = 0;
|
unsigned int time = 0;
|
||||||
int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
|
int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
|
||||||
ulong start = get_timer(0);
|
ulong start = get_timer(0);
|
||||||
|
|
||||||
|
host->start_addr = 0;
|
||||||
/* Timeout unit - ms */
|
/* Timeout unit - ms */
|
||||||
static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
|
static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
|
||||||
|
|
||||||
|
@ -218,33 +328,11 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
|
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if (data->flags == MMC_DATA_READ)
|
if (data->flags == MMC_DATA_READ)
|
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mode |= SDHCI_TRNS_READ;
|
mode |= SDHCI_TRNS_READ;
|
||||||
|
|
||||||
#ifdef CONFIG_MMC_SDHCI_SDMA
|
if (host->flags & USE_DMA) {
|
||||||
if (data->flags == MMC_DATA_READ)
|
mode |= SDHCI_TRNS_DMA;
|
||||||
start_addr = (unsigned long)data->dest;
|
sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
|
||||||
else
|
|
||||||
start_addr = (unsigned long)data->src;
|
|
||||||
if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
|
|
||||||
(start_addr & 0x7) != 0x0) {
|
|
||||||
is_aligned = 0;
|
|
||||||
start_addr = (unsigned long)aligned_buffer;
|
|
||||||
if (data->flags != MMC_DATA_READ)
|
|
||||||
memcpy(aligned_buffer, data->src, trans_bytes);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
|
|
||||||
/*
|
|
||||||
* Always use this bounce-buffer when
|
|
||||||
* CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
|
|
||||||
*/
|
|
||||||
is_aligned = 0;
|
|
||||||
start_addr = (unsigned long)aligned_buffer;
|
|
||||||
if (data->flags != MMC_DATA_READ)
|
|
||||||
memcpy(aligned_buffer, data->src, trans_bytes);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
|
|
||||||
mode |= SDHCI_TRNS_DMA;
|
|
||||||
#endif
|
|
||||||
sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
|
sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
|
||||||
data->blocksize),
|
data->blocksize),
|
||||||
SDHCI_BLOCK_SIZE);
|
SDHCI_BLOCK_SIZE);
|
||||||
|
@ -255,12 +343,6 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
|
||||||
}
|
}
|
||||||
|
|
||||||
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
|
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
|
||||||
#ifdef CONFIG_MMC_SDHCI_SDMA
|
|
||||||
if (data) {
|
|
||||||
trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
|
|
||||||
flush_cache(start_addr, trans_bytes);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
|
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
|
||||||
start = get_timer(0);
|
start = get_timer(0);
|
||||||
do {
|
do {
|
||||||
|
@ -286,7 +368,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
|
||||||
ret = -1;
|
ret = -1;
|
||||||
|
|
||||||
if (!ret && data)
|
if (!ret && data)
|
||||||
ret = sdhci_transfer_data(host, data, start_addr);
|
ret = sdhci_transfer_data(host, data);
|
||||||
|
|
||||||
if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
|
if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
|
||||||
udelay(1000);
|
udelay(1000);
|
||||||
|
@ -570,6 +652,24 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
|
||||||
__func__);
|
__func__);
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
host->flags |= USE_SDMA;
|
||||||
|
#endif
|
||||||
|
#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
|
||||||
|
if (!(caps & SDHCI_CAN_DO_ADMA2)) {
|
||||||
|
printf("%s: Your controller doesn't support SDMA!!\n",
|
||||||
|
__func__);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
host->adma_desc_table = (struct sdhci_adma_desc *)
|
||||||
|
memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
|
||||||
|
|
||||||
|
host->adma_addr = (dma_addr_t)host->adma_desc_table;
|
||||||
|
#ifdef CONFIG_DMA_ADDR_T_64BIT
|
||||||
|
host->flags |= USE_ADMA64;
|
||||||
|
#else
|
||||||
|
host->flags |= USE_ADMA;
|
||||||
|
#endif
|
||||||
#endif
|
#endif
|
||||||
if (host->quirks & SDHCI_QUIRK_REG32_RW)
|
if (host->quirks & SDHCI_QUIRK_REG32_RW)
|
||||||
host->version =
|
host->version =
|
||||||
|
|
|
@ -186,6 +186,7 @@
|
||||||
/* 55-57 reserved */
|
/* 55-57 reserved */
|
||||||
|
|
||||||
#define SDHCI_ADMA_ADDRESS 0x58
|
#define SDHCI_ADMA_ADDRESS 0x58
|
||||||
|
#define SDHCI_ADMA_ADDRESS_HI 0x5c
|
||||||
|
|
||||||
/* 60-FB reserved */
|
/* 60-FB reserved */
|
||||||
|
|
||||||
|
@ -252,6 +253,38 @@ struct sdhci_ops {
|
||||||
void (*set_delay)(struct sdhci_host *host);
|
void (*set_delay)(struct sdhci_host *host);
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
|
||||||
|
#define ADMA_MAX_LEN 65532
|
||||||
|
#ifdef CONFIG_DMA_ADDR_T_64BIT
|
||||||
|
#define ADMA_DESC_LEN 16
|
||||||
|
#else
|
||||||
|
#define ADMA_DESC_LEN 8
|
||||||
|
#endif
|
||||||
|
#define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
|
||||||
|
MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN
|
||||||
|
|
||||||
|
#define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)
|
||||||
|
|
||||||
|
/* Decriptor table defines */
|
||||||
|
#define ADMA_DESC_ATTR_VALID BIT(0)
|
||||||
|
#define ADMA_DESC_ATTR_END BIT(1)
|
||||||
|
#define ADMA_DESC_ATTR_INT BIT(2)
|
||||||
|
#define ADMA_DESC_ATTR_ACT1 BIT(4)
|
||||||
|
#define ADMA_DESC_ATTR_ACT2 BIT(5)
|
||||||
|
|
||||||
|
#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
|
||||||
|
#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
|
||||||
|
|
||||||
|
struct sdhci_adma_desc {
|
||||||
|
u8 attr;
|
||||||
|
u8 reserved;
|
||||||
|
u16 len;
|
||||||
|
u32 addr_lo;
|
||||||
|
#ifdef CONFIG_DMA_ADDR_T_64BIT
|
||||||
|
u32 addr_hi;
|
||||||
|
#endif
|
||||||
|
} __packed;
|
||||||
|
#endif
|
||||||
struct sdhci_host {
|
struct sdhci_host {
|
||||||
const char *name;
|
const char *name;
|
||||||
void *ioaddr;
|
void *ioaddr;
|
||||||
|
@ -272,6 +305,17 @@ struct sdhci_host {
|
||||||
uint voltages;
|
uint voltages;
|
||||||
|
|
||||||
struct mmc_config cfg;
|
struct mmc_config cfg;
|
||||||
|
dma_addr_t start_addr;
|
||||||
|
int flags;
|
||||||
|
#define USE_SDMA (0x1 << 0)
|
||||||
|
#define USE_ADMA (0x1 << 1)
|
||||||
|
#define USE_ADMA64 (0x1 << 2)
|
||||||
|
#define USE_DMA (USE_SDMA | USE_ADMA | USE_ADMA64)
|
||||||
|
dma_addr_t adma_addr;
|
||||||
|
#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
|
||||||
|
struct sdhci_adma_desc *adma_desc_table;
|
||||||
|
uint desc_slot;
|
||||||
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
|
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
|
||||||
|
|
Loading…
Add table
Reference in a new issue