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fpga: zynqpl: Flush dcache only for non-bitstream data

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In case of aes decryption destination address range must be flushed
before transferring decrypted data to destination.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
T Karthik Reddy 2019-03-12 20:20:23 +05:30 • committed by Michal Simek
parent c64afba2fb
commit ca0c0e07ad
1 changed files with 3 additions and 2 deletions
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5
drivers/fpga/zynqpl.c
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@ -548,8 +548,9 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
* Flush destination address range only if image is not * Flush destination address range only if image is not
* bitstream. * bitstream.
*/ */
flush_dcache_range((u32)dstaddr, (u32)dstaddr + if (bstype == BIT_NONE && dstaddr != 0xFFFFFFFF)
roundup(dstlen << 2, ARCH_DMA_MINALIGN)); flush_dcache_range((u32)dstaddr, (u32)dstaddr +
roundup(dstlen << 2, ARCH_DMA_MINALIGN));
if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen)) if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
return FPGA_FAIL; return FPGA_FAIL;