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fpga: zynqpl: Flush dcache only for non-bitstream data
In case of aes decryption destination address range must be flushed before transferring decrypted data to destination. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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1 changed files with 3 additions and 2 deletions
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@ -548,8 +548,9 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
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* Flush destination address range only if image is not
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* Flush destination address range only if image is not
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* bitstream.
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* bitstream.
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*/
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*/
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flush_dcache_range((u32)dstaddr, (u32)dstaddr +
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if (bstype == BIT_NONE && dstaddr != 0xFFFFFFFF)
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roundup(dstlen << 2, ARCH_DMA_MINALIGN));
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flush_dcache_range((u32)dstaddr, (u32)dstaddr +
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roundup(dstlen << 2, ARCH_DMA_MINALIGN));
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if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
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if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
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return FPGA_FAIL;
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return FPGA_FAIL;
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