mirror of
https://github.com/Fishwaldo/u-boot.git
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powerpc/85xx: Add support for booting from NAND on MPC8572DS
Mimic support that exists on MPC8536DS on the MPC8572DS to allow booting from NAND. Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
16dad75975
commit
cb14e93b55
6 changed files with 337 additions and 18 deletions
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@ -1,5 +1,5 @@
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#
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# Copyright 2007-2008 Freescale Semiconductor, Inc.
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# Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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@ -23,4 +23,10 @@
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#
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# mpc8572ds board
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#
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ifndef NAND_SPL
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ifeq ($(CONFIG_NAND), y)
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LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
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endif
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endif
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RESET_VECTOR_ADDRESS = 0xeffffffc
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@ -1,5 +1,5 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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* Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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@ -85,6 +85,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
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SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 8, BOOKE_PAGESZ_4K, 1),
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#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
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/* *I*G - L2SRAM */
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR,
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CONFIG_SYS_INIT_L2_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 9, BOOKE_PAGESZ_256K, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
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CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 10, BOOKE_PAGESZ_256K, 1),
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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@ -473,6 +473,7 @@ MPC8569MDS_ATM powerpc mpc85xx mpc8569mds freesca
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MPC8569MDS_NAND powerpc mpc85xx mpc8569mds freescale - MPC8569MDS:NAND
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MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS
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MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT
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MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND
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P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011
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P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,NAND
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P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,SDCARD
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@ -33,6 +33,25 @@
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#define CONFIG_PHYS_64BIT
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#endif
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#ifdef CONFIG_NAND
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#define CONFIG_NAND_U_BOOT
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#define CONFIG_RAMBOOT_NAND
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#ifdef CONFIG_NAND_SPL
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#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
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#else
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#define CONFIG_SYS_TEXT_BASE 0xf8f82000
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#endif /* CONFIG_NAND_SPL */
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#endif
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xeff80000
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#endif
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#ifndef CONFIG_SYS_MONITOR_BASE
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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@ -41,10 +60,6 @@
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#define CONFIG_MPC8572DS 1
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#define CONFIG_MP 1 /* support multiple processors */
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xeff80000
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#endif
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#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
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#define CONFIG_PCI 1 /* Enable PCI/PCIE */
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#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
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@ -80,11 +95,22 @@
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#define CONFIG_SYS_MEMTEST_END 0x7fffffff
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#define CONFIG_PANIC_HANG /* do not reset board on panic */
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/*
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* Config the L2 Cache as L2 SRAM
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*/
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
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#else
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#endif
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#define CONFIG_SYS_L2_SIZE (512 << 10)
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
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@ -93,6 +119,12 @@
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#endif
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
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#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
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#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
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#else
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#endif
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/* DDR Setup */
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_FSL_DDR2
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@ -177,8 +209,11 @@
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#endif
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#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
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#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
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#define CONFIG_FLASH_BR_PRELIM \
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(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
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| BR_PS_16 | BR_V)
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#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
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#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
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#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
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@ -193,7 +228,12 @@
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#if defined(CONFIG_RAMBOOT_NAND)
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#define CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#else
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#undef CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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@ -246,6 +286,8 @@
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#define PIXIS_VWATCH 0x24 /* Watchdog Register */
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#define PIXIS_LED 0x25 /* LED Register */
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#define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
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/* old pixis referenced names */
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#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
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#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
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@ -277,12 +319,22 @@
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
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#ifndef CONFIG_NAND_SPL
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#define CONFIG_SYS_NAND_BASE 0xffa00000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
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#else
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#endif
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#else
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#define CONFIG_SYS_NAND_BASE 0xfff00000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
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#else
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#endif
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#endif
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
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CONFIG_SYS_NAND_BASE + 0x40000, \
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CONFIG_SYS_NAND_BASE + 0x80000,\
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@ -293,6 +345,17 @@
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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/* NAND boot: 4K NAND loader config */
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#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
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#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
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#define CONFIG_SYS_NAND_U_BOOT_START \
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(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
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#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
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#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
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/* NAND flash config */
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#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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@ -308,9 +371,17 @@
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| OR_FCM_TRLX \
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| OR_FCM_EHTR)
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#ifdef CONFIG_RAMBOOT_NAND
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#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
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#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
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#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
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#else
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#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
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#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
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#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
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#endif
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#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8 bit */ \
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#ifdef CONFIG_NAND_SPL
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#define CONFIG_NS16550_MIN_FUNCTIONS
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#endif
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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@ -546,14 +620,25 @@
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/*
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* Environment
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
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#define CONFIG_ENV_ADDR 0xfff80000
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#else
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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#if defined(CONFIG_SYS_RAMBOOT)
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#if defined(CONFIG_RAMBOOT_NAND)
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#define CONFIG_ENV_IS_IN_NAND 1
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_OFFSET ((512 * 1024)\
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+ CONFIG_SYS_NAND_BLOCK_SIZE)
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#endif
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#else
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#define CONFIG_ENV_IS_IN_FLASH 1
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#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
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#define CONFIG_ENV_ADDR 0xfff80000
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#else
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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#endif
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
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#endif
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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133
nand_spl/board/freescale/mpc8572ds/Makefile
Normal file
133
nand_spl/board/freescale/mpc8572ds/Makefile
Normal file
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@ -0,0 +1,133 @@
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#
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# (C) Copyright 2007
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# Copyright 2009-2010 Freescale Semiconductor, Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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NAND_SPL := y
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CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
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PAD_TO := 0xfff01000
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include $(TOPDIR)/config.mk
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LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
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LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS)
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AFLAGS += -DCONFIG_NAND_SPL
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CFLAGS += -DCONFIG_NAND_SPL
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SOBJS = start.o resetvec.o
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COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
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nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
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SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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__OBJS := $(SOBJS) $(COBJS)
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LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
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nandobj := $(OBJTREE)/nand_spl/
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ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
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all: $(obj).depend $(ALL)
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$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
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$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
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$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
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$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
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$(nandobj)u-boot-spl: $(OBJS)
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cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
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-Map $(nandobj)u-boot-spl.map \
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-o $(nandobj)u-boot-spl
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# create symbolic links for common files
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$(obj)cache.c:
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@rm -f $(obj)cache.c
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ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
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$(obj)cpu_init_early.c:
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@rm -f $(obj)cpu_init_early.c
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ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
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$(obj)cpu_init_nand.c:
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@rm -f $(obj)cpu_init_nand.c
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ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
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$(obj)fsl_law.c:
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@rm -f $(obj)fsl_law.c
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ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
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$(obj)law.c:
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@rm -f $(obj)law.c
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ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
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$(obj)nand_boot_fsl_elbc.c:
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@rm -f $(obj)nand_boot_fsl_elbc.c
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ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
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$(obj)nand_boot_fsl_elbc.c
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$(obj)ns16550.c:
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@rm -f $(obj)ns16550.c
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ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
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$(obj)resetvec.S:
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@rm -f $(obj)resetvec.S
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ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
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$(obj)fixed_ivor.S:
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@rm -f $(obj)fixed_ivor.S
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ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
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$(obj)start.S: $(obj)fixed_ivor.S
|
||||
@rm -f $(obj)start.S
|
||||
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
|
||||
|
||||
$(obj)tlb.c:
|
||||
@rm -f $(obj)tlb.c
|
||||
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
|
||||
|
||||
$(obj)tlb_table.c:
|
||||
@rm -f $(obj)tlb_table.c
|
||||
ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
|
||||
|
||||
ifneq ($(OBJTREE), $(SRCTREE))
|
||||
$(obj)nand_boot.c:
|
||||
@rm -f $(obj)nand_boot.c
|
||||
ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
|
||||
endif
|
||||
|
||||
#########################################################################
|
||||
|
||||
$(obj)%.o: $(obj)%.S
|
||||
$(CC) $(AFLAGS) -c -o $@ $<
|
||||
|
||||
$(obj)%.o: $(obj)%.c
|
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
82
nand_spl/board/freescale/mpc8572ds/nand_boot.c
Normal file
82
nand_spl/board/freescale/mpc8572ds/nand_boot.c
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* Copyright 2009-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
*
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ns16550.h>
|
||||
#include <asm/io.h>
|
||||
#include <nand.h>
|
||||
|
||||
u32 sysclk_tbl[] = {
|
||||
33333000, 39999600, 49999500, 66666000,
|
||||
83332500, 99999000, 133332000, 166665000
|
||||
};
|
||||
|
||||
void board_init_f(ulong bootflag)
|
||||
{
|
||||
int px_spd;
|
||||
u32 plat_ratio, bus_clk, sys_clk;
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
|
||||
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
|
||||
/* for FPGA */
|
||||
set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
|
||||
set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
|
||||
#else
|
||||
#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined
|
||||
#endif
|
||||
|
||||
/* initialize selected port with appropriate baud rate */
|
||||
px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
|
||||
sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
|
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
|
||||
bus_clk = sys_clk * plat_ratio / 2;
|
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
|
||||
bus_clk / 16 / CONFIG_BAUDRATE);
|
||||
|
||||
puts("\nNAND boot... ");
|
||||
|
||||
/* copy code to RAM and jump to it - this should not return */
|
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read.
|
||||
*/
|
||||
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
|
||||
CONFIG_SYS_NAND_U_BOOT_RELOC);
|
||||
}
|
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr)
|
||||
{
|
||||
nand_boot();
|
||||
}
|
||||
|
||||
void putc(char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
|
||||
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
|
||||
}
|
||||
|
||||
void puts(const char *str)
|
||||
{
|
||||
while (*str)
|
||||
putc(*str++);
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue