Merge branch 'fixes' into cleanups

Conflicts:

	board/atmel/atngw100/atngw100.c
	board/atmel/atstk1000/atstk1000.c
	cpu/at32ap/at32ap700x/gpio.c
	include/asm-avr32/arch-at32ap700x/clk.h
	include/configs/atngw100.h
	include/configs/atstk1002.h
	include/configs/atstk1003.h
	include/configs/atstk1004.h
	include/configs/atstk1006.h
	include/configs/favr-32-ezkit.h
	include/configs/hammerhead.h
	include/configs/mimc200.h

.gitignore

@@ -11,6 +11,7 @@
 *.a
 *.o
 *~
+*.swp
 *.patch
 
 #
@@ -46,9 +47,16 @@ patches-*
 patches
 series
 
+# gdb files
+.gdb_history
+
 # cscope files
 cscope.*
 
+# tags files
+/ctags
+/etags
+
 # OneNAND IPL files
 /onenand_ipl/onenand-ipl*
 /onenand_ipl/board/*/onenand*

CREDITS

@@ -405,7 +405,9 @@ D: Atmel AT91CAP9ADK support
 
 N: Ricardo Ribalda Delgado
 E: ricardo.ribalda@uam.es
-D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460
+D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460, v5fx30teval
+D: Virtex ppc440 generic architecture
+D: Virtex ppc405 generic architecture
 W: http://www.ii.uam.es/~rribalda
 
 N: Stefan Roese

MAINTAINERS

@@ -4,7 +4,7 @@
 #									#
 # For any board without permanent maintainer, please contact		#
 #	Wolfgang Denk <wd@denx.de>					#
-# and Cc: the <U-Boot-Users@lists.sourceforge.net> mailing lists.	#
+# and Cc: the <u-boot@lists.denx.de> mailing list.			#
 #									#
 # Note: lists sorted by Maintainer Name					#
 #########################################################################
@@ -130,6 +130,10 @@ Jon Diekema <jon.diekema@smiths-aerospace.com>
 
 	sbc8260		MPC8260
 
+Dirk Eibach <eibach@gdsys.de>
+
+	neo		PPC405EP
+
 Dave Ellis <DGE@sixnetio.com>
 
 	SXNI855T	MPC8xx
@@ -314,6 +318,9 @@ Daniel Poirot <dan.poirot@windriver.com>
 Ricardo Ribalda <ricardo.ribalda@uam.es>
 
 	ml507 		PPC440x5
+	v5fx30teval	PPC440x5
+	xilinx-ppc405-generic	PPC405
+	xilinx-ppc440-generic	PPC440x5
 
 Stefan Roese <sr@denx.de>
 
@@ -359,6 +366,10 @@ Travis Sawyer (travis.sawyer@sandburst.com>
 	METROBOX	PPC440GX
 	XPEDITE1K	PPC440GX
 
+Georg Schardt <schardt@team-ctech.de>
+
+	fx12mm		PPC405
+
 Heiko Schocher <hs@denx.de>
 
 	ids8247		MPC8247
@@ -592,6 +603,10 @@ Greg Ungerer <greg.ungerer@opengear.com>
 	cm4116		ks8695p
 	cm4148		ks8695p
 
+Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
+
+	SFFSDR		ARM926EJS
+
 Richard Woodruff <r-woodruff2@ti.com>
 
 	omap2420h4	ARM1136EJS
@@ -601,6 +616,10 @@ Alex Z
 	lart		SA1100
 	dnp1110		SA1110
 
+Sergey Lapin <slapin@ossfans.org>
+
+	afeb9260	ARM926EJS (AT91SAM9260 SoC)
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
@@ -685,7 +704,6 @@ Yasushi Shoji <yashi@atmark-techno.com>
 Michal Simek <monstr@monstr.eu>
 
 	ML401		MicroBlaze
-	XUPV2P		MicroBlaze
 
 #########################################################################
 # Coldfire Systems:							#
@@ -707,6 +725,7 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 	M52277EVB	mcf5227x
 	M5235EVB	mcf52x2
 	M5253DEMO	mcf52x2
+	M53017EVB	mcf532x
 	M5329EVB	mcf532x
 	M5373EVB	mcf532x
 	M54455EVB	mcf5445x

MAKEALL

@@ -1,6 +1,15 @@
 #!/bin/sh
 
-: ${JOBS:=}
+# Determine number of CPU cores if no default was set
+: ${BUILD_NCPUS:="`getconf _NPROCESSORS_ONLN`"}
+
+if [ "$BUILD_NCPUS" -gt 1 ]
+then
+	JOBS=-j`expr "$BUILD_NCPUS" + 1`
+else
+	JOBS=""
+fi
+
 
 if [ "${CROSS_COMPILE}" ] ; then
 	MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"
@@ -161,6 +170,7 @@ LIST_4xx="		\
 	alpr		\
 	AP1000		\
 	AR405		\
+	arches		\
 	ASH405		\
 	bamboo		\
 	bamboo_nand	\
@@ -185,6 +195,7 @@ LIST_4xx="		\
 	ebony		\
 	ERIC		\
 	EXBITGEN	\
+	fx12mm		\
 	G2000		\
 	glacier		\
 	haleakala	\
@@ -210,6 +221,7 @@ LIST_4xx="		\
 	ml300		\
 	ml507		\
 	ml507_flash	\
+	neo		\
 	ocotea		\
 	OCRTC		\
 	ORSG		\
@@ -230,12 +242,16 @@ LIST_4xx="		\
 	sequoia_nand	\
 	taihu		\
 	taishan		\
+	v5fx30teval	\
+	v5fx30teval_flash \
 	VOH405		\
 	VOM405		\
 	W7OLMC		\
 	W7OLMG		\
 	walnut		\
 	WUH405		\
+	xilinx-ppc440-generic \
+	xilinx-ppc440-generic_flash \
 	XPEDITE1K	\
 	yellowstone	\
 	yosemite	\
@@ -320,7 +336,7 @@ LIST_8260="		\
 
 LIST_83xx="		\
 	MPC8313ERDB_33	\
-	MPC8313ERDB_66	\
+	MPC8313ERDB_NAND_66	\
 	MPC8315ERDB	\
 	MPC8323ERDB	\
 	MPC832XEMDS	\
@@ -527,6 +543,7 @@ LIST_ARM11="		\
 #########################################################################
 
 LIST_at91="		\
+	afeb9260	\
 	at91cap9adk	\
 	at91rm9200dk	\
 	at91sam9260ek	\
@@ -681,7 +698,6 @@ LIST_nios2="		\
 LIST_microblaze="	\
 	ml401		\
 	suzaku		\
-	xupv2p		\
 "
 
 #########################################################################
@@ -702,6 +718,7 @@ LIST_coldfire="			\
 	M5272C3			\
 	M5275EVB		\
 	M5282EVB		\
+	M53017EVB		\
 	M5329AFEE		\
 	M5373EVB		\
 	M54451EVB		\

Makefile

@@ -21,11 +21,16 @@
 # MA 02111-1307 USA
 #
 
-VERSION = 1
+VERSION = 2009
-PATCHLEVEL = 3
+PATCHLEVEL = 01
-SUBLEVEL = 4
+SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
+ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+else
+U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL)$(EXTRAVERSION)
+endif
+TIMESTAMP_FILE = $(obj)include/timestamp_autogenerated.h
 VERSION_FILE = $(obj)include/version_autogenerated.h
 
 HOSTARCH := $(shell uname -m | \
@@ -40,7 +45,12 @@ HOSTARCH := $(shell uname -m | \
 HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \
 	    sed -e 's/\(cygwin\).*/cygwin/')
 
-export	HOSTARCH HOSTOS
+# Set shell to bash if possible, otherwise fall back to sh
+SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
+	else if [ -x /bin/bash ]; then echo /bin/bash; \
+	else echo sh; fi; fi)
+
+export	HOSTARCH HOSTOS SHELL
 
 # Deal with colliding definitions from tcsh etc.
 VENDOR=
@@ -199,6 +209,7 @@ endif
 OBJS := $(addprefix $(obj),$(OBJS))
 
 LIBS  = lib_generic/libgeneric.a
+LIBS += lib_generic/lzma/liblzma.a
 LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \
 	"board/$(VENDOR)/common/lib$(VENDOR).a"; fi)
 LIBS += cpu/$(CPU)/lib$(CPU).a
@@ -216,6 +227,7 @@ LIBS += disk/libdisk.a
 LIBS += drivers/bios_emulator/libatibiosemu.a
 LIBS += drivers/block/libblock.a
 LIBS += drivers/dma/libdma.a
+LIBS += drivers/fpga/libfpga.a
 LIBS += drivers/hwmon/libhwmon.a
 LIBS += drivers/i2c/libi2c.a
 LIBS += drivers/input/libinput.a
@@ -225,6 +237,7 @@ LIBS += drivers/mtd/libmtd.a
 LIBS += drivers/mtd/nand/libnand.a
 LIBS += drivers/mtd/nand_legacy/libnand_legacy.a
 LIBS += drivers/mtd/onenand/libonenand.a
+LIBS += drivers/mtd/ubi/libubi.a
 LIBS += drivers/mtd/spi/libspi_flash.a
 LIBS += drivers/net/libnet.a
 LIBS += drivers/net/phy/libphy.a
@@ -238,9 +251,11 @@ endif
 ifeq ($(CPU),mpc85xx)
 LIBS += drivers/qe/qe.a
 LIBS += cpu/mpc8xxx/ddr/libddr.a
+TAG_SUBDIRS += cpu/mpc8xxx
 endif
 ifeq ($(CPU),mpc86xx)
 LIBS += cpu/mpc8xxx/ddr/libddr.a
+TAG_SUBDIRS += cpu/mpc8xxx
 endif
 LIBS += drivers/rtc/librtc.a
 LIBS += drivers/serial/libserial.a
@@ -252,7 +267,7 @@ LIBS += api/libapi.a
 LIBS += post/libpost.a
 
 LIBS := $(addprefix $(obj),$(LIBS))
-.PHONY : $(LIBS) $(VERSION_FILE)
+.PHONY : $(LIBS) $(TIMESTAMP_FILE) $(VERSION_FILE)
 
 LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).a
 LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
@@ -295,7 +310,7 @@ $(obj)u-boot.hex:	$(obj)u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
 
 $(obj)u-boot.srec:	$(obj)u-boot
-		$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
+		$(OBJCOPY) -O srec $< $@
 
 $(obj)u-boot.bin:	$(obj)u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
@@ -344,13 +359,13 @@ $(SUBDIRS):	depend $(obj)include/autoconf.mk
 $(LDSCRIPT):	depend $(obj)include/autoconf.mk
 		$(MAKE) -C $(dir $@) $(notdir $@)
 
-$(NAND_SPL):	$(VERSION_FILE)	$(obj)include/autoconf.mk
+$(NAND_SPL):	$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
 		$(MAKE) -C nand_spl/board/$(BOARDDIR) all
 
 $(U_BOOT_NAND):	$(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
 		cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
 
-$(ONENAND_IPL):	$(VERSION_FILE)	$(obj)include/autoconf.mk
+$(ONENAND_IPL):	$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
 		$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
 
 $(U_BOOT_ONENAND):	$(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
@@ -359,10 +374,13 @@ $(U_BOOT_ONENAND):	$(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
 
 $(VERSION_FILE):
 		@( printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' "$(U_BOOT_VERSION)" \
-		 '$(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion $(TOPDIR))' \
+		 '$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ) > $@.tmp
-		 ) > $@.tmp
 		@cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
 
+$(TIMESTAMP_FILE):
+		@date +'#define U_BOOT_DATE "%b %d %C%y"' > $@
+		@date +'#define U_BOOT_TIME "%T"' >> $@
+
 gdbtools:
 		$(MAKE) -C tools/gdb all || exit 1
 
@@ -372,7 +390,7 @@ updater:
 env:
 		$(MAKE) -C tools/env all MTD_VERSION=${MTD_VERSION} || exit 1
 
-depend dep:	$(VERSION_FILE)
+depend dep:	$(TIMESTAMP_FILE) $(VERSION_FILE)
 		for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done
 
 TAG_SUBDIRS += include
@@ -445,7 +463,8 @@ $(obj)include/autoconf.mk: $(obj)include/config.h
 	set -e ; \
 	: Extract the config macros ; \
 	$(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \
-		sed -n -f tools/scripts/define2mk.sed > $@
+		sed -n -f tools/scripts/define2mk.sed > $@.tmp && \
+	mv $@.tmp $@
 
 sinclude $(obj)include/autoconf.mk.dep
 
@@ -453,7 +472,7 @@ sinclude $(obj)include/autoconf.mk.dep
 else	# !config.mk
 all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
 $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
-$(SUBDIRS) $(VERSION_FILE) gdbtools updater env depend \
+$(SUBDIRS) $(TIMESTAMP_FILE) $(VERSION_FILE) gdbtools updater env depend \
 dep tags ctags etags cscope $(obj)System.map:
 	@echo "System not configured - see README" >&2
 	@ exit 1
@@ -917,7 +936,7 @@ MBX860T_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mbx8xx
 
 mgsuvd_config:		unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mgsuvd
+	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mgsuvd keymile
 
 MHPC_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mhpc eltec
@@ -1059,7 +1078,7 @@ RPXlite_DW_config:	unconfig
 		  $(XECHO) "... with LCD display ..."; \
 		}
 	@[ -z "$(findstring _NVRAM,$@)" ] || \
-		{ echo "#define  CFG_ENV_IS_IN_NVRAM"	>>$(obj)include/config.h ; \
+		{ echo "#define  CONFIG_ENV_IS_IN_NVRAM"	>>$(obj)include/config.h ; \
 		  $(XECHO) "... with ENV in NVRAM ..."; \
 		}
 	@$(MKCONFIG) -a RPXlite_DW ppc mpc8xx RPXlite_dw
@@ -1201,7 +1220,8 @@ bubinga_config:	unconfig
 CANBT_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd
 
-# Canyonlands & Glacier use different U-Boot images
+# Arches, Canyonlands & Glacier use different U-Boot images
+arches_config \
 canyonlands_config \
 glacier_config:	unconfig
 	@mkdir -p $(obj)include
@@ -1242,12 +1262,12 @@ CMS700_config:	unconfig
 CPCI2DP_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
 
-CPCI405_config	\
+CPCI405_config		\
-CPCI4052_config	\
+CPCI4052_config		\
 CPCI405DT_config	\
 CPCI405AB_config:	unconfig
+	@mkdir -p $(obj)board/esd/cpci405
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
-	@echo "BOARD_REVISION = $(@:_config=)"	>> $(obj)include/config.mk
 
 CPCIISER4_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpciiser4 esd
@@ -1282,6 +1302,24 @@ ERIC_config:	unconfig
 EXBITGEN_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx exbitgen
 
+fx12mm_flash_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
+	@mkdir -p $(obj)include $(obj)board/avnet/fx12mm
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-rom.lds"\
+		> $(obj)board/avnet/fx12mm/config.tmp
+	@echo "TEXT_BASE := 0xFFCB0000" \
+		>> $(obj)board/avnet/fx12mm/config.tmp
+	@$(MKCONFIG) fx12mm ppc ppc4xx fx12mm avnet
+
+fx12mm_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
+	@mkdir -p $(obj)include $(obj)board/avnet/fx12mm
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-ram.lds"\
+		> $(obj)board/avnet/fx12mm/config.tmp
+	@echo "TEXT_BASE := 0x03000000" \
+		>> $(obj)board/avnet/fx12mm/config.tmp
+	@$(MKCONFIG) fx12mm ppc ppc4xx fx12mm avnet
+
 G2000_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000
 
@@ -1356,16 +1394,26 @@ ML2_config:	unconfig
 ml300_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml300 xilinx
 
-ml507_flash_config:	unconfig
+ml507_flash_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
 	@mkdir -p $(obj)include $(obj)board/xilinx/ml507
-	@cp $(obj)board/xilinx/ml507/u-boot-rom.lds  $(obj)board/xilinx/ml507/u-boot.lds
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
-	@echo "TEXT_BASE = 0xFE360000" > $(obj)board/xilinx/ml507/config.tmp
+		> $(obj)board/xilinx/ml507/config.tmp
-	@$(MKCONFIG) $(@:_flash_config=) ppc ppc4xx ml507 xilinx
+	@echo "TEXT_BASE := 0xFE360000" \
+		>> $(obj)board/xilinx/ml507/config.tmp
+	@$(MKCONFIG) ml507 ppc ppc4xx ml507 xilinx
 
-ml507_config:	unconfig
+ml507_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
 	@mkdir -p $(obj)include $(obj)board/xilinx/ml507
-	@cp $(obj)board/xilinx/ml507/u-boot-ram.lds  $(obj)board/xilinx/ml507/u-boot.lds
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds"\
-	@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml507 xilinx
+		> $(obj)board/xilinx/ml507/config.tmp
+	@echo "TEXT_BASE := 0x04000000"  \
+		>> $(obj)board/xilinx/ml507/config.tmp
+	@$(MKCONFIG) ml507 ppc ppc4xx ml507 xilinx
+
+neo_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx neo gdsys
 
 ocotea_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx ocotea amcc
@@ -1461,6 +1509,24 @@ taihu_config:	unconfig
 taishan_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
 
+v5fx30teval_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
+	@mkdir -p $(obj)include $(obj)board/avnet/v5fx30teval
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds"\
+		> $(obj)board/avnet/v5fx30teval/config.tmp
+	@echo "TEXT_BASE := 0x03000000" \
+		>> $(obj)board/avnet/v5fx30teval/config.tmp
+	@$(MKCONFIG) v5fx30teval ppc ppc4xx v5fx30teval avnet
+
+v5fx30teval_flash_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
+	@mkdir -p $(obj)include $(obj)board/avnet/v5fx30teval
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
+		> $(obj)board/avnet/v5fx30teval/config.tmp
+	@echo "TEXT_BASE := 0xFF1C0000" \
+		>> $(obj)board/avnet/v5fx30teval/config.tmp
+	@$(MKCONFIG) v5fx30teval ppc ppc4xx v5fx30teval avnet
+
 VOH405_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx voh405 esd
 
@@ -1479,6 +1545,38 @@ sycamore_config: unconfig
 WUH405_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx wuh405 esd
 
+xilinx-ppc405-generic_flash_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-rom.lds"\
+		> $(obj)board/xilinx/ppc405-generic/config.tmp
+	@echo "TEXT_BASE := 0xFE360000" \
+		>> $(obj)board/xilinx/ppc405-generic/config.tmp
+	@$(MKCONFIG) xilinx-ppc405-generic ppc ppc4xx ppc405-generic xilinx
+
+xilinx-ppc405-generic_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-ram.lds"\
+		> $(obj)board/xilinx/ppc405-generic/config.tmp
+	@echo "TEXT_BASE := 0x04000000" \
+		>> $(obj)board/xilinx/ppc405-generic/config.tmp
+	@$(MKCONFIG) xilinx-ppc405-generic ppc ppc4xx ppc405-generic xilinx
+
+xilinx-ppc440-generic_flash_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
+		> $(obj)board/xilinx/ppc440-generic/config.tmp
+	@echo "TEXT_BASE := 0xFE360000" \
+		>> $(obj)board/xilinx/ppc440-generic/config.tmp
+	@$(MKCONFIG) xilinx-ppc440-generic ppc ppc4xx ppc440-generic xilinx
+
+xilinx-ppc440-generic_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds"\
+		> $(obj)board/xilinx/ppc440-generic/config.tmp
+	@echo "TEXT_BASE := 0x04000000" \
+		>> $(obj)board/xilinx/ppc440-generic/config.tmp
+	@$(MKCONFIG) xilinx-ppc440-generic ppc ppc4xx ppc440-generic xilinx
+
 XPEDITE1K_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx xpedite1k
 
@@ -1652,12 +1750,12 @@ ISPAN_config		\
 ISPAN_REVB_config:	unconfig
 	@mkdir -p $(obj)include
 	@if [ "$(findstring _REVB_,$@)" ] ; then \
-		echo "#define CFG_REV_B" > $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_REV_B" > $(obj)include/config.h ; \
 	fi
 	@$(MKCONFIG) -a ISPAN ppc mpc8260 ispan
 
 mgcoge_config	:	unconfig
-	@$(MKCONFIG) mgcoge ppc mpc8260 mgcoge
+	@$(MKCONFIG) mgcoge ppc mpc8260 mgcoge keymile
 
 MPC8260ADS_config	\
 MPC8260ADS_lowboot_config	\
@@ -1679,8 +1777,8 @@ PQ2FADS-ZU_66MHz_lowboot_config	\
 	@mkdir -p $(obj)include
 	@mkdir -p $(obj)board/freescale/mpc8260ads
 	$(if $(findstring PQ2FADS,$@), \
-	@echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > $(obj)include/config.h, \
+	@echo "#define CONFIG_ADSTYPE CONFIG_SYS_PQ2FADS" > $(obj)include/config.h, \
-	@echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h)
+	@echo "#define CONFIG_ADSTYPE CONFIG_SYS_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h)
 	$(if $(findstring MHz,$@), \
 	@echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> $(obj)include/config.h, \
 	$(if $(findstring VR,$@), \
@@ -1843,7 +1941,27 @@ ZPC1900_config: unconfig
 ## Coldfire
 #########################################################################
 
-M52277EVB_config:	unconfig
+M52277EVB_config \
+M52277EVB_spansion_config \
+M52277EVB_stmicro_config :	unconfig
+	@case "$@" in \
+	M52277EVB_config)		FLASH=SPANSION;; \
+	M52277EVB_spansion_config)	FLASH=SPANSION;; \
+	M52277EVB_stmicro_config)	FLASH=STMICRO;; \
+	esac; \
+	if [ "$${FLASH}" = "SPANSION" ] ; then \
+		echo "#define CONFIG_SYS_SPANSION_BOOT"	>> $(obj)include/config.h ; \
+		echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m52277evb/config.tmp ; \
+		cp $(obj)board/freescale/m52277evb/u-boot.spa $(obj)board/freescale/m52277evb/u-boot.lds ; \
+		$(XECHO) "... with SPANSION boot..." ; \
+	fi; \
+	if [ "$${FLASH}" = "STMICRO" ] ; then \
+		echo "#define CONFIG_CF_SBF"	>> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_STMICRO_BOOT"	>> $(obj)include/config.h ; \
+		echo "TEXT_BASE = 0x43E00000" > $(obj)board/freescale/m52277evb/config.tmp ; \
+		cp $(obj)board/freescale/m52277evb/u-boot.stm $(obj)board/freescale/m52277evb/u-boot.lds ; \
+		$(XECHO) "... with ST Micro boot..." ; \
+	fi
 	@$(MKCONFIG) -a M52277EVB m68k mcf5227x m52277evb freescale
 
 M5235EVB_config \
@@ -1903,6 +2021,9 @@ M5275EVB_config :		unconfig
 M5282EVB_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb freescale
 
+M53017EVB_config :		unconfig
+	@$(MKCONFIG) $(@:_config=) m68k mcf532x m53017evb freescale
+
 M5329AFEE_config \
 M5329BFEE_config :	unconfig
 	@case "$@" in \
@@ -1932,19 +2053,19 @@ M54451EVB_stmicro_config :	unconfig
 	M54451EVB_stmicro_config)	FLASH=STMICRO;; \
 	esac; \
 	if [ "$${FLASH}" = "SPANSION" ] ; then \
-		echo "#define CFG_SPANSION_BOOT"	>> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_SPANSION_BOOT"	>> $(obj)include/config.h ; \
 		echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \
 		cp $(obj)board/freescale/m54451evb/u-boot.spa $(obj)board/freescale/m54451evb/u-boot.lds ; \
 		$(XECHO) "... with SPANSION boot..." ; \
 	fi; \
 	if [ "$${FLASH}" = "STMICRO" ] ; then \
 		echo "#define CONFIG_CF_SBF"	>> $(obj)include/config.h ; \
-		echo "#define CFG_STMICRO_BOOT"	>> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_STMICRO_BOOT"	>> $(obj)include/config.h ; \
 		echo "TEXT_BASE = 0x47E00000" > $(obj)board/freescale/m54451evb/config.tmp ; \
 		cp $(obj)board/freescale/m54451evb/u-boot.stm $(obj)board/freescale/m54451evb/u-boot.lds ; \
 		$(XECHO) "... with ST Micro boot..." ; \
 	fi; \
-	echo "#define CFG_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ;
+	echo "#define CONFIG_SYS_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ;
 	@$(MKCONFIG) -a M54451EVB m68k mcf5445x m54451evb freescale
 
 M54455EVB_config \
@@ -1966,25 +2087,25 @@ M54455EVB_stm33_config :	unconfig
 	M54455EVB_stm33_config)		FLASH=STMICRO; FREQ=33333333;; \
 	esac; \
 	if [ "$${FLASH}" = "INTEL" ] ; then \
-		echo "#define CFG_INTEL_BOOT" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_INTEL_BOOT" >> $(obj)include/config.h ; \
 		echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
 		cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \
 		$(XECHO) "... with INTEL boot..." ; \
 	fi; \
 	if [ "$${FLASH}" = "ATMEL" ] ; then \
-		echo "#define CFG_ATMEL_BOOT"	>> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_ATMEL_BOOT"	>> $(obj)include/config.h ; \
 		echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
 		cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \
 		$(XECHO) "... with ATMEL boot..." ; \
 	fi; \
 	if [ "$${FLASH}" = "STMICRO" ] ; then \
 		echo "#define CONFIG_CF_SBF"	>> $(obj)include/config.h ; \
-		echo "#define CFG_STMICRO_BOOT"	>> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_STMICRO_BOOT"	>> $(obj)include/config.h ; \
 		echo "TEXT_BASE = 0x4FE00000" > $(obj)board/freescale/m54455evb/config.tmp ; \
 		cp $(obj)board/freescale/m54455evb/u-boot.stm $(obj)board/freescale/m54455evb/u-boot.lds ; \
 		$(XECHO) "... with ST Micro boot..." ; \
 	fi; \
-	echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
+	echo "#define CONFIG_SYS_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
 	$(XECHO) "... with $${FREQ}Hz input clock"
 	@$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale
 
@@ -2004,20 +2125,20 @@ M5475GFE_config :	unconfig
 	M5475FFE_config)	BOOT=2;CODE=32;VID=1;USB=1;RAM=64;RAM1=64;; \
 	M5475GFE_config)	BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
 	esac; \
-	echo "#define CFG_BUSCLK	133333333" > $(obj)include/config.h ; \
+	echo "#define CONFIG_SYS_BUSCLK	133333333" > $(obj)include/config.h ; \
-	echo "#define CFG_BOOTSZ	$${BOOT}" >> $(obj)include/config.h ; \
+	echo "#define CONFIG_SYS_BOOTSZ	$${BOOT}" >> $(obj)include/config.h ; \
-	echo "#define CFG_DRAMSZ	$${RAM}" >> $(obj)include/config.h ; \
+	echo "#define CONFIG_SYS_DRAMSZ	$${RAM}" >> $(obj)include/config.h ; \
 	if [ "$${RAM1}" != "0" ] ; then \
-		echo "#define CFG_DRAMSZ1	$${RAM1}" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_DRAMSZ1	$${RAM1}" >> $(obj)include/config.h ; \
 	fi; \
 	if [ "$${CODE}" != "0" ] ; then \
-		echo "#define CFG_NOR1SZ	$${CODE}" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_NOR1SZ	$${CODE}" >> $(obj)include/config.h ; \
 	fi; \
 	if [ "$${VID}" == "1" ] ; then \
-		echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_VIDEO" >> $(obj)include/config.h ; \
 	fi; \
 	if [ "$${USB}" == "1" ] ; then \
-		echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_USBCTRL" >> $(obj)include/config.h ; \
 	fi
 	@$(MKCONFIG) -a M5475EVB m68k mcf547x_8x m547xevb freescale
 
@@ -2039,20 +2160,20 @@ M5485HFE_config :	unconfig
 	M5485GFE_config)	BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
 	M5485HFE_config)	BOOT=2;CODE=16;VID=1;USB=0;RAM=64;RAM1=0;; \
 	esac; \
-	echo "#define CFG_BUSCLK	100000000" > $(obj)include/config.h ; \
+	echo "#define CONFIG_SYS_BUSCLK	100000000" > $(obj)include/config.h ; \
-	echo "#define CFG_BOOTSZ	$${BOOT}" >> $(obj)include/config.h ; \
+	echo "#define CONFIG_SYS_BOOTSZ	$${BOOT}" >> $(obj)include/config.h ; \
-	echo "#define CFG_DRAMSZ	$${RAM}" >> $(obj)include/config.h ; \
+	echo "#define CONFIG_SYS_DRAMSZ	$${RAM}" >> $(obj)include/config.h ; \
 	if [ "$${RAM1}" != "0" ] ; then \
-		echo "#define CFG_DRAMSZ1	$${RAM1}" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_DRAMSZ1	$${RAM1}" >> $(obj)include/config.h ; \
 	fi; \
 	if [ "$${CODE}" != "0" ] ; then \
-		echo "#define CFG_NOR1SZ	$${CODE}" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_NOR1SZ	$${CODE}" >> $(obj)include/config.h ; \
 	fi; \
 	if [ "$${VID}" == "1" ] ; then \
-		echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_VIDEO" >> $(obj)include/config.h ; \
 	fi; \
 	if [ "$${USB}" == "1" ] ; then \
-		echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_USBCTRL" >> $(obj)include/config.h ; \
 	fi
 	@$(MKCONFIG) -a M5485EVB m68k mcf547x_8x m548xevb freescale
 
@@ -2071,11 +2192,11 @@ MPC8313ERDB_NAND_66_config: unconfig
 	@mkdir -p $(obj)board/freescale/mpc8313erdb
 	@if [ "$(findstring _33_,$@)" ] ; then \
 		$(XECHO) -n "...33M ..." ; \
-		echo "#define CFG_33MHZ" >>$(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_33MHZ" >>$(obj)include/config.h ; \
 	fi ; \
 	if [ "$(findstring _66_,$@)" ] ; then \
 		$(XECHO) -n "...66M..." ; \
-		echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_66MHZ" >>$(obj)include/config.h ; \
 	fi ; \
 	if [ "$(findstring _NAND_,$@)" ] ; then \
 		$(XECHO) -n "...NAND..." ; \
@@ -2083,6 +2204,9 @@ MPC8313ERDB_NAND_66_config: unconfig
 		echo "#define CONFIG_NAND_U_BOOT" >>$(obj)include/config.h ; \
 	fi ;
 	@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
+	@if [ "$(findstring _NAND_,$@)" ] ; then \
+		echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \
+	fi ;
 
 MPC8315ERDB_config: unconfig
 	@$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
@@ -2344,8 +2468,14 @@ TQM8560_config:		unconfig
 MPC8610HPCD_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8610hpcd freescale
 
+MPC8641HPCN_36BIT_config \
 MPC8641HPCN_config:    unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
+	@mkdir -p $(obj)include
+	@if [ "$(findstring _36BIT_,$@)" ] ; then \
+		echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
+		$(XECHO) "... enabling 36-bit physical addressing." ; \
+	fi
+	@$(MKCONFIG) -a MPC8641HPCN ppc mpc86xx mpc8641hpcn freescale
 
 sbc8641d_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d
@@ -2435,15 +2565,6 @@ shannon_config	:	unconfig
 at91rm9200dk_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
 
-at91sam9261ek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91
-
-at91sam9263ek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91
-
-at91sam9rlek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91
-
 cmc_pu2_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
 
@@ -2463,11 +2584,69 @@ mp2usb_config	:	unconfig
 ## Atmel ARM926EJ-S Systems
 #########################################################################
 
+afeb9260_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs afeb9260 NULL at91
+
 at91cap9adk_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91
 
+at91sam9260ek_nandflash_config \
+at91sam9260ek_dataflash_cs0_config \
+at91sam9260ek_dataflash_cs1_config \
 at91sam9260ek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91
+	@if [ "$(findstring _nandflash,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in NAND FLASH" ; \
+	elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+	else \
+		echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS1" ; \
+	fi;
+	@$(MKCONFIG) -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91
+
+at91sam9261ek_nandflash_config \
+at91sam9261ek_dataflash_cs0_config \
+at91sam9261ek_dataflash_cs3_config \
+at91sam9261ek_config	:	unconfig
+	@if [ "$(findstring _nandflash,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in NAND FLASH" ; \
+	elif [ "$(findstring dataflash_cs3,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_DATAFLASH_CS3 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS3" ; \
+	else \
+		echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+	fi;
+	@$(MKCONFIG) -a at91sam9261ek arm arm926ejs at91sam9261ek atmel at91
+
+at91sam9263ek_nandflash_config \
+at91sam9263ek_dataflash_config \
+at91sam9263ek_dataflash_cs0_config \
+at91sam9263ek_config	:	unconfig
+	@if [ "$(findstring _nandflash,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in NAND FLASH" ; \
+	else \
+		echo "#define CONFIG_SYS_USE_DATAFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+	fi;
+	@$(MKCONFIG) -a at91sam9263ek arm arm926ejs at91sam9263ek atmel at91
+
+at91sam9rlek_nandflash_config \
+at91sam9rlek_dataflash_config \
+at91sam9rlek_dataflash_cs0_config \
+at91sam9rlek_config	:	unconfig
+	@if [ "$(findstring _nandflash,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in NAND FLASH" ; \
+	else \
+		echo "#define CONFIG_SYS_USE_DATAFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+	fi;
+	@$(MKCONFIG) -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
 
 ########################################################################
 ## ARM Integrator boards - see doc/README-integrator for more info.
@@ -2972,11 +3151,6 @@ suzaku_config:	unconfig
 	@echo "#define CONFIG_SUZAKU 1" > $(obj)include/config.h
 	@$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
 
-xupv2p_config:	unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_XUPV2P 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $(@:_config=) microblaze microblaze xupv2p xilinx
-
 #========================================================================
 # Blackfin
 #========================================================================
@@ -3029,7 +3203,7 @@ mimc200_config		:	unconfig
 rsk7203_config: unconfig
 	@ >include/config.h
 	@echo "#define CONFIG_RSK7203 1" >> include/config.h
-	@./mkconfig -a $(@:_config=) sh sh2 rsk7203
+	@$(MKCONFIG) -a $(@:_config=) sh sh2 rsk7203 renesas
 
 #########################################################################
 ## sh3 (Renesas SuperH)
@@ -3052,7 +3226,7 @@ ms7720se_config: unconfig
 MigoR_config :       unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_MIGO_R 1" > $(obj)include/config.h
-	@./mkconfig -a $(@:_config=) sh sh4 MigoR
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 MigoR renesas
 
 ms7750se_config: unconfig
 	@mkdir -p $(obj)include
@@ -3067,27 +3241,27 @@ ms7722se_config :	unconfig
 r2dplus_config  :   unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_R2DPLUS 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $(@:_config=) sh sh4 r2dplus
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 r2dplus renesas
 
 r7780mp_config: unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_R7780MP 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $(@:_config=) sh sh4 r7780mp
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 r7780mp renesas
 
 sh7763rdp_config  :   unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7763rdp
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7763rdp renesas
 
 sh7785lcr_config  :   unconfig
 	@ >include/config.h
 	@echo "#define CONFIG_SH7785LCR 1" >> include/config.h
-	@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7785lcr
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7785lcr renesas
 
 ap325rxa_config  :   unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_AP325RXA 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $(@:_config=) sh sh4 ap325rxa
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 ap325rxa renesas
 
 #========================================================================
 # SPARC
@@ -3148,7 +3322,7 @@ clean:
 	@rm -f $(obj)include/bmp_logo.h
 	@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
 	@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl-4k.bin,ipl.map}
-	@rm -f $(obj)api_examples/demo $(VERSION_FILE)
+	@rm -f $(obj)api_examples/demo $(TIMESTAMP_FILE) $(VERSION_FILE)
 	@find $(OBJTREE) -type f \
 		\( -name 'core' -o -name '*.bak' -o -name '*~' \
 		-o -name '*.o'	-o -name '*.a'	\) -print \
@@ -3162,7 +3336,7 @@ clobber:	clean
 	@rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \
 		$(obj)cscope.* $(obj)*.*~
 	@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
-	@rm -f $(obj)tools/{crc32.c,environment.c,env/crc32.c,md5.c,sha1.c,inca-swap-bytes}
+	@rm -f $(obj)tools/{crc32.c,env_embedded.c,env/crc32.c,md5.c,sha1.c,inca-swap-bytes}
 	@rm -f $(obj)tools/{image.c,fdt.c,fdt_ro.c,fdt_rw.c,fdt_strerror.c,zlib.h}
 	@rm -f $(obj)tools/{fdt_wip.c,libfdt_internal.h}
 	@rm -f $(obj)cpu/mpc824x/bedbug_603e.c

README.nios_CONFIG_SYS_NIOS_CPU

@@ -0,0 +1,140 @@
+
+===============================================================================
+	C F G _ N I O S _ C P U _ *   v s .   N I O S	S D K
+===============================================================================
+
+When ever you have to make a new NIOS CPU configuration you can use this table
+as a reference list to the original NIOS SDK symbols made by Alteras SOPC
+Builder. Look into excalibur.h and excalibur.s in your SDK path cpu_sdk/inc.
+Symbols beginning with a '[ptf]:' are coming from your SOPC sytem description
+(PTF file) in sections WIZARD_SCRIPT_ARGUMENTS or SYSTEM_BUILDER_INFO.
+
+C O R E					N I O S	  S D K			[1],[7]
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_CLK					nasys_clock_freq
+CONFIG_SYS_NIOS_CPU_ICACHE					nasys_icache_size
+CONFIG_SYS_NIOS_CPU_DCACHE					nasys_dcache_size
+CONFIG_SYS_NIOS_CPU_REG_NUMS					nasys_nios_num_regs
+CONFIG_SYS_NIOS_CPU_MUL					__nios_use_multiply__
+CONFIG_SYS_NIOS_CPU_MSTEP					__nios_use_mstep__
+CONFIG_SYS_NIOS_CPU_STACK					nasys_stack_top
+CONFIG_SYS_NIOS_CPU_VEC_BASE					nasys_vector_table
+CONFIG_SYS_NIOS_CPU_VEC_SIZE					nasys_vector_table_size
+CONFIG_SYS_NIOS_CPU_VEC_NUMS
+CONFIG_SYS_NIOS_CPU_RST_VECT					nasys_reset_address
+CONFIG_SYS_NIOS_CPU_DBG_CORE					nasys_debug_core
+CONFIG_SYS_NIOS_CPU_RAM_BASE		na_onchip_ram_64_kbytes
+CONFIG_SYS_NIOS_CPU_RAM_SIZE		na_onchip_ram_64_kbytes_size
+CONFIG_SYS_NIOS_CPU_ROM_BASE		na_boot_monitor_rom
+CONFIG_SYS_NIOS_CPU_ROM_SIZE		na_boot_monitor_rom_size
+CONFIG_SYS_NIOS_CPU_OCI_BASE					nasys_oci_core
+CONFIG_SYS_NIOS_CPU_OCI_SIZE
+CONFIG_SYS_NIOS_CPU_SRAM_BASE		na_ext_ram		nasys_program_mem
+							nasys_data_mem
+CONFIG_SYS_NIOS_CPU_SRAM_SIZE		na_ext_ram_size		nasys_program_mem_size
+							nasys_data_mem_size
+CONFIG_SYS_NIOS_CPU_SDRAM_BASE		 na_sdram
+CONFIG_SYS_NIOS_CPU_SDRAM_SIZE		 na_sdram_size
+CONFIG_SYS_NIOS_CPU_FLASH_BASE		 na_ext_flash		nasys_main_flash
+							nasys_am29lv065d_flash_0
+							nasys_flash_0
+CONFIG_SYS_NIOS_CPU_FLASH_SIZE	    na_ext_flash_size		nasys_main_flash_size
+
+T I M E R				N I O S	  S D K			    [3]
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_TIMER_NUMS					nasys_timer_count
+CONFIG_SYS_NIOS_CPU_TIMER[0-9]					nasys_timer_[0-9]
+CONFIG_SYS_NIOS_CPU_TIMER[0-9]_IRQ				nasys_timer_[0-9]_irq
+CONFIG_SYS_NIOS_CPU_TIMER[0-9]_PER				[ptf]:period
+							[ptf]:period_units
+							[ptf]:mult
+CONFIG_SYS_NIOS_CPU_TIMER[0-9]_AR				[ptf]:always_run
+CONFIG_SYS_NIOS_CPU_TIMER[0-9]_FP				[ptf]:fixed_period
+CONFIG_SYS_NIOS_CPU_TIMER[0-9]_SS				[ptf]:snapshot
+
+U A R T					N I O S	  S D K			    [2]
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_UART_NUMS					nasys_uart_count
+CONFIG_SYS_NIOS_CPU_UART[0-9]					nasys_uart_[0-9]
+CONFIG_SYS_NIOS_CPU_UART[0-9]_IRQ				nasys_uart_[0-9]_irq
+CONFIG_SYS_NIOS_CPU_UART[0-9]_BR				[ptf]:baud
+CONFIG_SYS_NIOS_CPU_UART[0-9]_DB				[ptf]:data_bits
+CONFIG_SYS_NIOS_CPU_UART[0-9]_SB				[ptf]:stop_bits
+CONFIG_SYS_NIOS_CPU_UART[0-9]_PA				[ptf]:parity
+CONFIG_SYS_NIOS_CPU_UART[0-9]_HS				[ptf]:use_cts_rts
+CONFIG_SYS_NIOS_CPU_UART[0-9]_EOP				[ptf]:use_eop_register
+
+P I O					N I O S	  S D K			    [4]
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_PIO_NUMS					nasys_pio_count
+CONFIG_SYS_NIOS_CPU_PIO[0-9]					nasys_pio_[0-9]
+CONFIG_SYS_NIOS_CPU_PIO[0-9]_IRQ				nasys_pio_[0-9]_irq
+CONFIG_SYS_NIOS_CPU_PIO[0-9]_BITS				[ptf]:Data_Width
+CONFIG_SYS_NIOS_CPU_PIO[0-9]_TYPE				[ptf]:has_tri
+							[ptf]:has_out
+							[ptf]:has_in
+CONFIG_SYS_NIOS_CPU_PIO[0-9]_CAP				[ptf]:capture
+CONFIG_SYS_NIOS_CPU_PIO[0-9]_EDGE				[ptf]:edge_type
+CONFIG_SYS_NIOS_CPU_PIO[0-9]_ITYPE				[ptf]:irq_type
+
+S P I					N I O S	  S D K			    [6]
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_SPI_NUMS					nasys_spi_count
+CONFIG_SYS_NIOS_CPU_SPI[0-9]					nasys_spi_[0-9]
+CONFIG_SYS_NIOS_CPU_SPI[0-9]_IRQ				nasys_spi_[0-9]_irq
+CONFIG_SYS_NIOS_CPU_SPI[0-9]_BITS				[ptf]:databits
+CONFIG_SYS_NIOS_CPU_SPI[0-9]_MA				[ptf]:ismaster
+CONFIG_SYS_NIOS_CPU_SPI[0-9]_SLN				[ptf]:numslaves
+CONFIG_SYS_NIOS_CPU_SPI[0-9]_TCLK				[ptf]:targetclock
+CONFIG_SYS_NIOS_CPU_SPI[0-9]_TDELAY				[ptf]:targetdelay
+CONFIG_SYS_NIOS_CPU_SPI[0-9]_*					[ptf]:*
+
+I D E					N I O S	  S D K
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_IDE_NUMS					nasys_usersocket_count
+CONFIG_SYS_NIOS_CPU_IDE[0-9]					nasys_usersocket_[0-9]
+
+A S M I					N I O S	  S D K			    [5]
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_ASMI_NUMS					nasys_asmi_count
+CONFIG_SYS_NIOS_CPU_ASMI[0-9]					nasys_asmi_[0-9]
+CONFIG_SYS_NIOS_CPU_ASMI[0-9]_IRQ				nasys_asmi_[0-9]_irq
+
+E t h e r n e t	  ( L A N )		N I O S	  S D K
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_LAN_NUMS
+CONFIG_SYS_NIOS_CPU_LAN[0-9]_BASE	na_lan91c111
+CONFIG_SYS_NIOS_CPU_LAN[0-9]_OFFS				LAN91C111_REGISTERS_OFFSET
+CONFIG_SYS_NIOS_CPU_LAN[0-9]_IRQ	na_lan91c111_irq
+CONFIG_SYS_NIOS_CPU_LAN[0-9]_BUSW				LAN91C111_DATA_BUS_WIDTH
+CONFIG_SYS_NIOS_CPU_LAN[0-9]_TYPE
+
+s y s t e m   c o m p o s i n g		N I O S	  S D K
+-------------------------------------------------------------------------------
+CONFIG_SYS_NIOS_CPU_TICK_TIMER		(na_low_priority_timer2)
+CONFIG_SYS_NIOS_CPU_USER_TIMER		(na_timer1)
+CONFIG_SYS_NIOS_CPU_BUTTON_PIO		(na_button_pio)
+CONFIG_SYS_NIOS_CPU_LCD_PIO		(na_lcd_pio)
+CONFIG_SYS_NIOS_CPU_LED_PIO		(na_led_pio)
+CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO	(na_seven_seg_pio)
+CONFIG_SYS_NIOS_CPU_RECONF_PIO		(na_reconfig_request_pio)
+CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO	(na_cf_present_pio)
+CONFIG_SYS_NIOS_CPU_CFPOWER_PIO	(na_cf_power_pio)
+CONFIG_SYS_NIOS_CPU_CFATASEL_PIO	(na_cf_ata_select_pio)
+CONFIG_SYS_NIOS_CPU_USER_SPI		(na_spi)
+
+
+===============================================================================
+	R E F E R E N C E S
+===============================================================================
+[1]	http://www.altera.com/literature/ds/ds_nioscpu.pdf
+[2]	http://www.altera.com/literature/ds/ds_nios_uart.pdf
+[3]	http://www.altera.com/literature/ds/ds_nios_timer.pdf
+[4]	http://www.altera.com/literature/ds/ds_nios_pio.pdf
+[5]	http://www.altera.com/literature/ds/ds_nios_asmi.pdf
+[6]	http://www.altera.com/literature/ds/ds_nios_spi.pdf
+[7]	http://www.altera.com/literature/ds/ds_legacy_sdram_ctrl.pdf
+
+
+===============================================================================
+Stephan Linz <linz@li-pro.net>

api/api.c

@@ -534,7 +534,7 @@ static int API_env_enum(va_list ap)
 
 		for (i = 0; env_get_char(i) != '\0'; i = n + 1) {
 			for (n = i; env_get_char(n) != '\0'; ++n) {
-				if (n >= CFG_ENV_SIZE) {
+				if (n >= CONFIG_ENV_SIZE) {
 					/* XXX shouldn't we set *next = NULL?? */
 					return 0;
 				}

api/api_platform-ppc.c

@@ -66,7 +66,7 @@ int platform_sys_info(struct sys_info *si)
 	si->bar = gd->bd->bi_bar;
 #undef bi_bar
 #else
-	si->bar = NULL;
+	si->bar = 0;
 #endif
 
 	platform_set_mr(si, gd->bd->bi_memstart, gd->bd->bi_memsize, MR_ATTR_DRAM);

api/api_storage.c

@@ -30,6 +30,10 @@
 #include <common.h>
 #include <api_public.h>
 
+#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
+#include <usb.h>
+#endif
+
 #define DEBUG
 #undef DEBUG
 
@@ -63,28 +67,28 @@ static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, };
 void dev_stor_init(void)
 {
 #if defined(CONFIG_CMD_IDE)
-	specs[ENUM_IDE].max_dev = CFG_IDE_MAXDEVICE;
+	specs[ENUM_IDE].max_dev = CONFIG_SYS_IDE_MAXDEVICE;
 	specs[ENUM_IDE].enum_started = 0;
 	specs[ENUM_IDE].enum_ended = 0;
 	specs[ENUM_IDE].type = DEV_TYP_STOR | DT_STOR_IDE;
 	specs[ENUM_IDE].name = "ide";
 #endif
 #if defined(CONFIG_CMD_MMC)
-	specs[ENUM_MMC].max_dev = CFG_MMC_MAX_DEVICE;
+	specs[ENUM_MMC].max_dev = CONFIG_SYS_MMC_MAX_DEVICE;
 	specs[ENUM_MMC].enum_started = 0;
 	specs[ENUM_MMC].enum_ended = 0;
 	specs[ENUM_MMC].type = DEV_TYP_STOR | DT_STOR_MMC;
 	specs[ENUM_MMC].name = "mmc";
 #endif
 #if defined(CONFIG_CMD_SATA)
-	specs[ENUM_SATA].max_dev = CFG_SATA_MAX_DEVICE;
+	specs[ENUM_SATA].max_dev = CONFIG_SYS_SATA_MAX_DEVICE;
 	specs[ENUM_SATA].enum_started = 0;
 	specs[ENUM_SATA].enum_ended = 0;
 	specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
 	specs[ENUM_SATA].name = "sata";
 #endif
 #if defined(CONFIG_CMD_SCSI)
-	specs[ENUM_SCSI].max_dev = CFG_SCSI_MAX_DEVICE;
+	specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;
 	specs[ENUM_SCSI].enum_started = 0;
 	specs[ENUM_SCSI].enum_ended = 0;
 	specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;

blackfin_config.mk

@@ -24,7 +24,7 @@
 CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU)))
 CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE)))
 
-PLATFORM_RELFLAGS += -ffixed-P5
+PLATFORM_RELFLAGS += -ffixed-P5 -fomit-frame-pointer
 PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
 
 ifneq (,$(CONFIG_BFIN_CPU))

board/AtmarkTechno/suzaku/flash.c

@@ -24,7 +24,7 @@
 
 #include <common.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 unsigned long flash_init(void)
 {

board/AtmarkTechno/suzaku/u-boot.lds

@@ -61,6 +61,7 @@ SECTIONS
 	{
 		__bss_start = .;
 		*(.bss)
+		. = ALIGN(4);
 		__bss_end = .;
 	}
 	__end = . ;

board/BuS/EB+MCF-EV123/EB+MCF-EV123.c

@@ -32,7 +32,7 @@
 int checkboard (void)
 {
 	puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
-#if (TEXT_BASE ==  CFG_INT_FLASH_BASE)
+#if (TEXT_BASE ==  CONFIG_SYS_INT_FLASH_BASE)
 	puts ("       Boot from Internal FLASH\n");
 #endif
 
@@ -45,10 +45,10 @@ phys_size_t initdram (int board_type)
 
 	size = 0;
 	MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6
-			| MCFSDRAMC_DCR_RC ((15 * CFG_CLK) >> 4);
+			| MCFSDRAMC_DCR_RC ((15 * CONFIG_SYS_CLK) >> 4);
-#ifdef CFG_SDRAM_BASE0
+#ifdef CONFIG_SYS_SDRAM_BASE0
 
-	MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE0)
+	MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE0)
 			| MCFSDRAMC_DACR_CASL (1)
 			| MCFSDRAMC_DACR_CBM (3)
 			| MCFSDRAMC_DACR_PS_16;
@@ -57,17 +57,17 @@ phys_size_t initdram (int board_type)
 
 	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
 
-	*(unsigned short *) (CFG_SDRAM_BASE0) = 0xA5A5;
+	*(unsigned short *) (CONFIG_SYS_SDRAM_BASE0) = 0xA5A5;
 	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
 	for (i = 0; i < 2000; i++)
 		asm (" nop");
 	mbar_writeLong (MCFSDRAMC_DACR0,
 			mbar_readLong (MCFSDRAMC_DACR0) | MCFSDRAMC_DACR_IMRS);
-	*(unsigned int *) (CFG_SDRAM_BASE0 + 0x220) = 0xA5A5;
+	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE0 + 0x220) = 0xA5A5;
-	size += CFG_SDRAM_SIZE * 1024 * 1024;
+	size += CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 #endif
-#ifdef CFG_SDRAM_BASE1
+#ifdef CONFIG_SYS_SDRAM_BASE1
-	MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE1)
+	MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
 			| MCFSDRAMC_DACR_CASL (1)
 			| MCFSDRAMC_DACR_CBM (3)
 			| MCFSDRAMC_DACR_PS_16;
@@ -76,25 +76,25 @@ phys_size_t initdram (int board_type)
 
 	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
 
-	*(unsigned short *) (CFG_SDRAM_BASE1) = 0xA5A5;
+	*(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
 	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
 
 	for (i = 0; i < 2000; i++)
 		asm (" nop");
 
 	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
-	*(unsigned int *) (CFG_SDRAM_BASE1 + 0x220) = 0xA5A5;
+	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
-	size += CFG_SDRAM_SIZE1 * 1024 * 1024;
+	size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
 #endif
 	return size;
 }
 
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf("SDRAM test phase 1:\n");

board/BuS/EB+MCF-EV123/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o cfm_flash.o flash.o VCxK.o mii.o
+COBJS	= $(BOARD).o cfm_flash.o flash.o VCxK.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/BuS/EB+MCF-EV123/VCxK.c

@@ -25,7 +25,7 @@
 #include <asm/m5282.h>
 #include "VCxK.h"
 
-vu_char *vcxk_bws = (vu_char *)(CFG_CS3_BASE);
+vu_char *vcxk_bws = (vu_char *)(CONFIG_SYS_CS3_BASE);
 #define VCXK_BWS vcxk_bws
 
 static ulong vcxk_driver;

board/BuS/EB+MCF-EV123/cfm_flash.c

@@ -28,14 +28,14 @@
 
 #if defined(CONFIG_M5281) || defined(CONFIG_M5282)
 
-#if (CFG_CLK>20000000)
+#if (CONFIG_SYS_CLK>20000000)
-	#define CFM_CLK  (((long) CFG_CLK / (400000 * 8) + 1) | 0x40)
+	#define CFM_CLK  (((long) CONFIG_SYS_CLK / (400000 * 8) + 1) | 0x40)
 #else
-	#define CFM_CLK  ((long) CFG_CLK / 400000 + 1)
+	#define CFM_CLK  ((long) CONFIG_SYS_CLK / 400000 + 1)
 #endif
 
 #define cmf_backdoor_address(addr)	(((addr) & 0x0007FFFF) | 0x04000000 | \
-					 (CFG_MBAR & 0xC0000000))
+					 (CONFIG_SYS_MBAR & 0xC0000000))
 
 void cfm_flash_print_info (flash_info_t * info)
 {
@@ -60,8 +60,8 @@ void cfm_flash_init (flash_info_t * info)
 	MCFCFM_MCR = 0;
 	MCFCFM_CLKD = CFM_CLK;
 	debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\
-		CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
+		CONFIG_SYS_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
-		CFG_CLK);
+		CONFIG_SYS_CLK);
 	MCFCFM_SACC = 0;
 	MCFCFM_DACC = 0;
 
@@ -86,7 +86,7 @@ void cfm_flash_init (flash_info_t * info)
 	{
 		if (sector == 0)
 		{
-			info->start[sector] = CFG_INT_FLASH_BASE;
+			info->start[sector] = CONFIG_SYS_INT_FLASH_BASE;
 		}
 		else
 		{
@@ -187,7 +187,7 @@ int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cn
 	return rc;
 }
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 
 int cfm_flash_protect(flash_info_t * info,long sector,int prot)
 {

board/BuS/EB+MCF-EV123/cfm_flash.h

@@ -33,7 +33,7 @@ extern void cfm_flash_print_info (flash_info_t * info);
 extern int cfm_flash_erase_sector (flash_info_t * info, int sector);
 extern void cfm_flash_init (flash_info_t * info);
 extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 extern int cfm_flash_protect(flash_info_t * info,long sector,int prot);
 #endif
 

board/BuS/EB+MCF-EV123/flash.c

@@ -27,10 +27,10 @@
 #include <common.h>
 #include  "cfm_flash.h"
 
-#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
 #define FLASH_BANK_SIZE 0x200000
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 void flash_print_info (flash_info_t * info)
 {
@@ -83,7 +83,7 @@ unsigned long flash_init (void)
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		switch (i)
@@ -93,8 +93,8 @@ unsigned long flash_init (void)
 				(AMD_MANUFACT & FLASH_VENDMASK) |
 				(AMD_ID_LV160B & FLASH_TYPEMASK);
 			flash_info[i].size = FLASH_BANK_SIZE;
-			flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+			flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-			memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+			memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 			flashbase = PHYS_FLASH_1;
 			for (j = 0; j < flash_info[i].sector_count; j++) {
 				if (j == 0) {
@@ -128,8 +128,8 @@ unsigned long flash_init (void)
 	}
 
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE,
-		       CFG_FLASH_BASE + 0xffff, &flash_info[0]);
+		       CONFIG_SYS_FLASH_BASE + 0xffff, &flash_info[0]);
 
 	return size;
 }
@@ -177,7 +177,7 @@ int amd_flash_erase_sector(flash_info_t * info, int sector)
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
 			state = ERR_TIMOUT;
 		}
@@ -303,7 +303,7 @@ volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data)
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				state = ERR_TIMOUT;
 		}
 		if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK)))
@@ -390,7 +390,7 @@ int amd_flash_protect(flash_info_t * info,long sector,int prot)
 	return rc;
 }
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 
 int flash_real_protect(flash_info_t * info,long sector,int prot)
 {

board/BuS/EB+MCF-EV123/mii.c

@@ -1,304 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fec.h>
-#include <asm/immap.h>
-
-#include <config.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
-#undef MII_DEBUG
-#undef ET_DEBUG
-
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
-	if (setclear) {
-		MCFGPIO_PASPAR |= 0x0F00;
-		MCFGPIO_PEHLPAR = CFG_PEHLPAR;
-	} else {
-		MCFGPIO_PASPAR &= 0xF0FF;
-		MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR;
-	}
-	return 0;
-}
-
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-
-/* Make MII read/write commands for the FEC. */
-#define mk_mii_read(ADDR, REG)	(0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
-
-#define mk_mii_write(ADDR, REG, VAL)	(0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
-
-/* PHY identification */
-#define PHY_ID_LXT970		0x78100000	/* LXT970 */
-#define PHY_ID_LXT971		0x001378e0	/* LXT971 and 972 */
-#define PHY_ID_82555		0x02a80150	/* Intel 82555 */
-#define PHY_ID_QS6612		0x01814400	/* QS6612 */
-#define PHY_ID_AMD79C784	0x00225610	/* AMD 79C784 */
-#define PHY_ID_AMD79C874VC	0x0022561B	/* AMD 79C874 */
-#define PHY_ID_LSI80225		0x0016f870	/* LSI 80225 */
-#define PHY_ID_LSI80225B	0x0016f880	/* LSI 80225/B */
-#define PHY_ID_DP83848VV	0x20005C90	/* National 83848 */
-#define PHY_ID_DP83849		0x20005CA2	/* National 82849 */
-
-#define STR_ID_LXT970		"LXT970"
-#define STR_ID_LXT971		"LXT971"
-#define STR_ID_82555		"Intel82555"
-#define STR_ID_QS6612		"QS6612"
-#define STR_ID_AMD79C784	"AMD79C784"
-#define STR_ID_AMD79C874VC	"AMD79C874VC"
-#define STR_ID_LSI80225		"LSI80225"
-#define STR_ID_LSI80225B	"LSI80225/B"
-#define STR_ID_DP83848VV	"N83848"
-#define STR_ID_DP83849		"N83849"
-
-/****************************************************************************
- * mii_init -- Initialize the MII for MII command without ethernet
- * This function is a subset of eth_init
- ****************************************************************************
- */
-void mii_reset(struct fec_info_s *info)
-{
-	volatile fec_t *fecp = (fec_t *) (info->miibase);
-	int i;
-
-	fecp->ecr = FEC_ECR_RESET;
-	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
-		udelay(1);
-	}
-	if (i == FEC_RESET_DELAY) {
-		printf("FEC_RESET_DELAY timeout\n");
-	}
-}
-
-/* send command to phy using mii, wait for result */
-uint mii_send(uint mii_cmd)
-{
-	struct fec_info_s *info;
-	struct eth_device *dev;
-	volatile fec_t *ep;
-	uint mii_reply;
-	int j = 0;
-
-	/* retrieve from register structure */
-	dev = eth_get_dev();
-	info = dev->priv;
-
-	ep = (fec_t *) info->miibase;
-
-	ep->mmfr = mii_cmd;	/* command to phy */
-
-	/* wait for mii complete */
-	while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
-		udelay(1);
-		j++;
-	}
-	if (j >= MCFFEC_TOUT_LOOP) {
-		printf("MII not complete\n");
-		return -1;
-	}
-
-	mii_reply = ep->mmfr;	/* result from phy */
-	ep->eir = FEC_EIR_MII;	/* clear MII complete */
-#ifdef ET_DEBUG
-	printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
-	       __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
-#endif
-
-	return (mii_reply & 0xffff);	/* data read from phy */
-}
-#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
-
-#if defined(CFG_DISCOVER_PHY)
-int mii_discover_phy(struct eth_device *dev)
-{
-#define MAX_PHY_PASSES 11
-	struct fec_info_s *info = dev->priv;
-	int phyaddr, pass;
-	uint phyno, phytype;
-
-	if (info->phyname_init)
-		return info->phy_addr;
-
-	phyaddr = -1;		/* didn't find a PHY yet */
-	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
-		if (pass > 1) {
-			/* PHY may need more time to recover from reset.
-			 * The LXT970 needs 50ms typical, no maximum is
-			 * specified, so wait 10ms before try again.
-			 * With 11 passes this gives it 100ms to wake up.
-			 */
-			udelay(10000);	/* wait 10ms */
-		}
-
-		for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
-
-			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
-#ifdef ET_DEBUG
-			printf("PHY type 0x%x pass %d type\n", phytype, pass);
-#endif
-			if (phytype != 0xffff) {
-				phyaddr = phyno;
-				phytype <<= 16;
-				phytype |=
-				    mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
-
-				switch (phytype & 0xffffffff) {
-				case PHY_ID_AMD79C874VC:
-					strcpy(info->phy_name,
-					       STR_ID_AMD79C874VC);
-					info->phyname_init = 1;
-					break;
-				default:
-					strcpy(info->phy_name, "unknown");
-					info->phyname_init = 1;
-					break;
-				}
-
-#ifdef ET_DEBUG
-				printf("PHY @ 0x%x pass %d type ", phyno, pass);
-				switch (phytype & 0xffffffff) {
-				case PHY_ID_AMD79C874VC:
-					printf(STR_ID_AMD79C874VC);
-					break;
-				default:
-					printf("0x%08x\n", phytype);
-					break;
-				}
-#endif
-			}
-		}
-	}
-	if (phyaddr < 0)
-		printf("No PHY device found.\n");
-
-	return phyaddr;
-}
-#endif				/* CFG_DISCOVER_PHY */
-
-void mii_init(void) __attribute__((weak,alias("__mii_init")));
-
-void __mii_init(void)
-{
-	volatile fec_t *fecp;
-	struct fec_info_s *info;
-	struct eth_device *dev;
-	int miispd = 0, i = 0;
-	u16 autoneg = 0;
-
-	/* retrieve from register structure */
-	dev = eth_get_dev();
-	info = dev->priv;
-
-	fecp = (fec_t *) info->miibase;
-
-	fecpin_setclear(dev, 1);
-
-	mii_reset(info);
-
-	/* We use strictly polling mode only */
-	fecp->eimr = 0;
-
-	/* Clear any pending interrupt */
-	fecp->eir = 0xffffffff;
-
-	/* Set MII speed */
-	miispd = (gd->bus_clk / 1000000) / 5;
-	fecp->mscr = miispd << 1;
-
-	info->phy_addr = mii_discover_phy(dev);
-
-#define AUTONEGLINK		(PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
-	while (i < MCFFEC_TOUT_LOOP) {
-		autoneg = 0;
-		miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
-		i++;
-
-		if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
-			break;
-
-		udelay(500);
-	}
-	if (i >= MCFFEC_TOUT_LOOP) {
-		printf("Auto Negotiation not complete\n");
-	}
-
-	/* adapt to the half/full speed settings */
-	info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
-	info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
-}
-
-/*****************************************************************************
- * Read and write a MII PHY register, routines used by MII Utilities
- *
- * FIXME: These routines are expected to return 0 on success, but mii_send
- *	  does _not_ return an error code. Maybe 0xFFFF means error, i.e.
- *	  no PHY connected...
- *	  For now always return 0.
- * FIXME: These routines only work after calling eth_init() at least once!
- *	  Otherwise they hang in mii_send() !!! Sorry!
- *****************************************************************************/
-
-int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
-		       unsigned short *value)
-{
-	short rdreg;		/* register working value */
-
-#ifdef MII_DEBUG
-	printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
-#endif
-	rdreg = mii_send(mk_mii_read(addr, reg));
-
-	*value = rdreg;
-
-#ifdef MII_DEBUG
-	printf("0x%04x\n", *value);
-#endif
-
-	return 0;
-}
-
-int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
-			unsigned short value)
-{
-	short rdreg;		/* register working value */
-
-#ifdef MII_DEBUG
-	printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
-#endif
-
-	rdreg = mii_send(mk_mii_write(addr, reg, value));
-
-#ifdef MII_DEBUG
-	printf("0x%04x\n", value);
-#endif
-
-	return 0;
-}
-
-#endif				/* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

board/BuS/EB+MCF-EV123/u-boot.lds

@@ -63,7 +63,7 @@ SECTIONS
     lib_generic/zlib.o	(.text)
 
 /*    . = env_offset; */
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)

board/LEOX/elpt860/README.LEOX

@@ -106,7 +106,7 @@ version - print monitor version
 ?       - alias for 'help'
 
 ##################################################
-# Environment Variables (CFG_ENV_IS_IN_NVRAM)
+# Environment Variables (CONFIG_ENV_IS_IN_NVRAM)
 ##############################
 
 LEOX_elpt860: printenv

board/LEOX/elpt860/elpt860.c

@@ -138,23 +138,23 @@ const uint sdram_table[] = {
 
 /* ------------------------------------------------------------------------- */
 
-#define CFG_PC4    0x0800
+#define CONFIG_SYS_PC4    0x0800
 
-#define CFG_DS1    CFG_PC4
+#define CONFIG_SYS_DS1    CONFIG_SYS_PC4
 
 /*
  * Very early board init code (fpga boot, etc.)
  */
 int board_early_init_f (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	/*
 	 * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
 	 */
-	immr->im_ioport.iop_pcdat &= ~CFG_DS1;	/* PCDAT (DS1 = 0)                */
+	immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1;	/* PCDAT (DS1 = 0)                */
-	immr->im_ioport.iop_pcpar &= ~CFG_DS1;	/* PCPAR (0=general purpose I/O)  */
+	immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1;	/* PCPAR (0=general purpose I/O)  */
-	immr->im_ioport.iop_pcdir |= CFG_DS1;	/* PCDIR (I/O: 0=input, 1=output) */
+	immr->im_ioport.iop_pcdir |= CONFIG_SYS_DS1;	/* PCDIR (I/O: 0=input, 1=output) */
 
 	return (0);		/* success */
 }
@@ -181,7 +181,7 @@ int checkboard (void)
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size8, size9;
 	long int size_b0 = 0;
@@ -207,7 +207,7 @@ phys_size_t initdram (int board_type)
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
 	/*
 	 * The following value is used as an address (i.e. opcode) for
@@ -229,10 +229,10 @@ phys_size_t initdram (int board_type)
 	 * preliminary addresses - these have to be modified after the
 	 * SDRAM size has been determined.
 	 */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -252,7 +252,7 @@ phys_size_t initdram (int board_type)
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL,
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
 			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
 
 	udelay (1000);
@@ -260,7 +260,7 @@ phys_size_t initdram (int board_type)
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
 			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
 
 	if (size8 < size9) {	/* leave configuration at 9 columns       */
@@ -269,7 +269,7 @@ phys_size_t initdram (int board_type)
 	} else {		/* back to 8 columns                      */
 
 		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 		/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
 	}
@@ -282,22 +282,22 @@ phys_size_t initdram (int board_type)
 	 */
 	if (size_b0 < 0x02000000) {
 		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 		udelay (1000);
 	}
 
 	/*
 	 * Final mapping: map bigger bank first
 	 */
-	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 	{
 		unsigned long reg;
 
 		/* adjust refresh rate depending on SDRAM type, one bank */
 		reg = memctl->memc_mptpr;
-		reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+		reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 		memctl->memc_mptpr = reg;
 	}
 
@@ -319,7 +319,7 @@ phys_size_t initdram (int board_type)
 static long int
 dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -329,20 +329,20 @@ dram_size (long int mamr_value, long int *base, long int maxsize)
 
 /* ------------------------------------------------------------------------- */
 
-#define CFG_PA1     0x4000
+#define CONFIG_SYS_PA1     0x4000
-#define CFG_PA2     0x2000
+#define CONFIG_SYS_PA2     0x2000
 
-#define CFG_LBKs    (CFG_PA2 | CFG_PA1)
+#define CONFIG_SYS_LBKs    (CONFIG_SYS_PA2 | CONFIG_SYS_PA1)
 
 void reset_phy (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	/*
 	 * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
 	 *                                          and no AUI loopback
 	 */
-	immr->im_ioport.iop_padat &= ~CFG_LBKs;	/* PADAT (LBK eth 1&2 = 0)        */
+	immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs;	/* PADAT (LBK eth 1&2 = 0)        */
-	immr->im_ioport.iop_papar &= ~CFG_LBKs;	/* PAPAR (0=general purpose I/O)  */
+	immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs;	/* PAPAR (0=general purpose I/O)  */
-	immr->im_ioport.iop_padir |= CFG_LBKs;	/* PADIR (I/O: 0=input, 1=output) */
+	immr->im_ioport.iop_padir |= CONFIG_SYS_LBKs;	/* PADIR (I/O: 0=input, 1=output) */
 }

board/LEOX/elpt860/flash.c

@@ -33,7 +33,7 @@
 /*
 ** Note 1: In this file, you have to provide the following variable:
 ** ------
-**              flash_info_t    flash_info[CFG_MAX_FLASH_BANKS]
+**              flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS]
 ** 'flash_info_t' structure is defined into 'include/flash.h'
 ** and defined as extern into 'common/cmd_flash.c'
 **
@@ -61,11 +61,11 @@
 #include <mpc8xx.h>
 
 
-#ifndef	CFG_ENV_ADDR
+#ifndef	CONFIG_ENV_ADDR
-#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 #endif
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
  * Internal Functions
@@ -82,13 +82,13 @@ static int write_byte (flash_info_t *info, ulong dest, uchar data);
 unsigned long
 flash_init (void)
 {
-  volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+  volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
   volatile memctl8xx_t *memctl = &immap->im_memctl;
   unsigned long         size_b0;
   int i;
 
   /* Init: no FLASHes known */
-  for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+  for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
     {
       flash_info[i].flash_id = FLASH_UNKNOWN;
     }
@@ -105,28 +105,28 @@ flash_init (void)
     }
 
   /* Remap FLASH according to real size */
-  memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+  memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-  memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V;
+  memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V;
 
   /* Re-do sizing to get full correct info */
-  size_b0 = flash_get_size ((volatile unsigned char *)CFG_FLASH_BASE,
+  size_b0 = flash_get_size ((volatile unsigned char *)CONFIG_SYS_FLASH_BASE,
 			    &flash_info[0]);
 
-  flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+  flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
   /* monitor protection ON by default */
   flash_protect (FLAG_PROTECT_SET,
-		 CFG_MONITOR_BASE,
+		 CONFIG_SYS_MONITOR_BASE,
-		 CFG_MONITOR_BASE + monitor_flash_len-1,
+		 CONFIG_SYS_MONITOR_BASE + monitor_flash_len-1,
 		 &flash_info[0]);
 #endif
 
-#ifdef	CFG_ENV_IS_IN_FLASH
+#ifdef	CONFIG_ENV_IS_IN_FLASH
   /* ENV protection ON by default */
   flash_protect(FLAG_PROTECT_SET,
-		CFG_ENV_ADDR,
+		CONFIG_ENV_ADDR,
-		CFG_ENV_ADDR + CFG_ENV_SIZE-1,
+		CONFIG_ENV_ADDR + CONFIG_ENV_SIZE-1,
 		&flash_info[0]);
 #endif
 
@@ -383,7 +383,7 @@ flash_erase (flash_info_t  *info,
   addr = (volatile unsigned char *)(info->start[l_sect]);
   while ( (addr[0] & 0x80) != 0x80 )
     {
-      if ( (now = get_timer(start)) > CFG_FLASH_ERASE_TOUT )
+      if ( (now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT )
 	{
 	  printf ("Timeout\n");
 	  return ( 1 );
@@ -556,7 +556,7 @@ write_word (flash_info_t  *info,
   start = get_timer (0);
   while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) )
     {
-      if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
+      if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT )
 	{
 	  return (1);
 	}
@@ -602,7 +602,7 @@ write_byte (flash_info_t  *info,
   start = get_timer (0);
   while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) )
     {
-      if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
+      if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT )
 	{
 	  return (1);
 	}

board/LEOX/elpt860/u-boot.lds

@@ -77,7 +77,7 @@ SECTIONS
     lib_ppc/ticks.o			(.text)
 
     . = env_offset;
-    common/environment.o		(.text)
+    common/env_embedded.o		(.text)
 
     *(.text)
     *(.fixup)
@@ -147,6 +147,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/LEOX/elpt860/u-boot.lds.debug

@@ -70,7 +70,7 @@ SECTIONS
     lib_generic/crc32.o		(.text)
 
     . = env_offset;
-    common/environment.o	(.text)
+    common/env_embedded.o	(.text)
 
     *(.text)
     *(.fixup)

board/MAI/AmigaOneG3SE/AmigaOneG3SE.c

@@ -26,6 +26,7 @@
 #include <common.h>
 #include <command.h>
 #include <pci.h>
+#include <netdev.h>
 #include "articiaS.h"
 #include "memio.h"
 #include "via686.h"
@@ -111,3 +112,11 @@ void pci_init_board (void)
 	articiaS_pci_init ();
 #endif
 }
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_3COM)
+	eth_3com_initialize(bis);
+#endif
+	return 0;
+}

board/MAI/AmigaOneG3SE/cmd_boota.c

@@ -27,7 +27,7 @@ struct bootcode_block bblk;
 
 int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	unsigned char *load_address = (unsigned char *) CFG_LOAD_ADDR;
+	unsigned char *load_address = (unsigned char *) CONFIG_SYS_LOAD_ADDR;
 	unsigned char *base_address;
 	unsigned long offset;
 

board/MAI/AmigaOneG3SE/enet.c

@@ -28,6 +28,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <pci.h>
 

board/MAI/AmigaOneG3SE/flash.c

@@ -1,14 +1,14 @@
 #include <common.h>
 #include <flash.h>
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 unsigned long flash_init(void)
 {
     int i;
 
-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
     {
 	flash_info[i].flash_id = FLASH_UNKNOWN;
 	flash_info[i].sector_count = 0;

board/MAI/AmigaOneG3SE/flash_new.c

@@ -39,7 +39,7 @@
 #endif
 /*---------------------------------------------------------------------*/
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 static ulong flash_get_size (ulong addr, flash_info_t *info);
 static int flash_get_offsets (ulong base, flash_info_t *info);
@@ -80,7 +80,7 @@ unsigned long flash_init_old(void)
 {
     int i;
 
-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
     {
 	flash_info[i].flash_id = FLASH_UNKNOWN;
 	flash_info[i].sector_count = 0;
@@ -101,33 +101,33 @@ unsigned long flash_init (void)
 	flash_to_xd();
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].sector_count = 0;
 		flash_info[i].size = 0;
 	}
 
-	DEBUGF("\n## Get flash size @ 0x%08x\n", CFG_FLASH_BASE);
+	DEBUGF("\n## Get flash size @ 0x%08x\n", CONFIG_SYS_FLASH_BASE);
 
-	flash_size = flash_get_size (CFG_FLASH_BASE, flash_info);
+	flash_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info);
 
 	DEBUGF("## Flash bank size: %08lx\n", flash_size);
 
 	if (flash_size) {
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \
-    CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE
+    CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_MAX_SIZE
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE,
-			      CFG_MONITOR_BASE + monitor_flash_len - 1,
+			      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 			      &flash_info[0]);
 #endif
 
-#ifdef CFG_ENV_IS_IN_FLASH
+#ifdef CONFIG_ENV_IS_IN_FLASH
 		/* ENV protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_ENV_ADDR,
+			      CONFIG_ENV_ADDR,
-			      CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+			      CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
 			      &flash_info[0]);
 #endif
 
@@ -286,10 +286,10 @@ static ulong flash_get_size (ulong addr, flash_info_t *info)
 
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	if (! flash_get_offsets (addr, info)) {
@@ -418,10 +418,10 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
 	last  = start;
 	addr = info->start[l_sect];
 
-	DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT);
+	DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT);
 
 	while ((in8(addr) & 0x80) != 0x80) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			flash_reset (info->start[0]);
 			flash_to_mem();
@@ -562,7 +562,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 		/* data polling for D7 */
 		start = get_timer (0);
 		while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) {
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				flash_reset (addr);
 				flash_to_mem();
 				return (1);

board/MAI/AmigaOneG3SE/i8259.h

@@ -21,20 +21,20 @@
  * MA 02111-1307 USA
  */
 
-#define ICW1_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW1
+#define ICW1_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW1
-#define ICW1_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW1
+#define ICW1_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW1
-#define ICW2_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW2
+#define ICW2_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW2
-#define ICW2_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW2
+#define ICW2_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW2
-#define ICW3_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW3
+#define ICW3_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW3
-#define ICW3_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW3
+#define ICW3_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW3
-#define ICW4_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW4
+#define ICW4_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW4
-#define ICW4_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW4
+#define ICW4_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW4
-#define OCW1_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW1
+#define OCW1_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW1
-#define OCW1_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW1
+#define OCW1_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW1
-#define OCW2_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW2
+#define OCW2_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW2
-#define OCW2_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW2
+#define OCW2_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW2
-#define OCW3_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW3
+#define OCW3_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW3
-#define OCW3_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW3
+#define OCW3_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW3
 
 #define IMR_1   OCW1_1
 #define IMR_2   OCW1_2

board/MAI/AmigaOneG3SE/interrupts.c

@@ -119,12 +119,12 @@ int interrupt_init (void)
 #ifdef DEBUG
 	puts("interrupt_init: setting decrementer_count\n");
 #endif
-	decrementer_count = get_tbclk() / CFG_HZ;
+	decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
 
 #ifdef DEBUG
 	puts("interrupt_init: setting actual decremter\n");
 #endif
-	set_dec (get_tbclk() / CFG_HZ);
+	set_dec (get_tbclk() / CONFIG_SYS_HZ);
 
 #ifdef DEBUG
 	puts("interrupt_init: clearing external interrupt table\n");

board/MAI/AmigaOneG3SE/ps2kbd.c

@@ -214,7 +214,7 @@ int isa_kbd_init (void)
 	}
 }
 
-#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE
+#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 extern int overwrite_console (void);
 #else
 int overwrite_console (void)
@@ -492,22 +492,22 @@ unsigned char handle_kbd_event (void)
  */
 unsigned char kbd_read_status(void)
 {
-	return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
+	return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
 }
 
 unsigned char kbd_read_input(void)
 {
-	return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
+	return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
 }
 
 void kbd_write_command(unsigned char cmd)
 {
-	out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
 }
 
 void kbd_write_output(unsigned char data)
 {
-	out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
 }
 
 int kbd_read_data(void)

board/MAI/AmigaOneG3SE/serial.c

@@ -6,7 +6,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CFG_NS16550
+#ifndef CONFIG_SYS_NS16550
 static uint32 ComPort1;
 
 uint16 SerialEcho = 1;
@@ -147,8 +147,8 @@ void serial_debug_putc (int c)
 
 #else
 
-const NS16550_t Com0 = (NS16550_t) CFG_NS16550_COM1;
+const NS16550_t Com0 = (NS16550_t) CONFIG_SYS_NS16550_COM1;
-const NS16550_t Com1 = (NS16550_t) CFG_NS16550_COM2;
+const NS16550_t Com1 = (NS16550_t) CONFIG_SYS_NS16550_COM2;
 
 int serial_init (void)
 {

board/MAI/AmigaOneG3SE/u-boot.lds

@@ -62,7 +62,7 @@ SECTIONS
     cpu/74xx_7xx/start.o	(.text)
 /* store the environment in a seperate sector in the boot flash */
 /*    . = env_offset; */
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)

board/MAI/AmigaOneG3SE/usb_uhci.c

@@ -627,7 +627,7 @@ int usb_lowlevel_init(void)
 	pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr);
 	USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr);
 	usb_base_addr&=0xFFFFFFF0;
-	usb_base_addr+=CFG_ISA_IO_BASE_ADDRESS;
+	usb_base_addr+=CONFIG_SYS_ISA_IO_BASE_ADDRESS;
 	rh.devnum = 0;
 	usb_init_skel();
 	reset_hc();
@@ -801,7 +801,7 @@ int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 	unsigned short wIndex;
 	unsigned short wLength;
 
-	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+	if (usb_pipeint(pipe)) {
 		printf("Root-Hub submit IRQ: NOT implemented\n");
 #if 0
 		uhci->rh.urb = urb;

board/Marvell/common/bootseq.txt

@@ -88,7 +88,7 @@ in_flash:
 		    nothing
 		mem_malloc_init
 		malloc_bin_reloc
-		spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM)
+		spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
 		env_relocated
 		misc_init_r(bd): (board/evb64260/evb64260.c)
 		    mpsc_init2

board/Marvell/common/flash.c

@@ -48,7 +48,7 @@
 int flash_erase_intel (flash_info_t * info, int s_first, int s_last);
 int write_word_intel (bank_addr_t addr, bank_word_t value);
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -68,14 +68,14 @@ unsigned long flash_init (void)
 	unsigned long base, flash_size;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* the boot flash */
-	base = CFG_FLASH_BASE;
+	base = CONFIG_SYS_FLASH_BASE;
 	size_b0 =
-		flash_get_size (CFG_BOOT_FLASH_WIDTH, (vu_long *) base,
+		flash_get_size (CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *) base,
 				&flash_info[0]);
 
 	printf ("[%ldkB@%lx] ", size_b0 / 1024, base);
@@ -84,11 +84,11 @@ unsigned long flash_init (void)
 		printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b0, size_b0 << 20);
 	}
 
-	base = memoryGetDeviceBaseAddress (CFG_EXTRA_FLASH_DEVICE);
+	base = memoryGetDeviceBaseAddress (CONFIG_SYS_EXTRA_FLASH_DEVICE);
 /*	base = memoryGetDeviceBaseAddress(DEV_CS3_BASE_ADDR);*/
-	for (i = 1; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		unsigned long size =
-			flash_get_size (CFG_EXTRA_FLASH_WIDTH,
+			flash_get_size (CONFIG_SYS_EXTRA_FLASH_WIDTH,
 					(vu_long *) base, &flash_info[i]);
 
 		printf ("[%ldMB@%lx] ", size >> 20, base);
@@ -617,7 +617,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 							/* has the timeout limit been reached? */
 							if (get_timer (start)
 							    >
-							    CFG_FLASH_ERASE_TOUT)
+							    CONFIG_SYS_FLASH_ERASE_TOUT)
 							{
 								/* timeout limit reached */
 								printf ("Time out limit reached erasing sector at address %08lx\n", info->start[sect]);
@@ -776,7 +776,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	addr = (volatile unsigned char *) (info->start[l_sect]);
 	/* broken for 2x16: TODO */
 	while ((addr[0] & 0x80) != 0x80) {
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -956,7 +956,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)
 				{
 					/* has the timeout limit been reached? */
 					if (get_timer (start) >
-					    CFG_FLASH_WRITE_TOUT) {
+					    CONFIG_SYS_FLASH_WRITE_TOUT) {
 						/* timeout limit reached */
 						printf ("Time out limit reached programming address %08lx with data %08lx\n", dest, data);
 						/* reset the flash */
@@ -1064,7 +1064,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}

board/Marvell/common/i2c.c

@@ -48,7 +48,7 @@ static void i2c_init (int speed, int slaveaddr)
 	unsigned int actualN = 0, actualM = 0;
 	unsigned int control, status;
 	unsigned int minMargin = 0xffffffff;
-	unsigned int tclk = CFG_TCLK;
+	unsigned int tclk = CONFIG_SYS_TCLK;
 	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
 
 	DP (puts ("i2c_init\n"));
@@ -372,7 +372,7 @@ i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
 	  int len)
 {
 	uchar status = 0;
-	unsigned int i2cFreq = CFG_I2C_SPEED;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
 
 	DP (puts ("i2c_read\n"));
 
@@ -447,7 +447,7 @@ i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
 	   int len)
 {
 	uchar status = 0;
-	unsigned int i2cFreq = CFG_I2C_SPEED;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
 
 	DP (puts ("i2c_write\n"));
 
@@ -500,7 +500,7 @@ int i2c_probe (uchar chip)
 	unsigned int i2c_status;
 #endif
 	uchar status = 0;
-	unsigned int i2cFreq = CFG_I2C_SPEED;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
 
 	DP (puts ("i2c_probe\n"));
 

board/Marvell/common/intel_flash.c

@@ -152,7 +152,7 @@ int write_word_intel (bank_addr_t addr, bank_word_t value)
 	/* data polling for D7 */
 	start = get_timer (0);
 	do {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			retval = 1;
 			goto done;
 		}
@@ -227,7 +227,7 @@ int flash_erase_intel (flash_info_t * info, int s_first, int s_last)
 			do {
 				now = get_timer (start);
 
-				if (now - estart > CFG_FLASH_ERASE_TOUT) {
+				if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout (sect %d)\n", sect);
 					haderr = 1;
 					break;

board/Marvell/common/intel_flash.h

@@ -68,7 +68,7 @@
 /* ID and Lock Configuration */
 #define CHIP_RD_ID_LOCK		0x01		/* Bit 0 of each byte */
 #define CHIP_RD_ID_MAN		0x89		/* Manufacturer code = 0x89 */
-#define CHIP_RD_ID_DEV		CFG_FLASH_ID
+#define CHIP_RD_ID_DEV		CONFIG_SYS_FLASH_ID
 
 /* dimensions */
 #define CHIP_WIDTH		2		/* chips are in 16 bit mode */

board/Marvell/common/misc.S

@@ -16,7 +16,7 @@
 board_relocate_rom:
 	mflr	r7
 	/* update the location of the GT registers */
-	lis	r11, CFG_GT_REGS@h
+	lis	r11, CONFIG_SYS_GT_REGS@h
 	/* if we're using ECC, we must use the DMA engine to copy ourselves */
 	bl	start_idma_transfer_0
 	bl	wait_for_idma_0
@@ -29,12 +29,12 @@ board_relocate_rom:
 board_init_ecc:
 	mflr	r7
 	/* NOTE: r10 still contains the location we've been relocated to
-	 * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
+	 * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
 
 	/* now that we're running from ram, init the rest of main memory
 	 * for ECC use */
-	lis	r8, CFG_MONITOR_LEN@h
+	lis	r8, CONFIG_SYS_MONITOR_LEN@h
-	ori	r8, r8, CFG_MONITOR_LEN@l
+	ori	r8, r8, CONFIG_SYS_MONITOR_LEN@l
 
 	divw	r3, r10, r8
 
@@ -120,15 +120,15 @@ stop_idma_engine_0:
 	blr
 #endif
 
-#ifdef CFG_BOARD_ASM_INIT
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
 	/* NOTE: trashes r3-r7 */
 	.globl board_asm_init
 board_asm_init:
 	/* just move the GT registers to where they belong */
-	lis	r3, CFG_DFL_GT_REGS@h
+	lis	r3, CONFIG_SYS_DFL_GT_REGS@h
-	ori	r3, r3, CFG_DFL_GT_REGS@l
+	ori	r3, r3, CONFIG_SYS_DFL_GT_REGS@l
-	lis	r4, CFG_GT_REGS@h
+	lis	r4, CONFIG_SYS_GT_REGS@h
-	ori	r4, r4, CFG_GT_REGS@l
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
 	li	r5, INTERNAL_SPACE_DECODE
 
 	/* test to see if we've already moved */

board/Marvell/common/ns16550.c

@@ -1,7 +1,7 @@
 /*
  * COM1 NS16550 support
  * originally from linux source (arch/ppc/boot/ns16550.c)
- * modified to use CFG_ISA_MEM and new defines
+ * modified to use CONFIG_SYS_ISA_MEM and new defines
  *
  * further modified by Josh Huber <huber@mclx.com> to support
  * the DUART on the Galileo Eval board. (db64360)
@@ -13,8 +13,8 @@
 #ifdef ZUMA_NTL
 /* no 16550 device */
 #else
-const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_DUART_IO + 0),
+const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0),
-	(NS16550_t) (CFG_DUART_IO + 0x20)
+	(NS16550_t) (CONFIG_SYS_DUART_IO + 0x20)
 };
 
 volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)

board/Marvell/common/ns16550.h

@@ -2,7 +2,7 @@
  * NS16550 Serial Port
  * originally from linux source (arch/ppc/boot/ns16550.h)
  * modified slightly to
- * have addresses as offsets from CFG_ISA_BASE
+ * have addresses as offsets from CONFIG_SYS_ISA_BASE
  * added a few more definitions
  * added prototypes for ns16550.c
  * reduced no of com ports to 2

board/Marvell/common/serial.c

@@ -52,17 +52,17 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int serial_init (void)
 {
-#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
 	int clock_divisor = 230400 / gd->baudrate;
 #endif
 
 	mpsc_init (gd->baudrate);
 
 	/* init the DUART chans so that KGDB in the kernel can use them */
-#ifdef CFG_INIT_CHAN1
+#ifdef CONFIG_SYS_INIT_CHAN1
 	NS16550_reinit (COM_PORTS[0], clock_divisor);
 #endif
-#ifdef CFG_INIT_CHAN2
+#ifdef CONFIG_SYS_INIT_CHAN2
 	NS16550_reinit (COM_PORTS[1], clock_divisor);
 #endif
 	return (0);
@@ -97,10 +97,10 @@ int serial_init (void)
 {
 	int clock_divisor = 230400 / gd->baudrate;
 
-#ifdef CFG_INIT_CHAN1
+#ifdef CONFIG_SYS_INIT_CHAN1
 	(void) NS16550_init (0, clock_divisor);
 #endif
-#ifdef CFG_INIT_CHAN2
+#ifdef CONFIG_SYS_INIT_CHAN2
 	(void) NS16550_init (1, clock_divisor);
 #endif
 	return (0);
@@ -109,29 +109,29 @@ int serial_init (void)
 void serial_putc (const char c)
 {
 	if (c == '\n')
-		NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r');
+		NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
 
-	NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c);
+	NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
 }
 
 int serial_getc (void)
 {
-	return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]);
+	return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
 }
 
 int serial_tstc (void)
 {
-	return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]);
+	return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
 }
 
 void serial_setbrg (void)
 {
 	int clock_divisor = 230400 / gd->baudrate;
 
-#ifdef CFG_INIT_CHAN1
+#ifdef CONFIG_SYS_INIT_CHAN1
 	NS16550_reinit (COM_PORTS[0], clock_divisor);
 #endif
-#ifdef CFG_INIT_CHAN2
+#ifdef CONFIG_SYS_INIT_CHAN2
 	NS16550_reinit (COM_PORTS[1], clock_divisor);
 #endif
 }

board/Marvell/db64360/db64360.c

@@ -33,6 +33,7 @@
 #include "../include/pci.h"
 #include "../include/mv_gen_reg.h"
 #include <net.h>
+#include <netdev.h>
 
 #include "eth.h"
 #include "mpsc.h"
@@ -54,7 +55,7 @@
 /* ------------------------------------------------------------------------- */
 
 /* this is the current GT register space location */
-/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
 
 /* Unfortunately, we cant change it while we are in flash, so we initialize it
  * to the "final" value. This means that any debug_led calls before
@@ -63,7 +64,7 @@
  */
 
 void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
 int display_mem_map (void);
 
 /* ------------------------------------------------------------------------- */
@@ -126,7 +127,7 @@ static void gt_pci_config (void)
 
 		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 
 	}
 	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
@@ -135,7 +136,7 @@ static void gt_pci_config (void)
 
 		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 	}
 
 	/* Enable master */
@@ -153,21 +154,21 @@ static void gt_pci_config (void)
 	/* ronen- add write to pci remap registers for 64460.
 	   in 64360 when writing to pci base go and overide remap automaticaly,
 	   in 64460 it doesn't */
-	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
 
 	/* PCI interface settings */
 	/* Timeout set to retry forever */
@@ -183,7 +184,7 @@ static void gt_pci_config (void)
 	for (stat = 0; stat <= PCI_HOST1; stat++)
 		pciWriteConfigReg (stat,
 				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
-				   SELF, CFG_GT_REGS);
+				   SELF, CONFIG_SYS_GT_REGS);
 #endif
 
 }
@@ -199,7 +200,7 @@ static void gt_cpu_config (void)
 	tmp = GTREGREAD (CPU_CONFIGURATION);
 
 	/* set the SINGLE_CPU bit  see MV64360 P.399 */
-#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
 	tmp |= CPU_CONF_SINGLE_CPU;
 #endif
 
@@ -250,7 +251,7 @@ int board_early_init_f (void)
 	 * it last time. (huber)
 	 */
 
-	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
 
 	/* No PCI in first release of Port To_do: enable it. */
 #ifdef CONFIG_PCI
@@ -296,56 +297,56 @@ int board_early_init_f (void)
 	 * on-board sram on the eval board, and updates the correct
 	 * registers to boot from the sram. (device0)
 	 */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
 		sram_boot = 1;
 	if (!sram_boot)
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
 
-	memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
-	memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
-	memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
 
 
 	/* configure device timing */
-#ifdef CFG_DEV0_PAR		/* set port parameters for SRAM device module access */
+#ifdef CONFIG_SYS_DEV0_PAR		/* set port parameters for SRAM device module access */
 	if (!sram_boot)
-		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
+		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
 #endif
 
-#ifdef CFG_DEV1_PAR		/* set port parameters for RTC device module access */
+#ifdef CONFIG_SYS_DEV1_PAR		/* set port parameters for RTC device module access */
-	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
 #endif
-#ifdef CFG_DEV2_PAR		/* set port parameters for DUART device module access */
+#ifdef CONFIG_SYS_DEV2_PAR		/* set port parameters for DUART device module access */
-	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
 #endif
 
-#ifdef CFG_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
 	/* detect if we are booting from the 32 bit flash */
 	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
 		/* 32 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
-			      CFG_32BIT_BOOT_PAR);
+			      CONFIG_SYS_32BIT_BOOT_PAR);
 	} else {
 		/* 8 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 	}
 #else
 	/* 8 bit boot flash only */
-/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
 #endif
 
 
 	gt_cpu_config ();
 
 	/* MPP setup */
-	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
-	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
-	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
-	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
 
-	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
 	DEBUG_LED0_ON ();
 	DEBUG_LED1_ON ();
 	DEBUG_LED2_ON ();
@@ -358,7 +359,7 @@ int board_early_init_f (void)
 int misc_init_r ()
 {
 	icache_enable ();
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
 	l2cache_enable ();
 #endif
 #ifdef CONFIG_MPSC
@@ -379,9 +380,9 @@ void after_reloc (ulong dest_addr, gd_t * gd)
 	/* check to see if we booted from the sram.  If so, move things
 	 * back to the way they should be. (we're running from main
 	 * memory at this point now */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
-		memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
+		memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
 	}
 	display_mem_map ();
 	/* now, jump to the main ppcboot board init code */
@@ -401,7 +402,7 @@ int checkboard (void)
 {
 	int l_type = 0;
 
-	printf ("BOARD: %s\n", CFG_BOARD_NAME);
+	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
 	return (l_type);
 }
 
@@ -414,34 +415,34 @@ void debug_led (int led, int mode)
 	if (mode == 1) {
 		switch (led) {
 		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x08000);
 			break;
 
 		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x0c000);
 			break;
 
 		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x10000);
 			break;
 		}
 	} else if (mode == 0) {
 		switch (led) {
 		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x14000);
 			break;
 
 		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x18000);
 			break;
 
 		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x1c000);
 			break;
 		}
@@ -512,7 +513,7 @@ int display_mem_map (void)
 
 /* DRAM check routines copied from gw8260 */
 
-#if defined (CFG_DRAM_TEST)
+#if defined (CONFIG_SYS_DRAM_TEST)
 
 /*********************************************************************/
 /* NAME:  move64() -  moves a double word (64-bit)		     */
@@ -543,7 +544,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
 }
 
 
-#if defined (CFG_DRAM_TEST_DATA)
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
 
 unsigned long long pattern[] = {
 	0xaaaaaaaaaaaaaaaaULL,
@@ -606,7 +607,7 @@ unsigned long long pattern[] = {
 /*********************************************************************/
 int mem_test_data (void)
 {
-	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
 	unsigned long long temp64 = 0;
 	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
 	int i;
@@ -633,9 +634,9 @@ int mem_test_data (void)
 
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_DATA */
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
 
-#if defined (CFG_DRAM_TEST_ADDRESS)
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
 /*********************************************************************/
 /* NAME:  mem_test_address() -	test address lines		     */
 /*								     */
@@ -660,8 +661,8 @@ int mem_test_data (void)
 int mem_test_address (void)
 {
 	volatile unsigned int *pmem =
-		(volatile unsigned int *) CFG_MEMTEST_START;
+		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
-	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
 	unsigned int i;
 
 	/* write address to each location */
@@ -678,9 +679,9 @@ int mem_test_address (void)
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_ADDRESS */
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
 
-#if defined (CFG_DRAM_TEST_WALK)
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
 /*********************************************************************/
 /* NAME:   mem_march() -  memory march				     */
 /*								     */
@@ -738,7 +739,7 @@ int mem_march (volatile unsigned long long *base,
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_WALK */
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
 
 /*********************************************************************/
 /* NAME:   mem_test_walk() -  a simple walking ones test	     */
@@ -770,8 +771,8 @@ int mem_test_walk (void)
 {
 	unsigned long long mask;
 	volatile unsigned long long *pmem =
-		(volatile unsigned long long *) CFG_MEMTEST_START;
+		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
-	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
 
 	unsigned int i;
 
@@ -847,9 +848,9 @@ int testdram (void)
 /*    runwalk = 0; */
 
 	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
 	}
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
 	if (rundata == 1) {
 		printf ("Test DATA ...  ");
 		if (mem_test_data () == 1) {
@@ -859,7 +860,7 @@ int testdram (void)
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
 	if (runaddress == 1) {
 		printf ("Test ADDRESS ...  ");
 		if (mem_test_address () == 1) {
@@ -869,7 +870,7 @@ int testdram (void)
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
 	if (runwalk == 1) {
 		printf ("Test WALKING ONEs ...  ");
 		if (mem_test_walk () == 1) {
@@ -885,7 +886,7 @@ int testdram (void)
 	return 0;
 
 }
-#endif /* CFG_DRAM_TEST */
+#endif /* CONFIG_SYS_DRAM_TEST */
 
 /* ronen - the below functions are used by the bootm function           */
 /*  - we map the base register to fbe00000 (same mapping as in the LSP) */
@@ -924,8 +925,13 @@ void board_prebootm_init ()
 /* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */
 
 /* Relocate MV64360 internal regs */
-	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
+	my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
 
 	icache_disable ();
 	dcache_disable ();
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/Marvell/db64360/mpsc.c

@@ -426,7 +426,7 @@ void mpsc_sdma_init (void)
 			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
 
 /* Setup MPSC internal address space base address	*/
-	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
 
 /* no high address remap*/
 	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
@@ -516,9 +516,9 @@ int galbrg_set_baudrate (int channel, int rate)
 
 #ifdef ZUMA_NTL
 	/* from tclk */
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #else
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #endif
 
 	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */

board/Marvell/db64360/pci.c

@@ -52,13 +52,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host)
 		printf ("PCI %d bus mode: Conventional PCI\n", host);
 		break;
 	case 1:
-		printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
+		printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
 		break;
 	case 2:
-		printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
+		printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
 		break;
 	case 3:
-		printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
+		printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
 		break;
 	default:
 		printf ("Unknown BUS %d\n", mode);
@@ -859,14 +859,14 @@ void pci_init_board (void)
 
 	/* PCI memory space */
 	pci_set_region (pci0_hose.regions + 0,
-			CFG_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
-			CFG_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
-			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci0_hose.regions + 1,
-			CFG_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
-			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci0_hose,
 		     pci_hose_read_config_byte_via_dword,
@@ -901,14 +901,14 @@ void pci_init_board (void)
 
 	/* PCI memory space */
 	pci_set_region (pci1_hose.regions + 0,
-			CFG_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
-			CFG_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
-			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci1_hose.regions + 1,
-			CFG_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
-			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci1_hose,
 		     pci_hose_read_config_byte_via_dword,

board/Marvell/db64360/sdram_init.c

@@ -312,7 +312,7 @@ return 0;
 	} else
 		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
 
-#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
+#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
 
 	for (i = 0; i <= 127; i++) {
 		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
@@ -690,16 +690,16 @@ return 0;
 						if ((dimmInfo->
 						     minimumCycleTimeAtMaxCasLatancy_LoP
 						     <
-						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						    ||
 						    ((dimmInfo->
 						      minimumCycleTimeAtMaxCasLatancy_LoP
 						      ==
-						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						     && (dimmInfo->
 							 minimumCycleTimeAtMaxCasLatancy_RoP
 							 <
-							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
 						{
 							dimmInfo->
 								maxClSupported_DDR
@@ -714,16 +714,16 @@ return 0;
 						if ((dimmInfo->
 						     minimumCycleTimeAtMaxCasLatancy_LoP
 						     >
-						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						    ||
 						    ((dimmInfo->
 						      minimumCycleTimeAtMaxCasLatancy_LoP
 						      ==
-						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						     && (dimmInfo->
 							 minimumCycleTimeAtMaxCasLatancy_RoP
 							 >
-							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
 						{
 							printf ("*********************************************************\n");
 							printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
@@ -1290,37 +1290,37 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
 	case 0x0:
 	case 0x80:		/* refresh period is 15.625 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ)
+			(unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_HZ)
 					/ (float) 1000000.0);
 		break;
 	case 0x1:
 	case 0x81:		/* refresh period is 3.9 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x2:
 	case 0x82:		/* refresh period is 7.8 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x3:
 	case 0x83:		/* refresh period is 31.3 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x4:
 	case 0x84:		/* refresh period is 62.5 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x5:
 	case 0x85:		/* refresh period is 125 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 125 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	default:		/* refresh period undefined */
@@ -1807,7 +1807,7 @@ phys_size_t initdram (int board_type)
 
 	printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
 
-	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
 		/* skip over banks that are not populated */
 		if (!checkbank[bank_no])
 			continue;

board/Marvell/db64360/u-boot.lds

@@ -60,7 +60,7 @@ SECTIONS
 
 /* store the environment in a seperate sector in the boot flash */
 /*    . = env_offset; */
-/*    common/environment.o(.text) */
+/*    common/env_embedded.o(.text) */
 
     *(.text)
     *(.fixup)
@@ -131,6 +131,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/Marvell/db64460/db64460.c

@@ -33,6 +33,7 @@
 #include "../include/pci.h"
 #include "../include/mv_gen_reg.h"
 #include <net.h>
+#include <netdev.h>
 
 #include "eth.h"
 #include "mpsc.h"
@@ -54,7 +55,7 @@
 /* ------------------------------------------------------------------------- */
 
 /* this is the current GT register space location */
-/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
 
 /* Unfortunately, we cant change it while we are in flash, so we initialize it
  * to the "final" value. This means that any debug_led calls before
@@ -63,7 +64,7 @@
  */
 
 void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
 int display_mem_map (void);
 
 /* ------------------------------------------------------------------------- */
@@ -126,7 +127,7 @@ static void gt_pci_config (void)
 
 		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 
 	}
 	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
@@ -135,7 +136,7 @@ static void gt_pci_config (void)
 
 		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 	}
 
 	/* Enable master */
@@ -153,21 +154,21 @@ static void gt_pci_config (void)
 	/* ronen- add write to pci remap registers for 64460.
 	   in 64360 when writing to pci base go and overide remap automaticaly,
 	   in 64460 it doesn't */
-	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
 
 	/* PCI interface settings */
 	/* Timeout set to retry forever */
@@ -183,7 +184,7 @@ static void gt_pci_config (void)
 	for (stat = 0; stat <= PCI_HOST1; stat++)
 		pciWriteConfigReg (stat,
 				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
-				   SELF, CFG_GT_REGS);
+				   SELF, CONFIG_SYS_GT_REGS);
 #endif
 
 }
@@ -199,7 +200,7 @@ static void gt_cpu_config (void)
 	tmp = GTREGREAD (CPU_CONFIGURATION);
 
 	/* set the SINGLE_CPU bit  see MV64460 P.399 */
-#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
 	tmp |= CPU_CONF_SINGLE_CPU;
 #endif
 
@@ -250,7 +251,7 @@ int board_early_init_f (void)
 	 * it last time. (huber)
 	 */
 
-	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
 
 	/* No PCI in first release of Port To_do: enable it. */
 #ifdef CONFIG_PCI
@@ -296,56 +297,56 @@ int board_early_init_f (void)
 	 * on-board sram on the eval board, and updates the correct
 	 * registers to boot from the sram. (device0)
 	 */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
 		sram_boot = 1;
 	if (!sram_boot)
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
 
-	memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
-	memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
-	memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
 
 
 	/* configure device timing */
-#ifdef CFG_DEV0_PAR		/* set port parameters for SRAM device module access */
+#ifdef CONFIG_SYS_DEV0_PAR		/* set port parameters for SRAM device module access */
 	if (!sram_boot)
-		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
+		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
 #endif
 
-#ifdef CFG_DEV1_PAR		/* set port parameters for RTC device module access */
+#ifdef CONFIG_SYS_DEV1_PAR		/* set port parameters for RTC device module access */
-	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
 #endif
-#ifdef CFG_DEV2_PAR		/* set port parameters for DUART device module access */
+#ifdef CONFIG_SYS_DEV2_PAR		/* set port parameters for DUART device module access */
-	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
 #endif
 
-#ifdef CFG_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
 	/* detect if we are booting from the 32 bit flash */
 	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
 		/* 32 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
-			      CFG_32BIT_BOOT_PAR);
+			      CONFIG_SYS_32BIT_BOOT_PAR);
 	} else {
 		/* 8 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 	}
 #else
 	/* 8 bit boot flash only */
-/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
 #endif
 
 
 	gt_cpu_config ();
 
 	/* MPP setup */
-	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
-	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
-	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
-	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
 
-	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
 	DEBUG_LED0_ON ();
 	DEBUG_LED1_ON ();
 	DEBUG_LED2_ON ();
@@ -358,7 +359,7 @@ int board_early_init_f (void)
 int misc_init_r ()
 {
 	icache_enable ();
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
 	l2cache_enable ();
 #endif
 #ifdef CONFIG_MPSC
@@ -379,9 +380,9 @@ void after_reloc (ulong dest_addr, gd_t * gd)
 	/* check to see if we booted from the sram.  If so, move things
 	 * back to the way they should be. (we're running from main
 	 * memory at this point now */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
-		memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
+		memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
 	}
 	display_mem_map ();
 	/* now, jump to the main ppcboot board init code */
@@ -401,7 +402,7 @@ int checkboard (void)
 {
 	int l_type = 0;
 
-	printf ("BOARD: %s\n", CFG_BOARD_NAME);
+	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
 	return (l_type);
 }
 
@@ -414,34 +415,34 @@ void debug_led (int led, int mode)
 	if (mode == 1) {
 		switch (led) {
 		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x08000);
 			break;
 
 		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x0c000);
 			break;
 
 		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x10000);
 			break;
 		}
 	} else if (mode == 0) {
 		switch (led) {
 		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x14000);
 			break;
 
 		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x18000);
 			break;
 
 		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x1c000);
 			break;
 		}
@@ -512,7 +513,7 @@ int display_mem_map (void)
 
 /* DRAM check routines copied from gw8260 */
 
-#if defined (CFG_DRAM_TEST)
+#if defined (CONFIG_SYS_DRAM_TEST)
 
 /*********************************************************************/
 /* NAME:  move64() -  moves a double word (64-bit)		     */
@@ -543,7 +544,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
 }
 
 
-#if defined (CFG_DRAM_TEST_DATA)
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
 
 unsigned long long pattern[] = {
 	0xaaaaaaaaaaaaaaaaULL,
@@ -606,7 +607,7 @@ unsigned long long pattern[] = {
 /*********************************************************************/
 int mem_test_data (void)
 {
-	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
 	unsigned long long temp64 = 0;
 	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
 	int i;
@@ -633,9 +634,9 @@ int mem_test_data (void)
 
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_DATA */
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
 
-#if defined (CFG_DRAM_TEST_ADDRESS)
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
 /*********************************************************************/
 /* NAME:  mem_test_address() -	test address lines		     */
 /*								     */
@@ -660,8 +661,8 @@ int mem_test_data (void)
 int mem_test_address (void)
 {
 	volatile unsigned int *pmem =
-		(volatile unsigned int *) CFG_MEMTEST_START;
+		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
-	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
 	unsigned int i;
 
 	/* write address to each location */
@@ -678,9 +679,9 @@ int mem_test_address (void)
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_ADDRESS */
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
 
-#if defined (CFG_DRAM_TEST_WALK)
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
 /*********************************************************************/
 /* NAME:   mem_march() -  memory march				     */
 /*								     */
@@ -738,7 +739,7 @@ int mem_march (volatile unsigned long long *base,
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_WALK */
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
 
 /*********************************************************************/
 /* NAME:   mem_test_walk() -  a simple walking ones test	     */
@@ -770,8 +771,8 @@ int mem_test_walk (void)
 {
 	unsigned long long mask;
 	volatile unsigned long long *pmem =
-		(volatile unsigned long long *) CFG_MEMTEST_START;
+		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
-	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
 
 	unsigned int i;
 
@@ -847,9 +848,9 @@ int testdram (void)
 /*    runwalk = 0; */
 
 	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
 	}
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
 	if (rundata == 1) {
 		printf ("Test DATA ...  ");
 		if (mem_test_data () == 1) {
@@ -859,7 +860,7 @@ int testdram (void)
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
 	if (runaddress == 1) {
 		printf ("Test ADDRESS ...  ");
 		if (mem_test_address () == 1) {
@@ -869,7 +870,7 @@ int testdram (void)
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
 	if (runwalk == 1) {
 		printf ("Test WALKING ONEs ...  ");
 		if (mem_test_walk () == 1) {
@@ -885,7 +886,7 @@ int testdram (void)
 	return 0;
 
 }
-#endif /* CFG_DRAM_TEST */
+#endif /* CONFIG_SYS_DRAM_TEST */
 
 /* ronen - the below functions are used by the bootm function           */
 /*  - we map the base register to fbe00000 (same mapping as in the LSP) */
@@ -924,8 +925,13 @@ void board_prebootm_init ()
 	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00);
 
 /* Relocate MV64460 internal regs */
-	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
+	my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
 
 	icache_disable ();
 	dcache_disable ();
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/Marvell/db64460/mpsc.c

@@ -426,7 +426,7 @@ void mpsc_sdma_init (void)
 			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
 
 /* Setup MPSC internal address space base address	*/
-	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
 
 /* no high address remap*/
 	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
@@ -516,9 +516,9 @@ int galbrg_set_baudrate (int channel, int rate)
 
 #ifdef ZUMA_NTL
 	/* from tclk */
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #else
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #endif
 
 	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */

board/Marvell/db64460/pci.c

@@ -52,13 +52,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host)
 		printf ("PCI %d bus mode: Conventional PCI\n", host);
 		break;
 	case 1:
-		printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
+		printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
 		break;
 	case 2:
-		printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
+		printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
 		break;
 	case 3:
-		printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
+		printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
 		break;
 	default:
 		printf ("Unknown BUS %d\n", mode);
@@ -859,14 +859,14 @@ void pci_init_board (void)
 
 	/* PCI memory space */
 	pci_set_region (pci0_hose.regions + 0,
-			CFG_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
-			CFG_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
-			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci0_hose.regions + 1,
-			CFG_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
-			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci0_hose,
 		     pci_hose_read_config_byte_via_dword,
@@ -901,14 +901,14 @@ void pci_init_board (void)
 
 	/* PCI memory space */
 	pci_set_region (pci1_hose.regions + 0,
-			CFG_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
-			CFG_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
-			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci1_hose.regions + 1,
-			CFG_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
-			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci1_hose,
 		     pci_hose_read_config_byte_via_dword,

board/Marvell/db64460/sdram_init.c

@@ -312,7 +312,7 @@ return 0;
 	} else
 		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
 
-#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
+#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
 
 	for (i = 0; i <= 127; i++) {
 		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
@@ -690,16 +690,16 @@ return 0;
 						if ((dimmInfo->
 						     minimumCycleTimeAtMaxCasLatancy_LoP
 						     <
-						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						    ||
 						    ((dimmInfo->
 						      minimumCycleTimeAtMaxCasLatancy_LoP
 						      ==
-						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						     && (dimmInfo->
 							 minimumCycleTimeAtMaxCasLatancy_RoP
 							 <
-							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
 						{
 							dimmInfo->
 								maxClSupported_DDR
@@ -714,16 +714,16 @@ return 0;
 						if ((dimmInfo->
 						     minimumCycleTimeAtMaxCasLatancy_LoP
 						     >
-						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						    ||
 						    ((dimmInfo->
 						      minimumCycleTimeAtMaxCasLatancy_LoP
 						      ==
-						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						     && (dimmInfo->
 							 minimumCycleTimeAtMaxCasLatancy_RoP
 							 >
-							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
 						{
 							printf ("*********************************************************\n");
 							printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
@@ -1289,37 +1289,37 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
 	case 0x0:
 	case 0x80:		/* refresh period is 15.625 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ)
+			(unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_HZ)
 					/ (float) 1000000.0);
 		break;
 	case 0x1:
 	case 0x81:		/* refresh period is 3.9 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x2:
 	case 0x82:		/* refresh period is 7.8 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x3:
 	case 0x83:		/* refresh period is 31.3 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x4:
 	case 0x84:		/* refresh period is 62.5 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x5:
 	case 0x85:		/* refresh period is 125 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 125 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	default:		/* refresh period undefined */
@@ -1816,7 +1816,7 @@ phys_size_t initdram (int board_type)
 
 	printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
 
-	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
 		/* skip over banks that are not populated */
 		if (!checkbank[bank_no])
 			continue;

board/Marvell/db64460/u-boot.lds

@@ -60,7 +60,7 @@ SECTIONS
 
 /* store the environment in a seperate sector in the boot flash */
 /*    . = env_offset; */
-/*    common/environment.o(.text) */
+/*    common/env_embedded.o(.text) */
 
     *(.text)
     *(.fixup)
@@ -131,6 +131,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/RPXClassic/RPXClassic.c

@@ -111,7 +111,7 @@ void board_get_enetaddr (uchar * enet)
 	char buff[256], *cp;
 
 	/* Initialize I2C					*/
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	/* Read 256 bytes in EEPROM				*/
 	i2c_read (0x54, 0, 1, (uchar *)buff, 128);
@@ -167,7 +167,7 @@ void rpxclassic_init (void)
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size10;
 
@@ -175,15 +175,15 @@ phys_size_t initdram (int board_type)
 			   sizeof (sdram_table) / sizeof (uint));
 
 	/* Refresh clock prescalar */
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	memctl->memc_mar = 0x00000000;
 
 	/* Map controller banks 1 to the SDRAM bank */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -200,7 +200,7 @@ phys_size_t initdram (int board_type)
 	 * try 10 column mode
 	 */
 
-	size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM,
+	size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
 						SDRAM_MAX_SIZE);
 
 	return (size10);
@@ -218,7 +218,7 @@ phys_size_t initdram (int board_type)
 
 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;

board/RPXClassic/eccx.c

@@ -299,7 +299,7 @@ void video_get_info_str (int line_number, char *info)
  */
 unsigned int board_video_init (void)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
     volatile memctl8xx_t *memctl = &immap->im_memctl;
 
     /* Program ECCX registers                                                */

board/RPXClassic/flash.c

@@ -33,7 +33,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -51,20 +51,20 @@ unsigned long flash_init (void)
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -313,7 +313,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	last  = start;
 	addr = (vu_long *)(info->start[l_sect]);
 	while ((addr[0] & 0x80808080) != 0x80808080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -436,7 +436,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}

board/RPXClassic/u-boot.lds

@@ -64,7 +64,7 @@ SECTIONS
 /* XXX ?
     . = env_offset;
 */
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)
@@ -135,6 +135,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/RPXClassic/u-boot.lds.debug

@@ -61,7 +61,7 @@ SECTIONS
     lib_generic/crc32.o		(.text)
 
     . = env_offset;
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)

board/RPXlite/RPXlite.c

@@ -104,7 +104,7 @@ int checkboard (void)
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size10;
 
@@ -112,15 +112,15 @@ phys_size_t initdram (int board_type)
 		   sizeof (sdram_table) / sizeof (uint));
 
 	/* Refresh clock prescalar */
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	memctl->memc_mar = 0x00000000;
 
 	/* Map controller banks 1 to the SDRAM bank */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -137,7 +137,7 @@ phys_size_t initdram (int board_type)
 	 * try 10 column mode
 	 */
 
-	size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM,
+	size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
 			    SDRAM_MAX_SIZE);
 
 	return (size10);
@@ -156,7 +156,7 @@ phys_size_t initdram (int board_type)
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;

board/RPXlite/flash.c

@@ -38,7 +38,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -52,13 +52,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info);
 
 unsigned long flash_init (void)
 {
-/*	volatile immap_t     *immap  = (immap_t *)CFG_IMMR; */
+/*	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR; */
 /*	volatile memctl8xx_t *memctl = &immap->im_memctl; */
 	unsigned long size_b0 ;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -73,19 +73,19 @@ unsigned long flash_init (void)
 */
 	/* Remap FLASH according to real size */
 /*%%%
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 %%%*/
 	/* Re-do sizing to get full correct info */
 
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -390,7 +390,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	last  = start;
 	addr = (vu_long *)(info->start[l_sect]);
 	while ((addr[0] & 0x80808080) != 0x80808080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -513,7 +513,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}

board/RPXlite/u-boot.lds

@@ -64,7 +64,7 @@ SECTIONS
 /* XXX ?
     . = env_offset;
 */
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)
@@ -135,6 +135,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/RPXlite/u-boot.lds.debug

@@ -61,7 +61,7 @@ SECTIONS
     lib_generic/crc32.o		(.text)
 
     . = env_offset;
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)

board/RPXlite_dw/README

@@ -21,7 +21,7 @@ make distclean
 make RPXlite_DW_64_config
 make all
 
-2. CFG_ENV_IS_IN_FLASH/CFG_ENV_IS_IN_NVRAM
+2. CONFIG_ENV_IS_IN_FLASH/CONFIG_ENV_IS_IN_NVRAM
 
 The default environment parameter is stored in FLASH because it is a common choice for
 environment parameter.So I make NVRAM as backup parameter storeage.The reason why I

board/RPXlite_dw/RPXlite_dw.c

@@ -106,22 +106,22 @@ int checkboard (void)
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size9;
 
 	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 
 	/* Refresh clock prescalar */
-	memctl->memc_mptpr = CFG_MPTPR ;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR ;
 
 	memctl->memc_mar  = 0x00000088;
 
 	/* Map controller banks 1 to the SDRAM bank */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
 	/*Disable Periodic timer A. */
 
 	udelay(200);
@@ -142,13 +142,13 @@ phys_size_t initdram (int board_type)
 	  * try 9 column mode
 	  */
 
-	size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
 
 	/*
 	 * Final mapping:
 	 */
 
-	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 
 	udelay (1000);
 
@@ -171,7 +171,7 @@ void rpxlite_init (void)
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;

board/RPXlite_dw/flash.c

@@ -49,7 +49,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions   vu_long : volatile unsigned long IN include/common.h
@@ -64,22 +64,22 @@ unsigned long flash_init (void)
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* If Monitor is in the cope of FLASH,then
 	 * protect this area by default in case for
 	 * other occupation. [SAM] */
 
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
 		      &flash_info[0]);
 #endif
 	flash_info[0].size = size_b0;
@@ -360,7 +360,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	last  = start;
 	addr = (vu_long *)(info->start[l_sect]);
 	while ((addr[0] & 0x80808080) != 0x80808080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -482,7 +482,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}

board/RPXlite_dw/u-boot.lds

@@ -64,7 +64,7 @@ SECTIONS
 /* XXX ?
     . = env_offset;
 */
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)
@@ -135,6 +135,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/RPXlite_dw/u-boot.lds.debug

@@ -61,7 +61,7 @@ SECTIONS
     lib_generic/crc32.o		(.text)
 
     . = env_offset;
-    common/environment.o(.text)
+    common/env_embedded.o(.text)
 
     *(.text)
     *(.fixup)

board/RRvision/RRvision.c

@@ -112,7 +112,7 @@ int checkboard (void)
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long reg;
 	long int size8, size9;
@@ -126,17 +126,17 @@ phys_size_t initdram (int board_type)
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
 	memctl->memc_mar = 0x00000088;
 
 	/*
 	 * Map controller bank 1 the SDRAM bank 2 at physical address 0.
 	 */
-	memctl->memc_or1 = CFG_OR2_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR2_PRELIM;
-	memctl->memc_br1 = CFG_BR2_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR2_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -156,7 +156,7 @@ phys_size_t initdram (int board_type)
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL,
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
 			   SDRAM_BASE2_PRELIM,
 			   SDRAM_MAX_SIZE);
 
@@ -165,7 +165,7 @@ phys_size_t initdram (int board_type)
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
 			   SDRAM_BASE2_PRELIM,
 			   SDRAM_MAX_SIZE);
 
@@ -174,7 +174,7 @@ phys_size_t initdram (int board_type)
 /*		debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
 	} else {			/* back to 8 columns            */
 		size = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 /*		debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
 	}
@@ -187,15 +187,15 @@ phys_size_t initdram (int board_type)
 	 */
 	if (size < 0x02000000) {
 		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 		udelay (1000);
 	}
 
 	/*
 	 * Final mapping
 	 */
-	memctl->memc_or1 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_or1 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 	/*
 	 * No bank 1
@@ -206,7 +206,7 @@ phys_size_t initdram (int board_type)
 
 	/* adjust refresh rate depending on SDRAM type, one bank */
 	reg = memctl->memc_mptpr;
-	reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
+	reg >>= 1;			/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 	memctl->memc_mptpr = reg;
 
 	udelay (10000);
@@ -227,7 +227,7 @@ phys_size_t initdram (int board_type)
 static long int dram_size (long int mamr_value, long int *base,
 						   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;

board/RRvision/flash.c

@@ -26,11 +26,11 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-#ifndef	CFG_ENV_ADDR
+#ifndef	CONFIG_ENV_ADDR
-#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 #endif
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -43,13 +43,13 @@ static int write_word (flash_info_t *info, ulong dest, ulong data);
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -63,25 +63,25 @@ unsigned long flash_init (void)
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & OR_AM_MSK);
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & OR_AM_MSK);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
 	/* Re-do sizing to get full correct info */
-	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
-#ifdef	CFG_ENV_IS_IN_FLASH
+#ifdef	CONFIG_ENV_IS_IN_FLASH
 	/* ENV protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_ENV_ADDR,
+		      CONFIG_ENV_ADDR,
-		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
 		      &flash_info[0]);
 #endif
 
@@ -388,7 +388,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	last  = start;
 	addr = (vu_long*)(info->start[l_sect]);
 	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			puts ("Timeout\n");
 			return 1;
 		}
@@ -511,7 +511,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}

board/RRvision/u-boot.lds

@@ -66,7 +66,7 @@ SECTIONS
     lib_ppc/time.o		(.text)
 
     . = env_offset;
-    common/environment.o	(.ppcenv)
+    common/env_embedded.o	(.ppcenv)
 
     *(.text)
     *(.fixup)
@@ -137,6 +137,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/a3000/a3000.c

@@ -27,6 +27,7 @@
 #include <common.h>
 #include <mpc824x.h>
 #include <pci.h>
+#include <netdev.h>
 
 int checkboard (void)
 {
@@ -45,7 +46,7 @@ phys_size_t initdram (int board_type)
 	long mear1;
 	long emear1;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 
 	new_bank0_end = size - 1;
 	mear1 = mpc824x_mpc107_getreg(MEAR1);
@@ -109,3 +110,8 @@ void pci_init_board(void)
 {
 	pci_mpc824x_init(&hose);
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/a3000/flash.c

@@ -25,15 +25,15 @@
 #include <common.h>
 #include <mpc824x.h>
 
-#if defined(CFG_ENV_IS_IN_FLASH)
+#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef  CFG_ENV_ADDR
+# ifndef  CONFIG_ENV_ADDR
-#  define CFG_ENV_ADDR  (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR  (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
-# ifndef  CFG_ENV_SIZE
+# ifndef  CONFIG_ENV_SIZE
-#  define CFG_ENV_SIZE  CFG_ENV_SECT_SIZE
+#  define CONFIG_ENV_SIZE  CONFIG_ENV_SECT_SIZE
 # endif
-# ifndef  CFG_ENV_SECT_SIZE
+# ifndef  CONFIG_ENV_SECT_SIZE
-#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
 # endif
 #endif
 
@@ -48,7 +48,7 @@
 #endif
 /*---------------------------------------------------------------------*/
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -65,13 +65,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info);
 
 unsigned long flash_init (void)
 {
-	unsigned long flash_banks[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS;
+	unsigned long flash_banks[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_BANKS;
-	unsigned long size, size_b[CFG_MAX_FLASH_BANKS];
+	unsigned long size, size_b[CONFIG_SYS_MAX_FLASH_BANKS];
 
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
 	{
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 
@@ -99,27 +99,27 @@ unsigned long flash_init (void)
 	}
 
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, CFG_MONITOR_LEN);
+	DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN);
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
 		      &flash_info[0]);
 #endif
 
-#ifdef	CFG_ENV_IS_IN_FLASH
+#ifdef	CONFIG_ENV_IS_IN_FLASH
 	/* ENV protection ON by default */
-	DEBUGF("protect environtment %x @ %x\n", CFG_ENV_ADDR, CFG_ENV_SECT_SIZE);
+	DEBUGF("protect environtment %x @ %x\n", CONFIG_ENV_ADDR, CONFIG_ENV_SECT_SIZE);
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_ENV_ADDR,
+		      CONFIG_ENV_ADDR,
-		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
 		      &flash_info[0]);
 #endif
 
 	size = 0;
 	DEBUGF("## Final Flash bank sizes: ");
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
 	{
 		DEBUGF("%08lx ", size_b[i]);
 		size += size_b[i];
@@ -285,10 +285,10 @@ static ulong flash_get_size (vu_char *addr, flash_info_t *info)
 
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = BS(0xFF);		/* restore read mode */
@@ -356,7 +356,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 			udelay (1000);
 
 			while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = BS(0xB0); /* suspend erase	  */
 					*addr = BS(0xFF); /* reset to read mode */
@@ -439,7 +439,7 @@ static int write_data (flash_info_t *info, uchar *dest, uchar data)
 	start = get_timer (0);
 
 	while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = BS(0xFF);	/* restore read mode */
 			return 1;
 		}

board/actux1/actux1.c

@@ -49,16 +49,16 @@ int board_init (void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
 
 	/* Setup GPIO's for PCI INTA */
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI1_INTA);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI1_INTA);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA);
 
 	/* Setup GPIO's for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
 	*IXP425_GPIO_GPCLKR = 0x011001FF;
 
 	/* CS5: Debug port */
@@ -69,7 +69,7 @@ int board_init (void)
 	*IXP425_EXP_CS7 = 0x80900003;
 
 	udelay (533);
-	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
 
 	ACTUX1_LED1 (2);
 	ACTUX1_LED2 (2);

board/actux1/actux1_hw.h

@@ -42,16 +42,16 @@
 #define ACTUX1_BOARDREL	(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
 
 /* GPIO settings */
-#define CFG_GPIO_PCI1_INTA		2
+#define CONFIG_SYS_GPIO_PCI1_INTA		2
-#define CFG_GPIO_PCI2_INTA		3
+#define CONFIG_SYS_GPIO_PCI2_INTA		3
-#define CFG_GPIO_I2C_SDA		4
+#define CONFIG_SYS_GPIO_I2C_SDA		4
-#define CFG_GPIO_I2C_SCL		5
+#define CONFIG_SYS_GPIO_I2C_SCL		5
-#define CFG_GPIO_DBGJUMPER		9
+#define CONFIG_SYS_GPIO_DBGJUMPER		9
-#define CFG_GPIO_BUTTON1		10
+#define CONFIG_SYS_GPIO_BUTTON1		10
-#define CFG_GPIO_DBGSENSE		11
+#define CONFIG_SYS_GPIO_DBGSENSE		11
-#define CFG_GPIO_DTR			12
+#define CONFIG_SYS_GPIO_DTR			12
-#define CFG_GPIO_IORST			13	/* Out */
+#define CONFIG_SYS_GPIO_IORST			13	/* Out */
-#define CFG_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
-#define CFG_GPIO_EXTBUS_CLK		15	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
 
 #endif

board/actux1/u-boot.lds

@@ -37,7 +37,7 @@ SECTIONS
 		common/dlmalloc.o(.text)
 		cpu/ixp/cpu.o(.text)
 		. = env_offset;
-		common/environment.o(.ppcenv)
+		common/env_embedded.o(.ppcenv)
 		* (.text)
 	}
 
@@ -64,6 +64,7 @@ SECTIONS
 	__bss_start =.;
 	.bss (NOLOAD): {
 		*(.bss)
+		. = ALIGN(4);
 	}
 	_end =.;
 }

board/actux2/actux2.c

@@ -50,24 +50,24 @@ int board_init (void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_ETHRST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_DSR);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_DCD);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_SET (CFG_GPIO_DCD);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
 
 	/* Setup GPIO's for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_DBGINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_ETHINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
 
 	/* Setup GPIO's for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
 	*IXP425_GPIO_GPCLKR = 0x011001FF;
 
 	/* CS1: IPAC-X */
@@ -80,8 +80,8 @@ int board_init (void)
 	*IXP425_EXP_CS7 = 0x80900003;
 
 	udelay (533);
-	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_SET (CFG_GPIO_ETHRST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
 
 	ACTUX2_LED1 (1);
 	ACTUX2_LED2 (0);

board/actux2/actux2_hw.h

@@ -39,21 +39,21 @@
 /*
  * GPIO settings
  */
-#define CFG_GPIO_DBGINT			0
+#define CONFIG_SYS_GPIO_DBGINT			0
-#define CFG_GPIO_ETHINT			1
+#define CONFIG_SYS_GPIO_ETHINT			1
-#define CFG_GPIO_ETHRST			2	/* Out */
+#define CONFIG_SYS_GPIO_ETHRST			2	/* Out */
-#define CFG_GPIO_LED5_GN		3	/* Out */
+#define CONFIG_SYS_GPIO_LED5_GN		3	/* Out */
-#define CFG_GPIO_UNUSED4		4
+#define CONFIG_SYS_GPIO_UNUSED4		4
-#define CFG_GPIO_UNUSED5		5
+#define CONFIG_SYS_GPIO_UNUSED5		5
-#define CFG_GPIO_DSR			6	/* Out */
+#define CONFIG_SYS_GPIO_DSR			6	/* Out */
-#define CFG_GPIO_DCD			7	/* Out */
+#define CONFIG_SYS_GPIO_DCD			7	/* Out */
-#define CFG_GPIO_IPAC_INT		8
+#define CONFIG_SYS_GPIO_IPAC_INT		8
-#define CFG_GPIO_DBGJUMPER		9
+#define CONFIG_SYS_GPIO_DBGJUMPER		9
-#define CFG_GPIO_BUTTON1		10
+#define CONFIG_SYS_GPIO_BUTTON1		10
-#define CFG_GPIO_DBGSENSE		11
+#define CONFIG_SYS_GPIO_DBGSENSE		11
-#define CFG_GPIO_DTR			12
+#define CONFIG_SYS_GPIO_DTR			12
-#define CFG_GPIO_IORST			13	/* Out */
+#define CONFIG_SYS_GPIO_IORST			13	/* Out */
-#define CFG_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
-#define CFG_GPIO_EXTBUS_CLK		15	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
 
 #endif

board/actux2/u-boot.lds

@@ -38,7 +38,7 @@ SECTIONS
 		cpu/ixp/cpu.o(.text)
 
 		. = env_offset;
-		common/environment.o (.ppcenv)
+		common/env_embedded.o (.ppcenv)
 
 		* (.text)
 	}
@@ -69,6 +69,7 @@ SECTIONS
 	__bss_start =.;
 	.bss (NOLOAD): {
 		*(.bss)
+		. = ALIGN(4);
 	}
 	_end =.;
 }

board/actux3/actux3.c

@@ -50,35 +50,35 @@ int board_init (void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_ETHRST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_DSR);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_DCD);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_LED5_GN);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED5_GN);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_LED6_RT);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_RT);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_LED6_GN);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_GN);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_SET (CFG_GPIO_DCD);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_LED5_GN);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED5_GN);
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_RT);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_RT);
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_GN);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_GN);
 
 	/*
 	 * Setup GPIO's for Interrupt inputs
 	 */
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_DBGINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_ETHINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
 
 	/*
 	 * Setup GPIO's for 33MHz clock output
 	 */
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
 	*IXP425_GPIO_GPCLKR = 0x011001FF;
 
 	/* CS1: IPAC-X */
@@ -91,8 +91,8 @@ int board_init (void)
 	*IXP425_EXP_CS7 = 0x80900003;
 
 	udelay (533);
-	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_SET (CFG_GPIO_ETHRST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
 
 	ACTUX3_LED1_RT (1);
 	ACTUX3_LED1_GN (0);

board/actux3/actux3_hw.h

@@ -41,20 +41,20 @@
 #define ACTUX3_OPTION		(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
 
 /* GPIO settings */
-#define CFG_GPIO_DBGINT			0
+#define CONFIG_SYS_GPIO_DBGINT			0
-#define CFG_GPIO_ETHINT			1
+#define CONFIG_SYS_GPIO_ETHINT			1
-#define CFG_GPIO_ETHRST			2	/* Out */
+#define CONFIG_SYS_GPIO_ETHRST			2	/* Out */
-#define CFG_GPIO_LED5_GN		3	/* Out */
+#define CONFIG_SYS_GPIO_LED5_GN		3	/* Out */
-#define CFG_GPIO_LED6_RT		4	/* Out */
+#define CONFIG_SYS_GPIO_LED6_RT		4	/* Out */
-#define CFG_GPIO_LED6_GN		5	/* Out */
+#define CONFIG_SYS_GPIO_LED6_GN		5	/* Out */
-#define CFG_GPIO_DSR			6	/* Out */
+#define CONFIG_SYS_GPIO_DSR			6	/* Out */
-#define CFG_GPIO_DCD			7	/* Out */
+#define CONFIG_SYS_GPIO_DCD			7	/* Out */
-#define CFG_GPIO_DBGJUMPER		9
+#define CONFIG_SYS_GPIO_DBGJUMPER		9
-#define CFG_GPIO_BUTTON1		10
+#define CONFIG_SYS_GPIO_BUTTON1		10
-#define CFG_GPIO_DBGSENSE		11
+#define CONFIG_SYS_GPIO_DBGSENSE		11
-#define CFG_GPIO_DTR			12
+#define CONFIG_SYS_GPIO_DTR			12
-#define CFG_GPIO_IORST			13	/* Out */
+#define CONFIG_SYS_GPIO_IORST			13	/* Out */
-#define CFG_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
-#define CFG_GPIO_EXTBUS_CLK		15	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
 
 #endif

board/actux3/u-boot.lds

@@ -38,7 +38,7 @@ SECTIONS
 		cpu/ixp/cpu.o (.text)
 
 		. = env_offset;
-		common/environment.o (.ppcenv)
+		common/env_embedded.o (.ppcenv)
 
 		* (.text)
 	}
@@ -69,6 +69,7 @@ SECTIONS
 	__bss_start =.;
 	.bss (NOLOAD): {
 		*(.bss)
+		. = ALIGN(4);
 	}
 	_end =.;
 }

board/actux4/actux4.c

@@ -49,53 +49,53 @@ int board_init (void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_nPWRON);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_nPWRON);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_nPWRON);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_nPWRON);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
 
 	/* led not populated on board*/
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_LED3);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED3);
-	GPIO_OUTPUT_SET (CFG_GPIO_LED3);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED3);
 
 	/* middle LED */
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_LED2);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED2);
-	GPIO_OUTPUT_SET (CFG_GPIO_LED2);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED2);
 
 	/* right LED */
 	/* weak pulldown = LED weak on */
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_LED1);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_LED1);
-	GPIO_OUTPUT_SET (CFG_GPIO_LED1);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED1);
 
 	/* Setup GPIO's for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTA);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTA);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTB);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTB);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTC);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTC);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_RTCINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_RTCINT);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI_INTA);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTA);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI_INTB);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTB);
 
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTA);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTA);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTB);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTB);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTC);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTC);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_RTCINT);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_RTCINT);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI_INTA);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTA);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI_INTB);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTB);
 
 	/* Setup GPIO's for 33MHz clock output */
 	*IXP425_GPIO_GPCLKR = 0x011001FF;
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
 
 	*IXP425_EXP_CS1 = 0xbd113c42;
 
 	udelay (10000);
-	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
 	udelay (10000);
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
 	udelay (10000);
-	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
 
 	return 0;
 }

board/actux4/actux4_hw.h

@@ -29,21 +29,21 @@
 /*
  * GPIO settings
  */
-#define CFG_GPIO_USBINTA		0
+#define CONFIG_SYS_GPIO_USBINTA		0
-#define CFG_GPIO_USBINTB		1
+#define CONFIG_SYS_GPIO_USBINTB		1
-#define CFG_GPIO_USBINTC		2
+#define CONFIG_SYS_GPIO_USBINTC		2
-#define CFG_GPIO_nPWRON			3	/* Out */
+#define CONFIG_SYS_GPIO_nPWRON			3	/* Out */
-#define CFG_GPIO_I2C_SCL		4
+#define CONFIG_SYS_GPIO_I2C_SCL		4
-#define CFG_GPIO_I2C_SDA		5
+#define CONFIG_SYS_GPIO_I2C_SDA		5
-#define CFG_GPIO_PCI_INTB		6
+#define CONFIG_SYS_GPIO_PCI_INTB		6
-#define CFG_GPIO_BUTTON1		7
+#define CONFIG_SYS_GPIO_BUTTON1		7
-#define CFG_GPIO_LED1			8	/* Out */
+#define CONFIG_SYS_GPIO_LED1			8	/* Out */
-#define CFG_GPIO_RTCINT			9
+#define CONFIG_SYS_GPIO_RTCINT			9
-#define CFG_GPIO_LED2			10	/* Out */
+#define CONFIG_SYS_GPIO_LED2			10	/* Out */
-#define CFG_GPIO_PCI_INTA		11
+#define CONFIG_SYS_GPIO_PCI_INTA		11
-#define CFG_GPIO_IORST			12	/* Out */
+#define CONFIG_SYS_GPIO_IORST			12	/* Out */
-#define CFG_GPIO_LED3			13	/* Out */
+#define CONFIG_SYS_GPIO_LED3			13	/* Out */
-#define CFG_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
-#define CFG_GPIO_EXTBUS_CLK		15	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
 
 #endif

board/actux4/u-boot.lds

@@ -60,6 +60,7 @@ SECTIONS
 	__bss_start =.;
 	.bss (NOLOAD): {
 		*(.bss)
+		. = ALIGN(4);
 	}
 	_end =.;
 }

board/adder/adder.c

@@ -68,7 +68,7 @@ static uint sdram_table[] = {
 phys_size_t initdram (int board_type)
 {
 	long int msize;
-	volatile immap_t     *immap  = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
@@ -76,7 +76,7 @@ phys_size_t initdram (int board_type)
 	/* Configure SDRAM refresh */
 	memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
 
-	memctl->memc_mamr = (94 << 24) | CFG_MAMR; /* No refresh */
+	memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */
 	udelay(200);
 
 	/* Run precharge from location 0x15 */
@@ -94,10 +94,10 @@ phys_size_t initdram (int board_type)
 	udelay(200);
 
 	memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
-	memctl->memc_or1   = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
+	memctl->memc_or1   = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
-	memctl->memc_br1   =  CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
+	memctl->memc_br1   =  CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
 
-	msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
+	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
 	memctl->memc_or1  |= ~(msize - 1);
 
 	return msize;

board/adder/u-boot.lds

@@ -118,6 +118,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/ads5121/ads5121.c

@@ -53,16 +53,16 @@ long int fixed_sdram(void);
 
 int board_early_init_f (void)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 lpcaw;
 
 	/*
 	 * Initialize Local Window for the CPLD registers access (CS2 selects
 	 * the CPLD chip)
 	 */
-	im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
+	im->sysconf.lpcs2aw = CSAW_START(CONFIG_SYS_CPLD_BASE) |
-			      CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
+			      CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE);
-	im->lpc.cs_cfg[2] = CFG_CS2_CFG;
+	im->lpc.cs_cfg[2] = CONFIG_SYS_CS2_CFG;
 
 	/*
 	 * According to MPC5121e RM, configuring local access windows should
@@ -80,21 +80,21 @@ int board_early_init_f (void)
 	 */
 
 #ifdef CONFIG_ADS5121_REV2
-	*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
+	*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
 #else
-	if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) {
+	if (*((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
-		*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
+		*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
 	} else {
 		/* running from Backup flash */
-		*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32;
+		*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0x32;
 	}
 #endif
 	/*
 	 * Configure Flash Speed
 	 */
-	*((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG;
+	*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS0_CONFIG)) = CONFIG_SYS_CS0_CFG;
 	if (SVR_MJREV (im->sysconf.spridr) >= 2) {
-		*((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CFG_CS_ALETIMING;
+		*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CONFIG_SYS_CS_ALETIMING;
 	}
 	/*
 	 * Enable clocks
@@ -120,8 +120,8 @@ phys_size_t initdram (int board_type)
  */
 long int fixed_sdram (void)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
 	u32 msize_log2 = __ilog2 (msize);
 	u32 i;
 
@@ -129,7 +129,7 @@ long int fixed_sdram (void)
 	im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR;
 
 	/* Initialize DDR Local Window */
-	im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
+	im->sysconf.ddrlaw.bar = CONFIG_SYS_DDR_BASE & 0xFFFFF000;
 	im->sysconf.ddrlaw.ar = msize_log2 - 1;
 
 	/*
@@ -141,68 +141,68 @@ long int fixed_sdram (void)
 	__asm__ __volatile__ ("isync");
 
 	/* Enable DDR */
-	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;
+	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN;
 
 	/* Initialize DDR Priority Manager */
-	im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
+	im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1;
-	im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
+	im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2;
-	im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
+	im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG;
-	im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
+	im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU;
-	im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
+	im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML;
-	im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
+	im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU;
-	im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
+	im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML;
-	im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
+	im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU;
-	im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
+	im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML;
-	im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
+	im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU;
-	im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
+	im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML;
-	im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
+	im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU;
-	im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
+	im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML;
-	im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
+	im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU;
-	im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
+	im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL;
-	im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
+	im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU;
-	im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
+	im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL;
-	im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
+	im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU;
-	im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
+	im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL;
-	im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
+	im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU;
-	im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
+	im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL;
-	im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
+	im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU;
-	im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
+	im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL;
 
 	/* Initialize MDDRC */
-	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
+	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG;
-	im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
+	im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
-	im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
+	im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1;
-	im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;
+	im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2;
 
 	/* Initialize DDR */
 	for (i = 0; i < 10; i++)
-		im->mddrc.ddr_command = CFG_MICRON_NOP;
+		im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
 
-	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-	im->mddrc.ddr_command = CFG_MICRON_RFSH;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-	im->mddrc.ddr_command = CFG_MICRON_RFSH;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-	im->mddrc.ddr_command = CFG_MICRON_EM2;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CFG_MICRON_EM2;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
-	im->mddrc.ddr_command = CFG_MICRON_EM3;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3;
-	im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL;
-	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
-	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CFG_MICRON_RFSH;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
-	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
-	im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT;
-	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
 
 	/* Start MDDRC */
-	im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
+	im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN;
-	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;
+	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN;
 
 	return msize;
 }
@@ -292,8 +292,8 @@ static  iopin_t ioregs_init[] = {
 
 int checkboard (void)
 {
-	ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
+	ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
-	uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
+	uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
 
 	printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
 		brd_rev, cpld_rev);

board/ads5121/ads5121_diu.c

@@ -43,7 +43,7 @@ static int xres, yres;
 
 void diu_set_pixel_clock(unsigned int pixclock)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile clk512x_t *clk = &immap->clk;
 	volatile unsigned int *clkdvdr = &clk->scfr[0];
 	unsigned long speed_ccb, temp, pixval;
@@ -100,7 +100,7 @@ int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
 }
 
 U_BOOT_CMD(
-	diufb, CFG_MAXARGS, 1, ads5121diu_init_show_bmp,
+	diufb, CONFIG_SYS_MAXARGS, 1, ads5121diu_init_show_bmp,
 	"diufb init | addr - Init or Display BMP file\n",
 	"init\n    - initialize DIU\n"
 	"addr\n    - display bmp at address 'addr'\n"

board/ads5121/pci.c

@@ -33,8 +33,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
 
 static struct pci_controller pci_hose;
 
@@ -46,7 +46,7 @@ static struct pci_controller pci_hose;
 void
 pci_init_board(void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile law512x_t *pci_law;
 	volatile pot512x_t *pci_pot;
 	volatile pcictrl512x_t *pci_ctrl;
@@ -87,10 +87,10 @@ pci_init_board(void)
 	/*
 	 * Configure PCI Local Access Windows
 	 */
-	pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
 
-	pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
 
 	/*
@@ -98,18 +98,18 @@ pci_init_board(void)
 	 */
 
 	/* PCI mem space - prefetch */
-	pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M;
 
 	/* PCI IO space */
-	pci_pot[1].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[1].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
 
 	/* PCI mmio - non-prefetch mem space */
-	pci_pot[2].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[2].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[2].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[2].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
 
 	/*
@@ -129,23 +129,23 @@ pci_init_board(void)
 
 	/* PCI memory prefetch space */
 	pci_set_region(hose->regions + 0,
-		       CFG_PCI_MEM_BASE,
+		       CONFIG_SYS_PCI_MEM_BASE,
-		       CFG_PCI_MEM_PHYS,
+		       CONFIG_SYS_PCI_MEM_PHYS,
-		       CFG_PCI_MEM_SIZE,
+		       CONFIG_SYS_PCI_MEM_SIZE,
 		       PCI_REGION_MEM|PCI_REGION_PREFETCH);
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + 1,
-		       CFG_PCI_MMIO_BASE,
+		       CONFIG_SYS_PCI_MMIO_BASE,
-		       CFG_PCI_MMIO_PHYS,
+		       CONFIG_SYS_PCI_MMIO_PHYS,
-		       CFG_PCI_MMIO_SIZE,
+		       CONFIG_SYS_PCI_MMIO_SIZE,
 		       PCI_REGION_MEM);
 
 	/* PCI IO space */
 	pci_set_region(hose->regions + 2,
-		       CFG_PCI_IO_BASE,
+		       CONFIG_SYS_PCI_IO_BASE,
-		       CFG_PCI_IO_PHYS,
+		       CONFIG_SYS_PCI_IO_PHYS,
-		       CFG_PCI_IO_SIZE,
+		       CONFIG_SYS_PCI_IO_SIZE,
 		       PCI_REGION_IO);
 
 	/* System memory space */
@@ -158,8 +158,8 @@ pci_init_board(void)
 	hose->region_count = 4;
 
 	pci_setup_indirect(hose,
-			   (CFG_IMMR + 0x8300),
+			   (CONFIG_SYS_IMMR + 0x8300),
-			   (CFG_IMMR + 0x8304));
+			   (CONFIG_SYS_IMMR + 0x8304));
 
 	pci_register_hose(hose);
 

board/ads5121/u-boot.lds

@@ -115,6 +115,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
   _end = . ;
   PROVIDE (end = .);

board/afeb9260/Makefile

@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= afeb9260.o
+COBJS-y	+= partition.o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/afeb9260/afeb9260.c

@@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <netdev.h>
+#include <net.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void afeb9260_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+	at91_set_A_periph(AT91_PIN_PB4, 1);		/* TXD0 */
+	at91_set_A_periph(AT91_PIN_PB5, 0);		/* RXD0 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
+#endif
+
+#ifdef CONFIG_USART1
+	at91_set_A_periph(AT91_PIN_PB6, 1);		/* TXD1 */
+	at91_set_A_periph(AT91_PIN_PB7, 0);		/* RXD1 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
+#endif
+
+#ifdef CONFIG_USART2
+	at91_set_A_periph(AT91_PIN_PB8, 1);		/* TXD2 */
+	at91_set_A_periph(AT91_PIN_PB9, 0);		/* RXD2 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
+#endif
+
+#ifdef CONFIG_USART3	/* DBGU */
+	at91_set_A_periph(AT91_PIN_PB14, 0);		/* DRXD */
+	at91_set_A_periph(AT91_PIN_PB15, 1);		/* DTXD */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+#endif
+}
+
+static void afeb9260_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+		       AT91_SMC_DBW_8 |
+		       AT91_SMC_TDF_(2));
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(AT91_PIN_PC13, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(AT91_PIN_PC14, 1);
+}
+
+static void afeb9260_spi_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PA3, 0);	/* SPI0_NPCS0 */
+	at91_set_B_periph(AT91_PIN_PC11, 0);	/* SPI0_NPCS1 */
+
+	at91_set_A_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
+	at91_set_A_periph(AT91_PIN_PA1, 0);	/* SPI0_MOSI */
+	at91_set_A_periph(AT91_PIN_PA2, 0);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
+}
+
+#ifdef CONFIG_MACB
+static void afeb9260_macb_hw_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA17) => PHY normal mode (not Test mode)
+	 *	ERX0 (PA14) => PHY ADDR0
+	 *	ERX1 (PA15) => PHY ADDR1
+	 *	ERX2 (PA25) => PHY ADDR2
+	 *	ERX3 (PA26) => PHY ADDR3
+	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+	/* Need to reset PHY -> 500ms reset */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     AT91_RSTC_ERSTL | (0x0D << 8) |
+				     AT91_RSTC_URSTEN);
+
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+	/* Wait for end hardware reset */
+	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+
+	/* Restore NRST value */
+	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+				     AT91_RSTC_ERSTL | (0x0 << 8) |
+				     AT91_RSTC_URSTEN);
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA17) |
+	       pin_to_mask(AT91_PIN_PA25) |
+	       pin_to_mask(AT91_PIN_PA26) |
+	       pin_to_mask(AT91_PIN_PA28),
+	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+	at91_set_A_periph(AT91_PIN_PA19, 0);	/* ETXCK_EREFCK */
+	at91_set_A_periph(AT91_PIN_PA17, 0);	/* ERXDV */
+	at91_set_A_periph(AT91_PIN_PA14, 0);	/* ERX0 */
+	at91_set_A_periph(AT91_PIN_PA15, 0);	/* ERX1 */
+	at91_set_A_periph(AT91_PIN_PA18, 0);	/* ERXER */
+	at91_set_A_periph(AT91_PIN_PA16, 0);	/* ETXEN */
+	at91_set_A_periph(AT91_PIN_PA12, 0);	/* ETX0 */
+	at91_set_A_periph(AT91_PIN_PA13, 0);	/* ETX1 */
+	at91_set_A_periph(AT91_PIN_PA21, 0);	/* EMDIO */
+	at91_set_A_periph(AT91_PIN_PA20, 0);	/* EMDC */
+
+#ifndef CONFIG_RMII
+	at91_set_B_periph(AT91_PIN_PA28, 0);	/* ECRS */
+	at91_set_B_periph(AT91_PIN_PA29, 0);	/* ECOL */
+	at91_set_B_periph(AT91_PIN_PA25, 0);	/* ERX2 */
+	at91_set_B_periph(AT91_PIN_PA26, 0);	/* ERX3 */
+	at91_set_B_periph(AT91_PIN_PA27, 0);	/* ERXCK */
+	at91_set_B_periph(AT91_PIN_PA10, 0);	/* ETX2 */
+	at91_set_B_periph(AT91_PIN_PA11, 0);	/* ETX3 */
+	at91_set_B_periph(AT91_PIN_PA22, 0);	/* ETXER */
+#endif
+
+}
+#endif
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* arch number of AT91SAM9260EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AFEB9260;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	afeb9260_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	afeb9260_nand_hw_init();
+#endif
+	afeb9260_spi_hw_init();
+#ifdef CONFIG_MACB
+	afeb9260_macb_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}

board/afeb9260/config.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0x21f00000

board/afeb9260/nand.c

@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
+
+#include <nand.h>
+
+/*
+ *	hardware specific access to control-lines
+ */
+#define	MASK_ALE	(1 << 21)	/* our ALE is AD21 */
+#define	MASK_CLE	(1 << 22)	/* our CLE is AD22 */
+
+static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd,
+					 int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+		IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= MASK_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= MASK_ALE;
+
+		at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
+		this->IO_ADDR_W = (void *) IO_ADDR_W;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
+{
+	return at91_get_gpio_value(AT91_PIN_PC13);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->ecc.mode = NAND_ECC_SOFT;
+#ifdef CONFIG_SYS_NAND_DBW_16
+	nand->options = NAND_BUSWIDTH_16;
+#endif
+	nand->cmd_ctrl = at91sam9260ek_nand_hwcontrol;
+	nand->dev_ready = at91sam9260ek_nand_ready;
+	nand->chip_delay = 20;
+
+	return 0;
+}

board/afeb9260/partition.c

@@ -0,0 +1,36 @@
+/*
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_CLEAR, 0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"},
+};

board/alaska/alaska.c

@@ -32,48 +32,48 @@ void setupBat (ulong size)
 	int blocksize = 0;
 
 	/* Flash 0 */
-#if defined (CFG_AMD_BOOT)
+#if defined (CONFIG_SYS_AMD_BOOT)
-	batu = CFG_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+	batu = CONFIG_SYS_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
 #else
-	batu = CFG_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
+	batu = CONFIG_SYS_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
 #endif
-	batl = CFG_FLASH0_BASE | 0x22;
+	batl = CONFIG_SYS_FLASH0_BASE | 0x22;
 	write_bat (IBAT0, batu, batl);
 	write_bat (DBAT0, batu, batl);
 
 	/* Flash 1 */
-#if defined (CFG_AMD_BOOT)
+#if defined (CONFIG_SYS_AMD_BOOT)
-	batu = CFG_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
+	batu = CONFIG_SYS_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
 #else
-	batu = CFG_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+	batu = CONFIG_SYS_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
 #endif
-	batl = CFG_FLASH1_BASE | 0x22;
+	batl = CONFIG_SYS_FLASH1_BASE | 0x22;
 	write_bat (IBAT1, batu, batl);
 	write_bat (DBAT1, batu, batl);
 
 	/* CPLD */
-	batu = CFG_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+	batu = CONFIG_SYS_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
-	batl = CFG_CPLD_BASE | 0x22;
+	batl = CONFIG_SYS_CPLD_BASE | 0x22;
 	write_bat (IBAT2, 0, 0);
 	write_bat (DBAT2, batu, batl);
 
 	/* FPGA */
-	batu = CFG_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+	batu = CONFIG_SYS_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
-	batl = CFG_FPGA_BASE | 0x22;
+	batl = CONFIG_SYS_FPGA_BASE | 0x22;
 	write_bat (IBAT3, 0, 0);
 	write_bat (DBAT3, batu, batl);
 
 	/* MBAR - Data only */
-	batu = CFG_MBAR | BPP_RW | BPP_RX;
+	batu = CONFIG_SYS_MBAR | BPP_RW | BPP_RX;
-	batl = CFG_MBAR | 0x22;
+	batl = CONFIG_SYS_MBAR | 0x22;
 	mtspr (IBAT4L, 0);
 	mtspr (IBAT4U, 0);
 	mtspr (DBAT4L, batl);
 	mtspr (DBAT4U, batu);
 
 	/* MBAR - SRAM */
-	batu = CFG_SRAM_BASE | BPP_RW | BPP_RX;
+	batu = CONFIG_SYS_SRAM_BASE | BPP_RW | BPP_RX;
-	batl = CFG_SRAM_BASE | 0x42;
+	batl = CONFIG_SYS_SRAM_BASE | 0x42;
 	mtspr (IBAT5L, batl);
 	mtspr (IBAT5U, batu);
 	mtspr (DBAT5L, batl);
@@ -93,8 +93,8 @@ void setupBat (ulong size)
 		blocksize = BL_256M << 2;
 
 	/* Memory */
-	batu = CFG_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
+	batu = CONFIG_SYS_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
-	batl = CFG_SDRAM_BASE | 0x42;
+	batl = CONFIG_SYS_SDRAM_BASE | 0x42;
 	mtspr (IBAT6L, batl);
 	mtspr (IBAT6U, batu);
 	mtspr (DBAT6L, batl);
@@ -120,9 +120,9 @@ void setupBat (ulong size)
 		else if (size <= 0x10000000)	/* 256MB */
 			blocksize = BL_256M << 2;
 
-		batu = (CFG_SDRAM_BASE +
+		batu = (CONFIG_SYS_SDRAM_BASE +
 			0x10000000) | blocksize | BPP_RW | BPP_RX;
-		batl = (CFG_SDRAM_BASE + 0x10000000) | 0x42;
+		batl = (CONFIG_SYS_SDRAM_BASE + 0x10000000) | 0x42;
 	}
 
 	mtspr (IBAT7L, batl);