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White space cleanup.

Browse source 
Some 80-column cleanups.
Convert printf() to puts() where possible.
Use #include "spd_sdram.h" as needed.
Enhanced reset command usage message a bit.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
This commit is contained in:
Jon Loeliger 2006-05-31 12:44:44 -05:00
parent 3d5c5be547
commit cb5965fb95
2 changed files with 127 additions and 121 deletions
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221
board/mpc8641hpcn/mpc8641hpcn.c
View file

@ -38,12 +38,13 @@ extern void ft_cpu_setup(void *blob, bd_t *bd);
#include "pixis.h" #include "pixis.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size); extern void ddr_enable_ecc(unsigned int dram_size);
#endif #endif
extern long int spd_sdram(void); #if defined(CONFIG_SPD_EEPROM)
#include "spd_sdram.h"
#endif
void sdram_init(void); void sdram_init(void);
long int fixed_sdram(void); long int fixed_sdram(void);
@ -51,7 +52,7 @@ long int fixed_sdram(void);
int board_early_init_f (void) int board_early_init_f (void)
{ {
return 0; return 0;
} }
int checkboard (void) int checkboard (void)
@ -60,34 +61,32 @@ int checkboard (void)
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur; volatile ccsr_gur_t *gur = &immap->im_gur;
volatile ccsr_pex_t *pex1 = &immap->im_pex1; volatile ccsr_pex_t *pex1 = &immap->im_pex1;
uint devdisr = gur->devdisr; uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
if ((io_sel == 2 || io_sel == 3 || io_sel == 5
if ((io_sel==2 || io_sel==3 || io_sel==5 \ || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
|| io_sel==6 || io_sel==7 || io_sel==0xF) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
debug ("PCI-EXPRESS 1: %s \n", debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
pex1_agent ? "Agent" : "Host"); if (pex1->pme_msg_det) {
debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); pex1->pme_msg_det = 0xffffffff;
if (pex1->pme_msg_det) { debug(" with errors. Clearing. Now 0x%08x",
pex1->pme_msg_det = 0xffffffff; pex1->pme_msg_det);
debug (" with errors. Clearing. Now 0x%08x", }
pex1->pme_msg_det); debug ("\n");
} } else {
debug ("\n"); puts("PCI-EXPRESS 1: Disabled\n");
} else { }
printf ("PCI-EXPRESS 1: Disabled\n");
}
#else #else
printf("PCI-EXPRESS1: Disabled\n"); puts("PCI-EXPRESS1: Disabled\n");
#endif #endif
return 0; return 0;
@ -98,7 +97,6 @@ long int
initdram(int board_type) initdram(int board_type)
{ {
long dram_size = 0; long dram_size = 0;
extern long spd_sdram (void);
#if defined(CONFIG_SPD_EEPROM) #if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram (); dram_size = spd_sdram ();
@ -110,7 +108,7 @@ initdram(int board_type)
puts(" DDR: "); puts(" DDR: ");
return dram_size; return dram_size;
#endif #endif
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* /*
* Initialize and enable DDR ECC. * Initialize and enable DDR ECC.
@ -130,7 +128,7 @@ int testdram(void)
uint *pend = (uint *) CFG_MEMTEST_END; uint *pend = (uint *) CFG_MEMTEST_END;
uint *p; uint *p;
printf("SDRAM test phase 1:\n"); puts("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++) for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa; *p = 0xaaaaaaaa;
@ -141,7 +139,7 @@ int testdram(void)
} }
} }
printf("SDRAM test phase 2:\n"); puts("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++) for (p = pstart; p < pend; p++)
*p = 0x55555555; *p = 0x55555555;
@ -152,7 +150,7 @@ int testdram(void)
} }
} }
printf("SDRAM test passed.\n"); puts("SDRAM test passed.\n");
return 0; return 0;
} }
#endif #endif
@ -177,9 +175,9 @@ long int fixed_sdram(void)
ddr->sdram_mode_1 = CFG_DDR_MODE_1; ddr->sdram_mode_1 = CFG_DDR_MODE_1;
ddr->sdram_mode_2 = CFG_DDR_MODE_2; ddr->sdram_mode_2 = CFG_DDR_MODE_2;
ddr->sdram_interval = CFG_DDR_INTERVAL; ddr->sdram_interval = CFG_DDR_INTERVAL;
ddr->sdram_data_init = CFG_DDR_DATA_INIT; ddr->sdram_data_init = CFG_DDR_DATA_INIT;
ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
#if defined (CONFIG_DDR_ECC) #if defined (CONFIG_DDR_ECC)
@ -187,7 +185,7 @@ long int fixed_sdram(void)
ddr->err_sbe = 0x00ff0000; ddr->err_sbe = 0x00ff0000;
#endif #endif
asm("sync;isync"); asm("sync;isync");
udelay(500); udelay(500);
#if defined (CONFIG_DDR_ECC) #if defined (CONFIG_DDR_ECC)
@ -198,7 +196,7 @@ long int fixed_sdram(void)
ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
#endif #endif
asm("sync; isync"); asm("sync; isync");
udelay(500); udelay(500);
#endif #endif
return CFG_SDRAM_SIZE * 1024 * 1024; return CFG_SDRAM_SIZE * 1024 * 1024;
@ -251,13 +249,12 @@ ft_board_setup(void *blob, bd_t *bd)
int len; int len;
ft_cpu_setup(blob, bd); ft_cpu_setup(blob, bd);
p = ft_get_prop(blob, "/memory/reg", &len); p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) { if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart); *p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize); *p = cpu_to_be32(bd->bi_memsize);
} }
} }
#endif #endif
@ -269,86 +266,96 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
ulong val; ulong val;
ulong corepll; ulong corepll;
if (argc > 1) { /*
cmd = argv[1][1]; * No args is a simple reset request.
switch (cmd) { */
case 'f': /* reset with frequency changed */ if (argv <= 0) {
if (argc < 5) out8(PIXIS_BASE + PIXIS_RST, 0);
goto my_usage; /* not reached */
}
cmd = argv[1][1];
switch (cmd) {
case 'f': /* reset with frequency changed */
if (argc < 5)
goto my_usage;
read_from_px_regs(0);
val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
corepll = strfractoint(argv[3]);
val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
if (val == 3) {
puts("Setting registers VCFGEN0 and VCTL\n");
read_from_px_regs(1);
puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
set_px_go();
} else
goto my_usage;
while (1); /* Not reached */
case 'l':
if (argv[2][1] == 'f') {
read_from_px_regs(0); read_from_px_regs(0);
read_from_px_regs_altbank(0);
/* reset with frequency changed */
val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); corepll = strfractoint(argv[4]);
corepll = strfractoint(argv[3]);
val = val + set_px_corepll(corepll); val = val + set_px_corepll(corepll);
val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10));
if (val == 3) { if (val == 3) {
printf("Setting registers VCFGEN0 and VCTL\n"); puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs(1); read_from_px_regs(1);
printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); read_from_px_regs_altbank(1);
set_px_go(); puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
set_px_go_with_watchdog();
} else } else
goto my_usage; goto my_usage;
while (1); /* Not reached */ while(1); /* Not reached */
case 'l': } else if(argv[2][1] == 'd'){
if (argv[2][1] == 'f') { /*
read_from_px_regs(0); * Reset from alternate bank without changing
read_from_px_regs_altbank(0); * frequencies but with watchdog timer enabled.
/* reset with frequency changed */ */
val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); read_from_px_regs(0);
read_from_px_regs_altbank(0);
puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
set_px_go_with_watchdog();
while(1); /* Not reached */
corepll = strfractoint(argv[4]); } else {
val = val + set_px_corepll(corepll); /*
val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); * Reset from next bank without changing
if (val == 3) { * frequency and without watchdog timer enabled.
printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); */
set_altbank(); read_from_px_regs(0);
read_from_px_regs(1); read_from_px_regs_altbank(0);
read_from_px_regs_altbank(1); if(argc > 2)
printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); goto my_usage;
set_px_go_with_watchdog(); puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
} else set_altbank();
goto my_usage; read_from_px_regs_altbank(1);
puts("Resetting board to boot from the other bank....\n");
while(1); /* Not reached */ set_px_go();
} else if(argv[2][1] == 'd'){
/* Reset from next bank without changing frequencies but with watchdog timer enabled */
read_from_px_regs(0);
read_from_px_regs_altbank(0);
printf("Setting registers VCFGEN1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
set_px_go_with_watchdog();
while(1); /* Not reached */
} else {
/* Reset from next bank without changing frequency and without watchdog timer enabled */
read_from_px_regs(0);
read_from_px_regs_altbank(0);
if(argc > 2)
goto my_usage;
printf("Setting registers VCFGNE1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
printf("Resetting board to boot from the other bank....\n");
set_px_go();
}
default:
goto my_usage;
} }
my_usage: default:
printf("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"); goto my_usage;
printf(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n"); }
printf("For example: reset cf 40 2.5 10\n");
printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
return;
} else my_usage:
out8(PIXIS_BASE+PIXIS_RST,0); puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
puts(" reset altbank [wd]\n");
puts("For example: reset cf 40 2.5 10\n");
puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
} }

27
cpu/mpc86xx/cpu.c
View file

@ -1,6 +1,6 @@
/* /*
* Copyright 2004 Freescale Semiconductor * Copyright 2006 Freescale Semiconductor
* Jeff Brown (jeffrey@freescale.com) * Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
* *
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
@ -55,8 +55,7 @@ int checkcpu (void)
minor = PVR_MIN(pvr); minor = PVR_MIN(pvr);
puts("CPU:\n"); puts("CPU:\n");
puts(" Core: ");
printf(" Core: ");
switch (ver) { switch (ver) {
case PVR_VER(PVR_86xx): case PVR_VER(PVR_86xx):
@ -112,11 +111,11 @@ int checkcpu (void)
printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
} }
printf(" L2: "); puts(" L2: ");
if (get_l2cr() & 0x80000000) if (get_l2cr() & 0x80000000)
printf("Enabled\n"); puts("Enabled\n");
else else
printf("Disabled\n"); puts("Disabled\n");
return 0; return 0;
} }
@ -125,7 +124,6 @@ int checkcpu (void)
static inline void static inline void
soft_restart(unsigned long addr) soft_restart(unsigned long addr)
{ {
#ifndef CONFIG_MPC8641HPCN #ifndef CONFIG_MPC8641HPCN
/* SRR0 has system reset vector, SRR1 has default MSR value */ /* SRR0 has system reset vector, SRR1 has default MSR value */
@ -137,8 +135,11 @@ soft_restart(unsigned long addr)
__asm__ __volatile__ ("rfi"); __asm__ __volatile__ ("rfi");
#else /* CONFIG_MPC8641HPCN */ #else /* CONFIG_MPC8641HPCN */
out8(PIXIS_BASE+PIXIS_RST,0);
out8(PIXIS_BASE + PIXIS_RST, 0);
#endif /* !CONFIG_MPC8641HPCN */ #endif /* !CONFIG_MPC8641HPCN */
while(1); /* not reached */ while(1); /* not reached */
} }
@ -149,10 +150,10 @@ soft_restart(unsigned long addr)
void void
do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{ {
ulong addr; #ifndef CONFIG_MPC8641HPCN
#ifdef CFG_RESET_ADDRESS #ifdef CFG_RESET_ADDRESS
addr = CFG_RESET_ADDRESS; ulong addr = CFG_RESET_ADDRESS;
#else #else
/* /*
* note: when CFG_MONITOR_BASE points to a RAM address, * note: when CFG_MONITOR_BASE points to a RAM address,
@ -160,11 +161,9 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
* address. Better pick an address known to be invalid on your * address. Better pick an address known to be invalid on your
* system and assign it to CFG_RESET_ADDRESS. * system and assign it to CFG_RESET_ADDRESS.
*/ */
addr = CFG_MONITOR_BASE - sizeof (ulong); ulong addr = CFG_MONITOR_BASE - sizeof(ulong);
#endif #endif
#ifndef CONFIG_MPC8641HPCN
/* flush and disable I/D cache */ /* flush and disable I/D cache */
__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");