GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-21 22:51:37 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

ddr: altera: Clean up of delay_for_n_mem_clocks() part 2

Browse source 
Factor out (afi_clocks - 1) into a single place instead of having it
all around the function.

Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut 2015-07-26 11:34:09 +02:00
parent 90a584b763
commit cbcaf46043
1 changed files with 10 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
drivers/ddr/altera/sequencer.c
View file

@ -767,8 +767,10 @@ static void delay_for_n_mem_clocks(const u32 clocks)
debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks); debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
/* scale (rounding up) to get afi clocks */ /* Scale (rounding up) to get afi clocks. */
afi_clocks = DIV_ROUND_UP(clocks, AFI_RATE_RATIO); afi_clocks = DIV_ROUND_UP(clocks, AFI_RATE_RATIO);
if (afi_clocks) /* Temporary underflow protection */
afi_clocks--;
/* /*
* Note, we don't bother accounting for being off a little * Note, we don't bother accounting for being off a little
@ -779,18 +781,18 @@ static void delay_for_n_mem_clocks(const u32 clocks)
*/ */
if (afi_clocks == 0) { if (afi_clocks == 0) {
; ;
} else if (afi_clocks <= 0x100) { } else if (afi_clocks < 0x100) {
inner = afi_clocks - 1; inner = afi_clocks;
outer = 0; outer = 0;
c_loop = 0; c_loop = 0;
} else if (afi_clocks <= 0x10000) { } else if (afi_clocks < 0x10000) {
inner = 0xff; inner = 0xff;
outer = (afi_clocks - 1) >> 8; outer = afi_clocks >> 8;
c_loop = 0; c_loop = 0;
} else { } else { /* >= 0x10000 */
inner = 0xff; inner = 0xff;
outer = 0xff; outer = 0xff;
c_loop = (afi_clocks - 1) >> 16; c_loop = afi_clocks >> 16;
} }
/* /*
@ -810,7 +812,7 @@ static void delay_for_n_mem_clocks(const u32 clocks)
* and sequencer rom and keeps the delays more accurate and reduces * and sequencer rom and keeps the delays more accurate and reduces
* overhead * overhead
*/ */
if (afi_clocks <= 0x100) { if (afi_clocks < 0x100) {
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
&sdr_rw_load_mgr_regs->load_cntr1); &sdr_rw_load_mgr_regs->load_cntr1);