mirror of
https://github.com/Fishwaldo/u-boot.git
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m68k: remove TASREG board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Acked-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Matthias Fuchs
Tom Rini
parent
92fa7f53f1
commit
cbdc662a2c
12 changed files with 1 additions and 11565 deletions
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@ -19,9 +19,6 @@ config TARGET_COBRA5272
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config TARGET_EB_CPU5282
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bool "Support eb_cpu5282"
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config TARGET_TASREG
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bool "Support TASREG"
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config TARGET_M5208EVBE
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bool "Support M5208EVBE"
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@ -75,7 +72,6 @@ endchoice
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source "board/BuS/eb_cpu5282/Kconfig"
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source "board/astro/mcf5373l/Kconfig"
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source "board/cobra5272/Kconfig"
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source "board/esd/tasreg/Kconfig"
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source "board/freescale/m5208evbe/Kconfig"
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source "board/freescale/m52277evb/Kconfig"
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source "board/freescale/m5235evb/Kconfig"
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@ -1,15 +0,0 @@
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if TARGET_TASREG
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config SYS_CPU
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default "mcf52x2"
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config SYS_BOARD
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default "tasreg"
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config SYS_VENDOR
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default "esd"
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config SYS_CONFIG_NAME
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default "TASREG"
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endif
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@ -1,6 +0,0 @@
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TASREG BOARD
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M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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S: Maintained
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F: board/esd/tasreg/
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F: include/configs/TASREG.h
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F: configs/TASREG_defconfig
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = tasreg.o flash.o
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@ -1,9 +0,0 @@
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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CONFIG_SYS_TEXT_BASE = 0xffc00000
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@ -1,59 +0,0 @@
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/*
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* (C) Copyright 2001
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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/*#include <asm/ppc4xx.h>*/
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#include <asm/processor.h>
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/*
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* include common flash code (for esd boards)
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*/
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#include "../common/flash.c"
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (vu_long * addr, flash_info_t * info);
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static void flash_get_offsets (ulong base, flash_info_t * info);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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unsigned long size_b0;
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int i;
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/* Init: no FLASHes known */
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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}
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/* Static FLASH Bank configuration here - FIXME XXX */
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size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0<<20);
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}
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/* Setup offsets */
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flash_get_offsets (-size_b0, &flash_info[0]);
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/* test-only: todo: Re-do sizing to get full correct info */
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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CONFIG_SYS_FLASH_BASE,
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CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-1,
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&flash_info[0]);
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flash_info[0].size = size_b0;
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return (size_b0);
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}
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File diff suppressed because it is too large
Load diff
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@ -1,432 +0,0 @@
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/*
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* (C) Copyright 2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <malloc.h>
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#include <asm/m5249.h>
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#include <asm/io.h>
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/* Prototypes */
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int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
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int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
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#if 0
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#define FPGA_DEBUG
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#endif
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/* predefine these here for FPGA programming (before including fpga.c) */
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#define SET_FPGA(data) mbar2_writeLong(MCFSIM_GPIO1_OUT, data)
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#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_DONE)
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#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_INIT)
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#define FPGA_PROG_ACTIVE_HIGH /* on this platform is PROG active high! */
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#define out32(a,b) /* nothing to do (gpio already configured) */
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/* fpga configuration data - generated by bin2cc */
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const unsigned char fpgadata[] =
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{
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#include "fpgadata.c"
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};
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/*
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* include common fpga code (for esd boards)
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*/
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#include "../common/fpga.c"
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int checkboard (void) {
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ulong val;
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uchar val8;
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puts ("Board: ");
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puts("esd TASREG");
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val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
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printf(" (Switch=%1X)\n", val8);
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/*
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* Set LED on
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*/
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val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
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mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
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return 0;
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};
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phys_size_t initdram (int board_type) {
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unsigned long junk = 0xa5a59696;
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/*
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* Note:
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* RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
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*/
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#ifdef CONFIG_SYS_FAST_CLK
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/*
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* Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
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* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
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*/
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mbar_writeShort(MCFSIM_DCR, 0x8239);
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#elif CONFIG_SYS_PLL_BYPASS
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/*
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* Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
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* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
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*/
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mbar_writeShort(MCFSIM_DCR, 0x8202);
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#else
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/*
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* Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
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* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
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*/
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mbar_writeShort(MCFSIM_DCR, 0x8222);
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#endif
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/*
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* SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
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* PM=1 (continuous page mode)
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*/
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/* RE=0 (keep auto-refresh disabled while setting up registers) */
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mbar_writeLong(MCFSIM_DACR0, 0x00003324);
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/* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
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mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
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/** Precharge sequence **/
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mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
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out_be32((void *)0, junk); /* write to a memory location to init. precharge */
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udelay(0x10); /* Allow several Precharge cycles */
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/** Refresh Sequence **/
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mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
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udelay(0x7d0); /* Allow gobs of refresh cycles */
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/** Mode Register initialization **/
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mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
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out_be32((void *)0x800, junk); /* Access RAM to initialize the mode register */
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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};
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int testdram (void) {
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/* TODO: XXX XXX XXX */
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printf ("DRAM test not implemented!\n");
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return (0);
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}
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int misc_init_r (void)
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{
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unsigned char *dst;
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ulong len = sizeof(fpgadata);
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int status;
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int index;
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int i;
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uchar buf[8];
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dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
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if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
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printf ("GUNZIP ERROR - must RESET board to recover\n");
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do_reset (NULL, 0, 0, NULL);
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}
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status = fpga_boot(dst, len);
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if (status != 0) {
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printf("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf("(Timeout: DONE not high after programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("FPGA: %s\n", &(dst[index+1]));
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index += len+3;
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}
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putc ('\n');
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/* delayed reboot */
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for (i=20; i>0; i--) {
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printf("Rebooting in %2d seconds \r",i);
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for (index=0;index<1000;index++)
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udelay(1000);
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}
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putc ('\n');
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do_reset(NULL, 0, 0, NULL);
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}
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puts("FPGA: ");
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("%s ", &(dst[index+1]));
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index += len+3;
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}
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putc ('\n');
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free(dst);
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/*
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*
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*/
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buf[0] = 0x00;
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buf[1] = 0x32;
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buf[2] = 0x3f;
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i2c_write(0x38, 0, 0, buf, 3);
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return (0);
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}
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#if 1 /* test-only: board specific test commands */
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int i2c_probe(uchar addr);
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/*
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*/
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int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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ulong addr;
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if (argc < 2) {
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puts("ERROR!\n");
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return -1;
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}
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addr = simple_strtol (argv[1], NULL, 16);
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printf("i2c probe looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
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for (;;) {
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i2c_probe(addr);
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/* Abort if ctrl-c was pressed */
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if (ctrlc()) {
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puts("\nAbort\n");
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return 0;
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}
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udelay(1000);
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}
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return 0;
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}
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U_BOOT_CMD(
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iploop, 2, 1, do_iploop,
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"i2c probe loop <addr>",
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""
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);
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/*
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*/
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int do_codec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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uchar buf[8];
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out_be16((void *)0xe0000000, 0x4000);
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udelay(5000); /* wait for 5ms */
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buf[0] = 0x10;
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buf[1] = 0x07;
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buf[2] = 0x03;
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i2c_write(0x10, 0, 0, buf, 3);
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buf[0] = 0x10;
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buf[1] = 0x01;
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buf[2] = 0x80;
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i2c_write(0x10, 0, 0, buf, 3);
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buf[0] = 0x10;
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buf[1] = 0x02;
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buf[2] = 0x03;
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i2c_write(0x10, 0, 0, buf, 3);
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buf[0] = 0x10;
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buf[1] = 0x03;
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buf[2] = 0x29;
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i2c_write(0x10, 0, 0, buf, 3);
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buf[0] = 0x10;
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buf[1] = 0x04;
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buf[2] = 0x00;
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i2c_write(0x10, 0, 0, buf, 3);
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buf[0] = 0x10;
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buf[1] = 0x05;
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buf[2] = 0x00;
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i2c_write(0x10, 0, 0, buf, 3);
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buf[0] = 0x10;
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buf[1] = 0x07;
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buf[2] = 0x02;
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i2c_write(0x10, 0, 0, buf, 3);
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return 0;
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}
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U_BOOT_CMD(
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codec, 1, 1, do_codec,
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"Enable codec",
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""
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);
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/*
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*/
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int do_saa(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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ulong addr;
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ulong instr;
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ulong cntrl;
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ulong data;
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uchar buf[8];
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if (argc < 5) {
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puts("ERROR!\n");
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return -1;
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}
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addr = simple_strtol (argv[1], NULL, 16);
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instr = simple_strtol (argv[2], NULL, 16);
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cntrl = simple_strtol (argv[3], NULL, 16);
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data = simple_strtol (argv[4], NULL, 16);
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buf[0] = (uchar)instr;
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buf[1] = (uchar)cntrl;
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buf[2] = (uchar)data;
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i2c_write(addr, 0, 0, buf, 3);
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return 0;
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}
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U_BOOT_CMD(
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saa, 5, 1, do_saa,
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"Write to SAA1064 <addr> <instr> <cntrl> <data>",
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""
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);
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/*
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*/
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int do_iwrite(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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ulong addr;
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ulong data0;
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ulong data1;
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ulong data2;
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ulong data3;
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uchar buf[8];
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int cnt;
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if (argc < 3) {
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puts("ERROR!\n");
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return -1;
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}
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addr = simple_strtol (argv[1], NULL, 16);
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cnt = simple_strtol (argv[2], NULL, 16);
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data0 = simple_strtol (argv[3], NULL, 16);
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data1 = simple_strtol (argv[4], NULL, 16);
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data2 = simple_strtol (argv[5], NULL, 16);
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data3 = simple_strtol (argv[6], NULL, 16);
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printf("Writing %d bytes to device %lx!\n", cnt, addr);
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buf[0] = (uchar)data0;
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buf[1] = (uchar)data1;
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buf[2] = (uchar)data2;
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buf[3] = (uchar)data3;
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i2c_write(addr, 0, 0, buf, cnt);
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return 0;
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}
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U_BOOT_CMD(
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iwrite, 6, 1, do_iwrite,
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"Write n bytes to I2C-device",
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"addr cnt data0 ... datan"
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);
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/*
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*/
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||||
int do_iread(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
ulong addr;
|
||||
ulong cnt;
|
||||
uchar buf[32];
|
||||
int i;
|
||||
|
||||
if (argc < 3) {
|
||||
puts("ERROR!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
addr = simple_strtol (argv[1], NULL, 16);
|
||||
cnt = simple_strtol (argv[2], NULL, 16);
|
||||
|
||||
i2c_read(addr, 0, 0, buf, cnt);
|
||||
printf("I2C Data:");
|
||||
for (i=0; i<cnt; i++) {
|
||||
printf(" %02X", buf[i]);
|
||||
}
|
||||
printf("\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
iread, 3, 1, do_iread,
|
||||
"Read from I2C <addr> <cnt>",
|
||||
""
|
||||
);
|
||||
|
||||
/*
|
||||
*/
|
||||
int do_ireadl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
ulong addr;
|
||||
uchar buf[32];
|
||||
int cnt;
|
||||
|
||||
if (argc < 2) {
|
||||
puts("ERROR!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
addr = simple_strtol (argv[1], NULL, 16);
|
||||
cnt = 1;
|
||||
|
||||
printf("iread looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
|
||||
|
||||
for (;;) {
|
||||
i2c_read(addr, 0, 0, buf, cnt);
|
||||
|
||||
/* Abort if ctrl-c was pressed */
|
||||
if (ctrlc()) {
|
||||
puts("\nAbort\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
udelay(3000);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
U_BOOT_CMD(
|
||||
ireadl, 2, 1, do_ireadl,
|
||||
"Read-loop from I2C <addr>",
|
||||
""
|
||||
);
|
||||
#endif
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(m68k)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
arch/m68k/cpu/mcf52x2/start.o (.text*)
|
||||
|
||||
*(.text*)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
|
||||
.reloc :
|
||||
{
|
||||
__got_start = .;
|
||||
KEEP(*(.got))
|
||||
__got_end = .;
|
||||
_GOT2_TABLE_ = .;
|
||||
KEEP(*(.got2))
|
||||
_FIXUP_TABLE_ = .;
|
||||
KEEP(*(.fixup))
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
_sbss = .;
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
}
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
CONFIG_M68K=y
|
||||
CONFIG_TARGET_TASREG=y
|
||||
|
|
@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
|
|||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
TASREG m68k mcf52x2 - - Matthias Fuchs <matthias.fuchs@esd.eu>
|
||||
A3000 powerpc mpc824x - -
|
||||
CPC45 powerpc mpc824x - - Josef Wagner <Wagner@Microsys.de>
|
||||
CU824 powerpc mpc824x - - Wolfgang Denk <wd@denx.de>
|
||||
|
|
|
|||
|
|
@ -1,287 +0,0 @@
|
|||
/*
|
||||
* Configuation settings for the esd TASREG board.
|
||||
*
|
||||
* (C) Copyright 2004
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef _TASREG_H
|
||||
#define _TASREG_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/m5249.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_MCF52x2 /* define processor family */
|
||||
#define CONFIG_M5249 /* define processor type */
|
||||
|
||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
|
||||
|
||||
#define CONFIG_MCFTMR
|
||||
|
||||
#define CONFIG_MCFUART
|
||||
#define CONFIG_SYS_UART_PORT (0)
|
||||
#define CONFIG_BAUDRATE 19200
|
||||
|
||||
#undef CONFIG_WATCHDOG
|
||||
|
||||
#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_BSP
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_I2C
|
||||
|
||||
#undef CONFIG_CMD_NET
|
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
|
||||
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x400
|
||||
#define CONFIG_SYS_MEMTEST_END 0x380000
|
||||
|
||||
/*
|
||||
* Clock configuration: enable only one of the following options
|
||||
*/
|
||||
|
||||
#if 0 /* this setting will run the cpu at 11MHz */
|
||||
#define CONFIG_SYS_PLL_BYPASS 1 /* bypass PLL for test purpose */
|
||||
#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */
|
||||
#define CONFIG_SYS_CLK 11289600 /* PLL bypass */
|
||||
#endif
|
||||
|
||||
#if 0 /* this setting will run the cpu at 70MHz */
|
||||
#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
|
||||
#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */
|
||||
#define CONFIG_SYS_CLK 72185018 /* The next lower speed */
|
||||
#endif
|
||||
|
||||
#if 1 /* this setting will run the cpu at 140MHz */
|
||||
#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
|
||||
#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
|
||||
#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
|
||||
#define CONFIG_SYS_MBAR2 0x80000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
|
||||
|
||||
#if 0 /* push-pull */
|
||||
#define SDA 0x00800000
|
||||
#define SCL 0x00000008
|
||||
#define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
|
||||
#define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
|
||||
#define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
|
||||
#define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
|
||||
#define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
|
||||
#define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
|
||||
#define I2C_INIT {OUT1|=SDA;OUT0|=SCL;}
|
||||
#define I2C_READ ((IN1&SDA)?1:0)
|
||||
#define I2C_SDA(x) {if(x)OUT1|=SDA;else OUT1&=~SDA;}
|
||||
#define I2C_SCL(x) {if(x)OUT0|=SCL;else OUT0&=~SCL;}
|
||||
#define I2C_DELAY {udelay(5);}
|
||||
#define I2C_ACTIVE {DIR1|=SDA;}
|
||||
#define I2C_TRISTATE {DIR1&=~SDA;}
|
||||
#else /* open-collector */
|
||||
#define SDA 0x00800000
|
||||
#define SCL 0x00000008
|
||||
#define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
|
||||
#define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
|
||||
#define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
|
||||
#define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
|
||||
#define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
|
||||
#define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
|
||||
#define I2C_INIT {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
|
||||
#define I2C_READ ((IN1&SDA)?1:0)
|
||||
#define I2C_SDA(x) {if(x)DIR1&=~SDA;else DIR1|=SDA;}
|
||||
#define I2C_SCL(x) {if(x)DIR0&=~SCL;else DIR0|=SCL;}
|
||||
#define I2C_DELAY {udelay(5);}
|
||||
#define I2C_ACTIVE {DIR1|=SDA;}
|
||||
#define I2C_TRISTATE {DIR1&=~SDA;}
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
|
||||
/*
|
||||
* The Catalyst CAT24WC32 has 32 byte page write mode using
|
||||
* last 5 bits of the address
|
||||
*/
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR 0xFFC40000 /* Address of Environment Sector*/
|
||||
#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
|
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
|
||||
|
||||
#if 0 /* test-only */
|
||||
#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x20000
|
||||
#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */
|
||||
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization ??
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
|
||||
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
|
||||
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
|
||||
/*
|
||||
* The following defines are added for buggy IOP480 byte interface.
|
||||
* All other boards should use the standard values (CPCI405 etc.)
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
|
||||
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
|
||||
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16
|
||||
|
||||
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - 8)
|
||||
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - 4)
|
||||
#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
|
||||
#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
|
||||
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
|
||||
CF_ACR_EN | CF_ACR_SM_ALL)
|
||||
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
|
||||
CF_CACR_DBWE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Memory bank definitions
|
||||
*/
|
||||
|
||||
/* CS0 - AMD Flash, address 0xffc00000 */
|
||||
#define CONFIG_SYS_CS0_BASE 0xffc00000
|
||||
#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
|
||||
/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
|
||||
#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
|
||||
|
||||
/* CS1 - FPGA, address 0xe0000000 */
|
||||
#define CONFIG_SYS_CS1_BASE 0xe0000000
|
||||
#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
|
||||
#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Port configuration
|
||||
*/
|
||||
#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
|
||||
#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
|
||||
#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
|
||||
#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
|
||||
#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
|
||||
#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
|
||||
|
||||
#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FPGA stuff
|
||||
*/
|
||||
#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
|
||||
#define CONFIG_SYS_FPGA_MAX_SIZE 512*1024 /* 512kByte is enough for XC2S200*/
|
||||
|
||||
/* FPGA program pin configuration */
|
||||
#define CONFIG_SYS_FPGA_PRG 0x00010000 /* FPGA program pin (ppc output) */
|
||||
#define CONFIG_SYS_FPGA_CLK 0x00040000 /* FPGA clk pin (ppc output) */
|
||||
#define CONFIG_SYS_FPGA_DATA 0x00020000 /* FPGA data pin (ppc output) */
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||||
#define CONFIG_SYS_FPGA_INIT 0x00080000 /* FPGA init pin (ppc input) */
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||||
#define CONFIG_SYS_FPGA_DONE 0x00100000 /* FPGA done pin (ppc input) */
|
||||
|
||||
#endif /* _TASREG_H */
|
||||
Loading…
Add table
Reference in a new issue