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ARC: [plat-axs10x]: migrate to DM_MMC
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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54858311df
commit
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3 changed files with 30 additions and 29 deletions
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@ -31,6 +31,25 @@
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#clock-cells = <0>;
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u-boot,dm-pre-reloc;
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};
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mmcclk_ciu: mmcclk-ciu {
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compatible = "fixed-clock";
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/*
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* DW sdio controller has external ciu clock divider
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* controlled via register in SDIO IP. It divides
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* sdio_ref_clk (which comes from CGU) by 16 for
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* default. So default mmcclk clock (which comes
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* to sdk_in) is 25000000 Hz.
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*/
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clock-frequency = <25000000>;
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#clock-cells = <0>;
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};
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mmcclk_biu: mmcclk-biu {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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};
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ethernet@18000 {
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@ -53,6 +72,15 @@
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reg = < 0x60000 0x100 >;
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};
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mmc: mmc@15000 {
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compatible = "snps,dw-mshc";
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reg = <0x15000 0x400>;
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bus-width = <4>;
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clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
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clock-names = "biu", "ciu";
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max-frequency = <25000000>;
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};
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uart0: serial0@22000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x22000 0x100>;
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@ -11,35 +11,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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int board_mmc_init(bd_t *bis)
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{
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struct dwmci_host *host = NULL;
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host = malloc(sizeof(struct dwmci_host));
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if (!host) {
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printf("dwmci_host malloc fail!\n");
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return 1;
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}
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memset(host, 0, sizeof(struct dwmci_host));
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host->name = "Synopsys Mobile storage";
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host->ioaddr = (void *)ARC_DWMMC_BASE;
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host->buswidth = 4;
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host->dev_index = 0;
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host->bus_hz = 50000000;
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add_dwmci(host, host->bus_hz / 2, 400000);
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return 0;
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct dwmci_host *host = mmc->priv;
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return !(dwmci_readl(host, DWMCI_CDETECT) & 1);
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}
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#define AXS_MB_CREG 0xE0011000
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int board_early_init_f(void)
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@ -35,7 +35,9 @@ CONFIG_DM=y
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CONFIG_DM_GPIO=y
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CONFIG_HSDK_CREG_GPIO=y
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CONFIG_MMC=y
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CONFIG_DM_MMC=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_SNPS=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_STMICRO=y
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