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Merge branch 'master' of /home/wd/git/u-boot/custodians
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commit
cc3074c322
3 changed files with 70 additions and 6 deletions
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@ -111,17 +111,72 @@ void reconfigure_pll(u32 new_cpu_freq)
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mtcpr(CPR0_SPCID, reg);
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mtcpr(CPR0_SPCID, reg);
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reset_needed = 1;
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reset_needed = 1;
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}
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}
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}
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/* Set reload inhibit so configuration will persist across
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/* Get current value of FWDVA.*/
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* processor resets */
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mfcpr(CPR0_PLLD, reg);
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temp = (reg & PLLD_FWDVA_MASK) >> 16;
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/*
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* Check to see if FWDVA has been set to value of 1. if it has we must
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* modify it.
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*/
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if (temp == 1) {
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mfcpr(CPR0_PLLD, reg);
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/* Get current value of fbdv. */
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temp = (reg & PLLD_FBDV_MASK) >> 24;
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fbdv = temp ? temp : 32;
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/* Get current value of lfbdv. */
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temp = (reg & PLLD_LFBDV_MASK);
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lfbdv = temp ? temp : 64;
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/*
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* Load register that contains current boot strapping option.
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*/
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mfcpr(CPR0_ICFG, reg);
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/* Shift strapping option into low 3 bits.*/
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reg = (reg >> 28);
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if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) ||
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(reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) {
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/*
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* Get current value of FWDVA. Assign current FWDVA to
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* new FWDVB.
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*/
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mfcpr(CPR0_PLLD, reg);
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target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16;
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fwdvb = target_fwdvb ? target_fwdvb : 8;
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/*
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* Get current value of FWDVB. Assign current FWDVB to
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* new FWDVA.
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*/
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target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8;
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fwdva = target_fwdva ? target_fwdva : 16;
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/*
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* Update CPR0_PLLD with switched FWDVA and FWDVB.
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*/
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reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
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PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
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reg |= ((fwdva == 16 ? 0 : fwdva) << 16) |
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((fwdvb == 8 ? 0 : fwdvb) << 8) |
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((fbdv == 32 ? 0 : fbdv) << 24) |
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(lfbdv == 64 ? 0 : lfbdv);
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mtcpr(CPR0_PLLD, reg);
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/* Acknowledge that a reset is required. */
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reset_needed = 1;
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}
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}
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if (reset_needed) {
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/*
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* Set reload inhibit so configuration will persist across
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* processor resets
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*/
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mfcpr(CPR0_ICFG, reg);
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mfcpr(CPR0_ICFG, reg);
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reg &= ~CPR0_ICFG_RLI_MASK;
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reg &= ~CPR0_ICFG_RLI_MASK;
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reg |= 1 << 31;
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reg |= 1 << 31;
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mtcpr(CPR0_ICFG, reg);
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mtcpr(CPR0_ICFG, reg);
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}
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/* Reset processor if configuration changed */
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/* Reset processor if configuration changed */
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if (reset_needed) {
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__asm__ __volatile__ ("sync; isync");
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__asm__ __volatile__ ("sync; isync");
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mtspr(SPRN_DBCR0, 0x20000000);
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mtspr(SPRN_DBCR0, 0x20000000);
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}
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}
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@ -537,7 +537,10 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector,
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ulong start;
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ulong start;
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#if CONFIG_SYS_HZ != 1000
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#if CONFIG_SYS_HZ != 1000
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tout *= CONFIG_SYS_HZ/1000;
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if ((ulong)CONFIG_SYS_HZ > 100000)
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tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */
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else
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tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
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#endif
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#endif
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/* Wait for command completion */
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/* Wait for command completion */
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@ -68,6 +68,12 @@
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#define CPR0_SPCID 0x0120
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#define CPR0_SPCID 0x0120
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#define CPR0_ICFG 0x0140
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#define CPR0_ICFG 0x0140
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/* 440EPX boot strap options */
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#define BOOT_STRAP_OPTION_A 0x00000000
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#define BOOT_STRAP_OPTION_B 0x00000001
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#define BOOT_STRAP_OPTION_D 0x00000003
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#define BOOT_STRAP_OPTION_E 0x00000004
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/* 440gx sdr register definations */
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/* 440gx sdr register definations */
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#define SDR0_SDSTP0 0x0020 /* */
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#define SDR0_SDSTP0 0x0020 /* */
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#define SDR0_SDSTP1 0x0021 /* */
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#define SDR0_SDSTP1 0x0021 /* */
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