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Merge branch 'master' of /home/wd/git/u-boot/custodians

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This commit is contained in:
Wolfgang Denk 2010-03-28 00:15:20 +01:00
commit cc3074c322
3 changed files with 70 additions and 6 deletions
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65
cpu/ppc4xx/cpu_init.c
View file

@ -111,17 +111,72 @@ void reconfigure_pll(u32 new_cpu_freq)
mtcpr(CPR0_SPCID, reg); mtcpr(CPR0_SPCID, reg);
reset_needed = 1; reset_needed = 1;
} }
}
/* Set reload inhibit so configuration will persist across /* Get current value of FWDVA.*/
* processor resets */ mfcpr(CPR0_PLLD, reg);
temp = (reg & PLLD_FWDVA_MASK) >> 16;
/*
* Check to see if FWDVA has been set to value of 1. if it has we must
* modify it.
*/
if (temp == 1) {
mfcpr(CPR0_PLLD, reg);
/* Get current value of fbdv. */
temp = (reg & PLLD_FBDV_MASK) >> 24;
fbdv = temp ? temp : 32;
/* Get current value of lfbdv. */
temp = (reg & PLLD_LFBDV_MASK);
lfbdv = temp ? temp : 64;
/*
* Load register that contains current boot strapping option.
*/
mfcpr(CPR0_ICFG, reg);
/* Shift strapping option into low 3 bits.*/
reg = (reg >> 28);
if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) ||
(reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) {
/*
* Get current value of FWDVA. Assign current FWDVA to
* new FWDVB.
*/
mfcpr(CPR0_PLLD, reg);
target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16;
fwdvb = target_fwdvb ? target_fwdvb : 8;
/*
* Get current value of FWDVB. Assign current FWDVB to
* new FWDVA.
*/
target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8;
fwdva = target_fwdva ? target_fwdva : 16;
/*
* Update CPR0_PLLD with switched FWDVA and FWDVB.
*/
reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
reg |= ((fwdva == 16 ? 0 : fwdva) << 16) |
((fwdvb == 8 ? 0 : fwdvb) << 8) |
((fbdv == 32 ? 0 : fbdv) << 24) |
(lfbdv == 64 ? 0 : lfbdv);
mtcpr(CPR0_PLLD, reg);
/* Acknowledge that a reset is required. */
reset_needed = 1;
}
}
if (reset_needed) {
/*
* Set reload inhibit so configuration will persist across
* processor resets
*/
mfcpr(CPR0_ICFG, reg); mfcpr(CPR0_ICFG, reg);
reg &= ~CPR0_ICFG_RLI_MASK; reg &= ~CPR0_ICFG_RLI_MASK;
reg |= 1 << 31; reg |= 1 << 31;
mtcpr(CPR0_ICFG, reg); mtcpr(CPR0_ICFG, reg);
}
/* Reset processor if configuration changed */ /* Reset processor if configuration changed */
if (reset_needed) {
__asm__ __volatile__ ("sync; isync"); __asm__ __volatile__ ("sync; isync");
mtspr(SPRN_DBCR0, 0x20000000); mtspr(SPRN_DBCR0, 0x20000000);
} }

5
drivers/mtd/cfi_flash.c
View file

@ -537,7 +537,10 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector,
ulong start; ulong start;
#if CONFIG_SYS_HZ != 1000 #if CONFIG_SYS_HZ != 1000
tout *= CONFIG_SYS_HZ/1000; if ((ulong)CONFIG_SYS_HZ > 100000)
tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */
else
tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
#endif #endif
/* Wait for command completion */ /* Wait for command completion */

6
include/ppc440.h
View file

@ -68,6 +68,12 @@
#define CPR0_SPCID 0x0120 #define CPR0_SPCID 0x0120
#define CPR0_ICFG 0x0140 #define CPR0_ICFG 0x0140
/* 440EPX boot strap options */
#define BOOT_STRAP_OPTION_A 0x00000000
#define BOOT_STRAP_OPTION_B 0x00000001
#define BOOT_STRAP_OPTION_D 0x00000003
#define BOOT_STRAP_OPTION_E 0x00000004
/* 440gx sdr register definations */ /* 440gx sdr register definations */
#define SDR0_SDSTP0 0x0020 /* */ #define SDR0_SDSTP0 0x0020 /* */
#define SDR0_SDSTP1 0x0021 /* */ #define SDR0_SDSTP1 0x0021 /* */