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serial: add LPC32X0 high-speed UART devices support
This change adds an implementation of high-speed UART found on NXP LPC32X0 SoCs. Such UARTs are enumerated as UART1, UART2 and UART7. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Marek Vasut <marek.vasut@gmail.com>
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3 changed files with 173 additions and 0 deletions
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@ -22,6 +22,66 @@
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#include <asm/types.h>
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/* 14-clock UART Registers */
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struct hsuart_regs {
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union {
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u32 rx; /* Receiver FIFO */
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u32 tx; /* Transmitter FIFO */
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};
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u32 level; /* FIFO Level Register */
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u32 iir; /* Interrupt ID Register */
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u32 ctrl; /* Control Register */
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u32 rate; /* Rate Control Register */
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};
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/* 14-clock UART Receiver FIFO Register bits */
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#define HSUART_RX_BREAK (1 << 10)
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#define HSUART_RX_ERROR (1 << 9)
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#define HSUART_RX_EMPTY (1 << 8)
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#define HSUART_RX_DATA (0xff << 0)
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/* 14-clock UART Level Register bits */
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#define HSUART_LEVEL_TX (0xff << 8)
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#define HSUART_LEVEL_RX (0xff << 0)
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/* 14-clock UART Interrupt Identification Register bits */
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#define HSUART_IIR_TX_INT_SET (1 << 6)
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#define HSUART_IIR_RX_OE (1 << 5)
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#define HSUART_IIR_BRK (1 << 4)
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#define HSUART_IIR_FE (1 << 3)
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#define HSUART_IIR_RX_TIMEOUT (1 << 2)
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#define HSUART_IIR_RX_TRIG (1 << 1)
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#define HSUART_IIR_TX (1 << 0)
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/* 14-clock UART Control Register bits */
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#define HSUART_CTRL_HRTS_INV (1 << 21)
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#define HSUART_CTRL_HRTS_TRIG_48 (0x3 << 19)
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#define HSUART_CTRL_HRTS_TRIG_32 (0x2 << 19)
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#define HSUART_CTRL_HRTS_TRIG_16 (0x1 << 19)
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#define HSUART_CTRL_HRTS_TRIG_8 (0x0 << 19)
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#define HSUART_CTRL_HRTS_EN (1 << 18)
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#define HSUART_CTRL_TMO_16 (0x3 << 16)
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#define HSUART_CTRL_TMO_8 (0x2 << 16)
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#define HSUART_CTRL_TMO_4 (0x1 << 16)
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#define HSUART_CTRL_TMO_DISABLED (0x0 << 16)
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#define HSUART_CTRL_HCTS_INV (1 << 15)
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#define HSUART_CTRL_HCTS_EN (1 << 14)
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#define HSUART_CTRL_HSU_OFFSET(n) ((n) << 9)
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#define HSUART_CTRL_HSU_BREAK (1 << 8)
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#define HSUART_CTRL_HSU_ERR_INT_EN (1 << 7)
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#define HSUART_CTRL_HSU_RX_INT_EN (1 << 6)
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#define HSUART_CTRL_HSU_TX_INT_EN (1 << 5)
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#define HSUART_CTRL_HSU_RX_TRIG_48 (0x5 << 2)
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#define HSUART_CTRL_HSU_RX_TRIG_32 (0x4 << 2)
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#define HSUART_CTRL_HSU_RX_TRIG_16 (0x3 << 2)
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#define HSUART_CTRL_HSU_RX_TRIG_8 (0x2 << 2)
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#define HSUART_CTRL_HSU_RX_TRIG_4 (0x1 << 2)
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#define HSUART_CTRL_HSU_RX_TRIG_1 (0x0 << 2)
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#define HSUART_CTRL_HSU_TX_TRIG_16 (0x3 << 0)
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#define HSUART_CTRL_HSU_TX_TRIG_8 (0x2 << 0)
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#define HSUART_CTRL_HSU_TX_TRIG_4 (0x1 << 0)
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#define HSUART_CTRL_HSU_TX_TRIG_0 (0x0 << 0)
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/* UART Control Registers */
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struct uart_ctrl_regs {
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u32 ctrl; /* Control Register */
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@ -29,6 +29,7 @@ COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o
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COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
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COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o
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COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o
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COBJS-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
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COBJS-$(CONFIG_MCFUART) += mcfuart.o
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COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o
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COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
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112
drivers/serial/lpc32xx_hsuart.c
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112
drivers/serial/lpc32xx_hsuart.c
Normal file
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@ -0,0 +1,112 @@
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/*
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* Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/uart.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct hsuart_regs *hsuart = (struct hsuart_regs *)HS_UART_BASE;
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static void lpc32xx_hsuart_set_baudrate(void)
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{
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u32 div;
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/* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */
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div = (get_serial_clock() / 14 + gd->baudrate / 2) / gd->baudrate - 1;
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if (div > 255)
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div = 255;
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writel(div, &hsuart->rate);
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}
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static int lpc32xx_hsuart_getc(void)
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{
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while (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
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/* NOP */;
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return readl(&hsuart->rx) & HSUART_RX_DATA;
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}
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static void lpc32xx_hsuart_putc(const char c)
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{
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writel(c, &hsuart->tx);
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/* Wait for character to be sent */
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while (readl(&hsuart->level) & HSUART_LEVEL_TX)
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/* NOP */;
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}
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static int lpc32xx_hsuart_tstc(void)
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{
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if (readl(&hsuart->level) & HSUART_LEVEL_RX)
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return 1;
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return 0;
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}
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static void lpc32xx_hsuart_init(void)
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{
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lpc32xx_hsuart_set_baudrate();
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/* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
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writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
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HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
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&hsuart->ctrl);
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}
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void serial_setbrg(void)
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{
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return lpc32xx_hsuart_set_baudrate();
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}
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void serial_putc(const char c)
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{
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lpc32xx_hsuart_putc(c);
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/* If \n, also do \r */
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if (c == '\n')
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lpc32xx_hsuart_putc('\r');
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}
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int serial_getc(void)
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{
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return lpc32xx_hsuart_getc();
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}
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void serial_puts(const char *s)
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{
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while (*s)
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serial_putc(*s++);
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}
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int serial_tstc(void)
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{
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return lpc32xx_hsuart_tstc();
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}
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int serial_init(void)
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{
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lpc32xx_hsuart_init();
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return 0;
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}
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