mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-15 19:51:37 +00:00
clk: renesas: Reinstate RPC clock on R-Car D3/E3
Reinstate RPC clock on D3/E3 after Linux 5.12 synchronization. The D3 and E3 clock drivers do not contain RPC clock entries mainline Linux yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This commit is contained in:
parent
f7b4e4c094
commit
ccc2c9aab1
2 changed files with 18 additions and 0 deletions
|
@ -44,6 +44,7 @@ enum clk_ids {
|
|||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_RINT,
|
||||
CLK_OCO,
|
||||
|
||||
|
@ -74,6 +75,13 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
|
|||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A77990_CLK_RPC),
|
||||
|
||||
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
|
||||
|
@ -211,6 +219,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
|
|||
DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("rpc", 917, R8A77990_CLK_RPC),
|
||||
DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP),
|
||||
|
|
|
@ -42,6 +42,7 @@ enum clk_ids {
|
|||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_RINT,
|
||||
CLK_OCO,
|
||||
|
||||
|
@ -70,6 +71,13 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
|
|||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A77995_CLK_RPC),
|
||||
|
||||
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
|
||||
|
@ -171,6 +179,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
|
|||
DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("rpc", 917, R8A77995_CLK_RPC),
|
||||
DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
|
||||
|
|
Loading…
Add table
Reference in a new issue