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clk: clk_stm32h7: migrate trace to dev and log macro
Change debug and pr_ macro to dev macro and define LOG_CATEGORY. Remove the "%s:" __func__ header as it is managed by dev macro (dev->name is displayed) or log macro (CONFIG_LOGF_FUNC). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrick Delaunay
Patrick Delaunay
parent
06a126313e
commit
cddc30d647
1 changed files with 38 additions and 32 deletions
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@ -4,6 +4,8 @@
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* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
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*/
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#define LOG_CATEGORY UCLASS_CLK
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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@ -11,6 +13,7 @@
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <dm/root.h>
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#include <linux/bitops.h>
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@ -465,18 +468,18 @@ static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc)
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int ret;
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const char *name = pllsrc_name[pllsrc];
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debug("%s name %s\n", __func__, name);
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log_debug("pllsrc name %s\n", name);
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clk.id = 0;
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ret = uclass_get_device_by_name(UCLASS_CLK, name, &fixed_clock_dev);
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if (ret) {
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pr_err("Can't find clk %s (%d)", name, ret);
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log_err("Can't find clk %s (%d)", name, ret);
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return 0;
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}
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ret = clk_request(fixed_clock_dev, &clk);
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if (ret) {
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pr_err("Can't request %s clk (%d)", name, ret);
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log_err("Can't request %s clk (%d)", name, ret);
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return 0;
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}
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@ -484,8 +487,7 @@ static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc)
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if (pllsrc == HSI)
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divider = stm32_get_HSI_divider(regs);
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debug("%s divider %d rate %ld\n", __func__,
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divider, clk_get_rate(&clk));
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log_debug("divider %d rate %ld\n", divider, clk_get_rate(&clk));
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return clk_get_rate(&clk) >> divider;
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};
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@ -516,7 +518,7 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,
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break;
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case RCC_PLLCKSELR_PLLSRC_NO_CLK:
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/* shouldn't happen */
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pr_err("wrong value for RCC_PLLCKSELR register\n");
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log_err("wrong value for RCC_PLLCKSELR register\n");
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pllsrc = 0;
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break;
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}
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@ -546,10 +548,10 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,
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vco = (pllsrc / divm1) * divn1;
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rate = (pllsrc * fracn1) / (divm1 * 8192);
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debug("%s divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n",
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__func__, divm1, divn1, divp1, divq1, divr1);
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debug("%s fracn1 = %d vco = %ld rate = %ld\n",
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__func__, fracn1, vco, rate);
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log_debug("divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n",
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divm1, divn1, divp1, divq1, divr1);
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log_debug("fracn1 = %d vco = %ld rate = %ld\n",
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fracn1, vco, rate);
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switch (output) {
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case PLL1_P_CK:
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@ -610,7 +612,7 @@ u32 psc = stm32_get_apb_psc(regs, apb);
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case 16:
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return sysclk / 4;
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default:
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pr_err("unexpected prescaler value (%d)\n", psc);
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log_err("unexpected prescaler value (%d)\n", psc);
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return 0;
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}
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else
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@ -623,7 +625,7 @@ u32 psc = stm32_get_apb_psc(regs, apb);
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case 16:
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return sysclk / psc;
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default:
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pr_err("unexpected prescaler value (%d)\n", psc);
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log_err("unexpected prescaler value (%d)\n", psc);
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return 0;
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}
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};
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@ -665,8 +667,8 @@ static ulong stm32_clk_get_rate(struct clk *clk)
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if (!sysclk)
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return sysclk;
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debug("%s system clock: source = %d freq = %ld\n",
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__func__, source, sysclk);
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dev_dbg(clk->dev, "system clock: source = %d freq = %ld\n",
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source, sysclk);
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d1cfgr = readl(®s->d1cfgr);
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@ -685,8 +687,8 @@ static ulong stm32_clk_get_rate(struct clk *clk)
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gate_offset = clk_map[clk->id].gate_offset;
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debug("%s clk->id=%ld gate_offset=0x%x sysclk=%ld\n",
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__func__, clk->id, gate_offset, sysclk);
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dev_dbg(clk->dev, "clk->id=%ld gate_offset=0x%x sysclk=%ld\n",
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clk->id, gate_offset, sysclk);
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switch (gate_offset) {
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case RCC_AHB3ENR:
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@ -704,8 +706,8 @@ static ulong stm32_clk_get_rate(struct clk *clk)
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sysclk = sysclk / prescaler_table[idx];
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}
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debug("%s system clock: freq after APB3 prescaler = %ld\n",
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__func__, sysclk);
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dev_dbg(clk->dev, "system clock: freq after APB3 prescaler = %ld\n",
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sysclk);
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return sysclk;
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break;
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@ -719,8 +721,9 @@ static ulong stm32_clk_get_rate(struct clk *clk)
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sysclk = sysclk / prescaler_table[idx];
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}
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debug("%s system clock: freq after APB4 prescaler = %ld\n",
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__func__, sysclk);
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dev_dbg(clk->dev,
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"system clock: freq after APB4 prescaler = %ld\n",
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sysclk);
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return sysclk;
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break;
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@ -741,8 +744,9 @@ static ulong stm32_clk_get_rate(struct clk *clk)
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return stm32_get_timer_rate(priv, sysclk, APB1);
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}
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debug("%s system clock: freq after APB1 prescaler = %ld\n",
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__func__, sysclk);
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dev_dbg(clk->dev,
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"system clock: freq after APB1 prescaler = %ld\n",
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sysclk);
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return (sysclk / stm32_get_apb_psc(regs, APB1));
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break;
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@ -758,15 +762,17 @@ static ulong stm32_clk_get_rate(struct clk *clk)
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return stm32_get_timer_rate(priv, sysclk, APB2);
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}
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debug("%s system clock: freq after APB2 prescaler = %ld\n",
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__func__, sysclk);
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dev_dbg(clk->dev,
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"system clock: freq after APB2 prescaler = %ld\n",
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sysclk);
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return (sysclk / stm32_get_apb_psc(regs, APB2));
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break;
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default:
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pr_err("unexpected gate_offset value (0x%x)\n", gate_offset);
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dev_err(clk->dev, "unexpected gate_offset value (0x%x)\n",
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gate_offset);
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return -EINVAL;
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break;
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}
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@ -783,9 +789,9 @@ static int stm32_clk_enable(struct clk *clk)
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gate_offset = clk_map[clk_id].gate_offset;
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gate_bit_index = clk_map[clk_id].gate_bit_idx;
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debug("%s: clkid=%ld gate offset=0x%x bit_index=%d name=%s\n",
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__func__, clk->id, gate_offset, gate_bit_index,
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clk_map[clk_id].name);
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dev_dbg(clk->dev, "clkid=%ld gate offset=0x%x bit_index=%d name=%s\n",
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clk->id, gate_offset, gate_bit_index,
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clk_map[clk_id].name);
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setbits_le32(®s->cr + (gate_offset / 4), BIT(gate_bit_index));
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@ -810,13 +816,13 @@ static int stm32_clk_probe(struct udevice *dev)
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"st,syscfg", &syscon);
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if (err) {
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pr_err("unable to find syscon device\n");
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dev_err(dev, "unable to find syscon device\n");
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return err;
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}
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priv->pwr_regmap = syscon_get_regmap(syscon);
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if (!priv->pwr_regmap) {
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pr_err("unable to find regmap\n");
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dev_err(dev, "unable to find regmap\n");
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return -ENODEV;
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}
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@ -829,7 +835,7 @@ static int stm32_clk_of_xlate(struct clk *clk,
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struct ofnode_phandle_args *args)
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{
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if (args->args_count != 1) {
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debug("Invaild args_count: %d\n", args->args_count);
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dev_dbg(clk->dev, "Invaild args_count: %d\n", args->args_count);
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return -EINVAL;
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}
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@ -852,7 +858,7 @@ static int stm32_clk_of_xlate(struct clk *clk,
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clk->id = 0;
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}
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debug("%s clk->id %ld\n", __func__, clk->id);
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dev_dbg(clk->dev, "clk->id %ld\n", clk->id);
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return 0;
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}
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