From bf37dcc53806f21f1e64912d5dfd00b99cb8d105 Mon Sep 17 00:00:00 2001 From: Hal Feng Date: Tue, 28 Mar 2023 14:35:32 +0800 Subject: [PATCH 01/24] pinctrl: starfive: Fix the crash problem when using gpio cmd starfive_pinctrl_priv struct is a priv of the parent device (pinctrl device), not the gpio device. Signed-off-by: Hal Feng --- drivers/pinctrl/starfive/pinctrl-starfive.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c index 6e69654550..fc72699a2c 100755 --- a/drivers/pinctrl/starfive/pinctrl-starfive.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive.c @@ -278,7 +278,7 @@ const struct pinctrl_ops starfive_pinctrl_ops = { static int starfive_gpio_direction_input(struct udevice *dev, unsigned int off) { struct udevice *pdev = dev->parent; - struct starfive_pinctrl_priv *priv = dev_get_priv(dev); + struct starfive_pinctrl_priv *priv = dev_get_priv(pdev); struct starfive_pinctrl_soc_info *info = priv->info; /* enable input and schmitt trigger */ @@ -297,7 +297,7 @@ static int starfive_gpio_direction_output(struct udevice *dev, unsigned int off, int val) { struct udevice *pdev = dev->parent; - struct starfive_pinctrl_priv *priv = dev_get_priv(dev); + struct starfive_pinctrl_priv *priv = dev_get_priv(pdev); struct starfive_pinctrl_soc_info *info = priv->info; if (info->set_one_pinmux) From e403bfb4a219d037d0b308320331c7625b10caf1 Mon Sep 17 00:00:00 2001 From: Hal Feng Date: Tue, 28 Mar 2023 15:09:02 +0800 Subject: [PATCH 02/24] pinctrl: starfive: Add .get_function ops for the gpio driver Support getting direction of gpio. Signed-off-by: Hal Feng --- drivers/pinctrl/starfive/pinctrl-starfive.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c index fc72699a2c..990d7ac526 100755 --- a/drivers/pinctrl/starfive/pinctrl-starfive.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive.c @@ -275,6 +275,21 @@ const struct pinctrl_ops starfive_pinctrl_ops = { .pinconf_set = starfive_pinconf_set, }; +static int starfive_gpio_get_direction(struct udevice *dev, unsigned int off) +{ + struct udevice *pdev = dev->parent; + struct starfive_pinctrl_priv *priv = dev_get_priv(pdev); + struct starfive_pinctrl_soc_info *info = priv->info; + + unsigned int offset = 4 * (off / 4); + unsigned int shift = 8 * (off % 4); + u32 doen = readl(priv->base + info->doen_reg_base + offset); + + doen = (doen >> shift) & info->doen_mask; + + return doen == GPOEN_ENABLE ? GPIOF_OUTPUT : GPIOF_INPUT; +} + static int starfive_gpio_direction_input(struct udevice *dev, unsigned int off) { struct udevice *pdev = dev->parent; @@ -365,6 +380,7 @@ static int starfive_gpio_probe(struct udevice *dev) } static const struct dm_gpio_ops starfive_gpio_ops = { + .get_function = starfive_gpio_get_direction, .direction_input = starfive_gpio_direction_input, .direction_output = starfive_gpio_direction_output, .get_value = starfive_gpio_get_value, From dc7742fa960a931172e14d21241b1cc87bf1b3a1 Mon Sep 17 00:00:00 2001 From: Hal Feng Date: Tue, 28 Mar 2023 15:09:39 +0800 Subject: [PATCH 03/24] riscv: dts: starfive: Add gpio-controller for the gpio node Add gpio-controller for node gpio and gpioa. Signed-off-by: Hal Feng --- arch/riscv/dts/jh7110.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index cf9a1eebb2..408787334c 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -555,6 +555,7 @@ reg-names = "control"; interrupts = <91>; interrupt-controller; + gpio-controller; #gpio-cells = <2>; ngpios = <64>; status = "okay"; @@ -566,6 +567,7 @@ reg-names = "control"; interrupts = <90>; interrupt-controller; + gpio-controller; #gpio-cells = <2>; ngpios = <4>; status = "okay"; From cb451c3932ba56762dd98b21a42417d1b2c3f8a2 Mon Sep 17 00:00:00 2001 From: Yanhong Wang Date: Thu, 30 Mar 2023 10:19:37 +0800 Subject: [PATCH 04/24] =?UTF-8?q?configs:=20starfive:=E3=80=80Enable=20CON?= =?UTF-8?q?FIG=5FOF=5FSEPARATE=20configuration?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Modify the mode of the DTB for DT Control from Embedded to separated. Signed-off-by: Yanhong Wang --- configs/starfive_evb_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/starfive_evb_defconfig b/configs/starfive_evb_defconfig index f1bc580bb7..cb969592a2 100644 --- a/configs/starfive_evb_defconfig +++ b/configs/starfive_evb_defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_RV64I=y CONFIG_CMODEL_MEDANY=y CONFIG_RISCV_SMODE=y CONFIG_SHOW_REGS=y +# CONFIG_OF_BOARD_FIXUP is not set CONFIG_FIT=y CONFIG_SPL_FIT_SOURCE="jh7110-uboot-fit-image.its" CONFIG_SUPPORT_RAW_INITRD=y @@ -37,6 +38,7 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800 CONFIG_SPL_DM_SPI_FLASH=y @@ -58,7 +60,6 @@ CONFIG_CMD_SYSBOOT=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FS_UUID=y CONFIG_CMD_LOG=y -CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_VERSION_VARIABLE=y From 7f2dda162c9a0017ebea7b359dbd4b73ea196f2d Mon Sep 17 00:00:00 2001 From: "shanlong.li" Date: Tue, 14 Mar 2023 01:07:12 -0700 Subject: [PATCH 05/24] configs: starfive: add nvme boot command add nvme boot command Signed-off-by: shanlong.li --- include/configs/starfive-visionfive2.h | 49 +++++++++++++++++--------- 1 file changed, 32 insertions(+), 17 deletions(-) diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index db8b309ded..fafd1f9de6 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -204,6 +204,11 @@ "run visionfive2_mem_set;" \ "run chipa_gmac_set; \0" \ +#define VISIONFIVE2_BOOTENV_NVME \ + "nvmepart=3\0" \ + "devnvme=0\0" \ + "nvme_env=vf2_nvme_uEnv.txt\0" \ + #define VISIONFIVE2_BOOTENV \ "bootenv=uEnv.txt\0" \ "testenv=vf2_uEnv.txt\0" \ @@ -215,28 +220,37 @@ "ext4bootenv=" \ "ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0"\ "importbootenv=" \ - "echo Importing environment from mmc${devnum} ...; " \ + "echo Importing environment from ${devnum}/${devnvme} ...; "\ "env import -t ${loadaddr} ${filesize}\0" \ "scan_mmc_dev=" \ "if test ${bootmode} = flash; then " \ - "if mmc dev ${devnum}; then " \ - "echo found device ${devnum};" \ - "else " \ - "setenv devnum 0;" \ - "mmc dev 0;" \ + "if pci enum; then " \ + "nvme scan; " \ + "echo pci enum ...;" \ "fi; " \ - "fi; " \ - "echo bootmode ${bootmode} device ${devnum};\0" \ + "if nvme dev; then " \ + "setenv btpart ${devnvme}:${nvmepart};" \ + "setenv load_vf2_env fatload nvme ${btpart} ${loadaddr} ${nvme_env};" \ + "else " \ + "if mmc dev ${devnum}; then " \ + "echo found device ${devnum};" \ + "else " \ + "setenv devnum 0;" \ + "mmc dev 0;" \ + "fi; " \ + "if mmc rescan; then " \ + "run loadbootenv && run importbootenv; "\ + "run ext4bootenv && run importbootenv; "\ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "echo bootmode ${bootmode} device ${devnum}/${devnvme};\0" \ "mmcbootenv=run scan_mmc_dev; " \ - "setenv bootpart ${devnum}:${mmcpart}; " \ - "if mmc rescan; then " \ - "run loadbootenv && run importbootenv; " \ - "run ext4bootenv && run importbootenv; " \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...; " \ - "run uenvcmd; " \ - "fi; " \ - "fi\0" \ + "setenv bootpart ${devnum}:${mmcpart};\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -250,6 +264,7 @@ "pxefile_addr_r=0x45900000\0" \ "ramdisk_addr_r=0x46100000\0" \ VF2_DISTRO_BOOTENV \ + VISIONFIVE2_BOOTENV_NVME \ VISIONFIVE2_BOOTENV \ CHIPA_GMAC_SET \ CHIPA_SET \ From 0c7da4bebe1889ca2b802e0577a1e8cd816a8d4d Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Mon, 3 Apr 2023 11:26:35 +0800 Subject: [PATCH 06/24] board: starfive: jh7110-evb: remove l2 pretcher in borad cfg It should be configured in L2. Signed-off-by: Samin Guo --- board/starfive/evb/starfive_evb.c | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/board/starfive/evb/starfive_evb.c b/board/starfive/evb/starfive_evb.c index dc02aad206..97162aafe2 100644 --- a/board/starfive/evb/starfive_evb.c +++ b/board/starfive/evb/starfive_evb.c @@ -234,32 +234,10 @@ static void get_cpu_voltage_type(struct udevice *dev) } #endif -/*enable U74-mc hart1~hart4 prefetcher*/ -static void enable_prefetcher(void) -{ - u32 hart; - u32 *reg; -#define L2_PREFETCHER_BASE_ADDR 0x2030000 -#define L2_PREFETCHER_OFFSET 0x2000 - - /*hart1~hart4*/ - for (hart = 1; hart < 5; hart++) { - reg = (u32 *)((u64)(L2_PREFETCHER_BASE_ADDR - + hart*L2_PREFETCHER_OFFSET)); - - mb(); /* memory barrier */ - setbits_le32(reg, 0x1); - mb(); /* memory barrier */ - } -} - int board_init(void) { enable_caches(); - /*enable hart1-hart4 prefetcher*/ - enable_prefetcher(); - jh7110_timer_init(); jh7110_usb_init(true); From 97f3b2aaee5e33c75386c1c97a4d61b0fb7d4871 Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Fri, 24 Feb 2023 14:41:34 +0800 Subject: [PATCH 07/24] riscv: jh7110: dram: only read a byte data from eeprom. only read a byte data from eeprom. Signed-off-by: Samin Guo --- arch/riscv/cpu/jh7110/dram.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c index 597d8d689a..20972a04c3 100644 --- a/arch/riscv/cpu/jh7110/dram.c +++ b/arch/riscv/cpu/jh7110/dram.c @@ -14,23 +14,23 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { int ret; - u32 data; + u8 data; u32 len; u32 offset; data = 0; - len = 4; - offset = 88; /*offset of memory size stored in eeprom*/ + len = 1; + offset = 91; /*offset of memory size stored in eeprom*/ ret = fdtdec_setup_mem_size_base(); if (ret) goto err; /*read memory size info*/ - ret = get_data_from_eeprom(offset, len, (u8 *)&data); + ret = get_data_from_eeprom(offset, len, &data); if (ret == len) - gd->ram_size = (phys_size_t)((hextoul((char *)&data, NULL) & 0xff) << 30); - ret = 0; + gd->ram_size = ((phys_size_t)hextoul(&data, NULL)) << 30; + ret = 0; err: return ret; } From 479dc3cb7e4c5c5a2103ff1663971c2a38a163ac Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Fri, 24 Feb 2023 15:08:35 +0800 Subject: [PATCH 08/24] riscv: starfive: jh7110: add check_eeprom_dram_info Make sure that the read DDR information is a valid value Signed-off-by: Samin Guo --- arch/riscv/cpu/jh7110/dram.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c index 20972a04c3..ad8baeba93 100644 --- a/arch/riscv/cpu/jh7110/dram.c +++ b/arch/riscv/cpu/jh7110/dram.c @@ -11,12 +11,26 @@ DECLARE_GLOBAL_DATA_PTR; +static bool check_eeprom_dram_info(phys_size_t size) +{ + switch (size) { + case 0x80000000: + case 0x100000000: + case 0x200000000: + case 0x400000000: + return true; + default: + return false; + } +} + int dram_init(void) { int ret; u8 data; u32 len; u32 offset; + phys_size_t size; data = 0; len = 1; @@ -27,8 +41,11 @@ int dram_init(void) /*read memory size info*/ ret = get_data_from_eeprom(offset, len, &data); - if (ret == len) - gd->ram_size = ((phys_size_t)hextoul(&data, NULL)) << 30; + if (ret == len) { + size = ((phys_size_t)hextoul(&data, NULL)) << 30; + if (check_eeprom_dram_info(size)) + gd->ram_size = size; + } ret = 0; err: From d72ca8695b3d3ac1c201aeedb74b70b138ea9ff4 Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Mon, 3 Apr 2023 11:29:25 +0800 Subject: [PATCH 09/24] board: starfive: jh7110-vf2: remove l2 pretcher in borad cfg It should be configured in L2. Signed-off-by: Samin Guo --- .../visionfive2/starfive_visionfive2.c | 22 ------------------- 1 file changed, 22 deletions(-) diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index e1fe6b2e46..db67c4dc49 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -332,25 +332,6 @@ static void get_cpu_voltage_type(struct udevice *dev) } #endif -/*enable U74-mc hart1~hart4 prefetcher*/ -static void enable_prefetcher(void) -{ - u32 hart; - u32 *reg; -#define L2_PREFETCHER_BASE_ADDR 0x2030000 -#define L2_PREFETCHER_OFFSET 0x2000 - - /*hart1~hart4*/ - for (hart = 1; hart < 5; hart++) { - reg = (u32 *)((u64)(L2_PREFETCHER_BASE_ADDR - + hart*L2_PREFETCHER_OFFSET)); - - mb(); /* memory barrier */ - setbits_le32(reg, 0x1); - mb(); /* memory barrier */ - } -} - static void jh7110_jtag_init(void) { /*jtag*/ @@ -430,9 +411,6 @@ int board_init(void) { enable_caches(); - /*enable hart1-hart4 prefetcher*/ - enable_prefetcher(); - jh7110_jtag_init(); jh7110_timer_init(); From 5755db49a8814116d2c7eaa7a44c2676e7d566c4 Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Mon, 3 Apr 2023 11:33:40 +0800 Subject: [PATCH 10/24] cache: sifive: Configure the l2 prefetcher parameter The default configuration of the SIFIVE L2 Prefetcher may not be the best combination on the JH7110, and some parameters need to be modified to achieve the best performance. Signed-off-by: Samin Guo --- drivers/cache/cache-sifive-ccache.c | 93 +++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/drivers/cache/cache-sifive-ccache.c b/drivers/cache/cache-sifive-ccache.c index 76c0ab26ae..5e6d3a58af 100644 --- a/drivers/cache/cache-sifive-ccache.c +++ b/drivers/cache/cache-sifive-ccache.c @@ -15,10 +15,96 @@ #define SIFIVE_CCACHE_WAY_ENABLE 0x008 + +/* Prefetch */ +#define SIFIVE_PREFET_HARD_BASE(hart) ((hart)*0x2000) +/* Prefetch Control Register */ +#define SIFIVE_PREFT_EN_MASK BIT(0) +#define SIFIVE_PREFT_CROSS_PAGE_DIS_MASK BIT(1) +#define SIFIVE_PREFT_DIST_MASK GENMASK(7, 2) +#define SIFIVE_PREFT_MAX_ALLOC_DIST_MASK GENMASK(13, 8) +#define SIFIVE_PREFT_LIN_TO_EXP_THRD_MASK GENMASK(19, 14) +#define SIFIVE_PREFT_AGE_OUT_EN_MASK BIT(20) +#define SIFIVE_PREFT_NUM_LDS_AGE_OUT_MASK GENMASK(27, 21) +#define SIFIVE_PREFT_CROSS_PAGE_EN_MASK BIT(28) + +/* Prefetch Advanced Control Register */ +#define SIFIVE_PREFT_ADV_Q_FULL_THRD GENMASK(3, 0) +#define SIFIVE_PREFT_ADV_HIT_CACHE_THRD GENMASK(8, 4) +#define SIFIVE_PREFT_ADV_HIT_MSHR_THRD GENMASK(12, 9) +#define SIFIVE_PREFT_ADV_WINDOW_MASK GENMASK(18, 13) + +#define SIFIVE_PREFET_HARD_MASK 0x1e +#define SIFIVE_MAX_HART_ID 0x20 +#define SIFIVE_PREFT_DIST_VAL 0x3 +#define SIFIVE_PREFT_DIST_MAX 0x3f +#define SIFIVE_PREFT_EN 0x1 + struct sifive_ccache { void __iomem *base; + void __iomem *pre_base; + u32 pre_hart_mask; + u32 pre_dist_size; }; +static int sifive_prefetcher_parse(struct udevice *dev) +{ + struct sifive_ccache *priv = dev_get_priv(dev); + + if (!priv->pre_base) + return -EINVAL; + + if (!dev_read_bool(dev, "prefetch-enable")) + return -ENOENT; + + priv->pre_hart_mask = dev_read_u32_default(dev, "prefetch-hart-mask", + SIFIVE_PREFET_HARD_MASK); + priv->pre_dist_size = dev_read_u32_default(dev, "prefetch-dist-size", + SIFIVE_PREFT_DIST_VAL); + return 0; +} + +static void sifive_prefetcher_cfg_by_id(struct udevice *dev, u32 hart) +{ + struct sifive_ccache *priv = dev_get_priv(dev); + void __iomem *reg; + u32 val; + + /* Prefetch Control Register */ + reg = priv->pre_base + SIFIVE_PREFET_HARD_BASE(hart); + + val = readl(reg); + val &= ~SIFIVE_PREFT_MAX_ALLOC_DIST_MASK; + val |= SIFIVE_PREFT_DIST_MAX << __ffs(SIFIVE_PREFT_MAX_ALLOC_DIST_MASK); + writel(val, reg); + + val = readl(reg); + val &= ~SIFIVE_PREFT_DIST_MASK; + val |= priv->pre_dist_size << __ffs(SIFIVE_PREFT_DIST_MASK); + writel(val, reg); + + val |= SIFIVE_PREFT_EN << __ffs(SIFIVE_PREFT_EN_MASK); + writel(val, reg); +} + +static int sifive_prefetcher_enable(struct udevice *dev) +{ + struct sifive_ccache *priv = dev_get_priv(dev); + u32 hart; + int ret; + + ret = sifive_prefetcher_parse(dev); + if (ret) + return ret; + + for (hart = 0; hart < SIFIVE_MAX_HART_ID; hart++) { + if (BIT(hart) & priv->pre_hart_mask) + sifive_prefetcher_cfg_by_id(dev, hart); + } + + return 0; +} + static int sifive_ccache_enable(struct udevice *dev) { struct sifive_ccache *priv = dev_get_priv(dev); @@ -31,6 +117,8 @@ static int sifive_ccache_enable(struct udevice *dev) writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE); + sifive_prefetcher_enable(dev); + return 0; } @@ -51,11 +139,16 @@ static const struct cache_ops sifive_ccache_ops = { static int sifive_ccache_probe(struct udevice *dev) { struct sifive_ccache *priv = dev_get_priv(dev); + fdt_addr_t addr; priv->base = dev_read_addr_ptr(dev); if (!priv->base) return -EINVAL; + addr = dev_read_addr_name(dev, "prefetcher"); + if (addr != FDT_ADDR_T_NONE) + priv->pre_base = (void *)(uintptr_t)addr; + return 0; } From 41cad11dbfc69454edf03ba0dc8fb05196bd74a8 Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Mon, 3 Apr 2023 11:39:32 +0800 Subject: [PATCH 11/24] riscv: dts: jh7110: Add L2 pretcher configuration Add L2 pretcher configuration for starfive jh7110 SoC. Signed-off-by: Samin Guo --- arch/riscv/dts/jh7110-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index 21a14bdc4d..e45b6cde3b 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -71,6 +71,16 @@ }; }; +&cachectrl { + reg = <0x0 0x2010000 0x0 0x4000>, + <0x0 0x2030000 0x0 0x80000>, + <0x0 0x8000000 0x0 0x2000000>; + reg-names = "control", "prefetcher", "sideband"; + prefetch-dist-size = <0x4>; + prefetch-hart-mask = <0x1e>; + prefetch-enable; +}; + &uart0 { clock-frequency = <24000000>; current-speed = <115200>; From c8f3d1842a51e6321e4cf0ac93243873f3e6b522 Mon Sep 17 00:00:00 2001 From: Mason Huo Date: Fri, 7 Apr 2023 09:34:08 +0800 Subject: [PATCH 12/24] board: starfive: jh7110: Modify cpu voltage set commands Update the cpu voltage set commands per binning information from OTP. Signed-off-by: Mason Huo --- board/starfive/evb/starfive_evb.c | 18 ++++++----- .../visionfive2/starfive_visionfive2.c | 17 +++++++---- include/configs/starfive-evb.h | 30 ++++++++++++------- include/configs/starfive-visionfive2.h | 11 +++++-- 4 files changed, 50 insertions(+), 26 deletions(-) diff --git a/board/starfive/evb/starfive_evb.c b/board/starfive/evb/starfive_evb.c index dc02aad206..e2e1e9b8a7 100644 --- a/board/starfive/evb/starfive_evb.c +++ b/board/starfive/evb/starfive_evb.c @@ -27,12 +27,14 @@ enum chip_type_t { }; enum cpu_voltage_type_t { - CPU_VOL_1020 = 0x0e, - CPU_VOL_1040 = 0xff, - CPU_VOL_1060 = 0xf0, - CPU_VOL_1080 = 0xf1, - CPU_VOL_1100 = 0xf2, + CPU_VOL_1020 = 0xef0, + CPU_VOL_1040 = 0xfff, + CPU_VOL_1060 = 0xff0, + CPU_VOL_1080 = 0xfe0, + CPU_VOL_1100 = 0xf80, + CPU_VOL_1120 = 0xf00, }; +#define CPU_VOL_MASK 0xfff #define SYS_CLOCK_ENABLE(clk) \ setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK) @@ -212,8 +214,10 @@ static void get_cpu_voltage_type(struct udevice *dev) if (ret != sizeof(buf)) printf("%s: error reading CPU vol from OTP\n", __func__); else { - buf = 0x0e; - switch ((buf & 0xff)) { + switch ((buf & CPU_VOL_MASK)) { + case CPU_VOL_1120: + env_set("cpu_max_vol", "1120000"); + break; case CPU_VOL_1100: env_set("cpu_max_vol", "1100000"); break; diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index e1fe6b2e46..080077007e 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -53,12 +53,14 @@ enum board_type_t { enum cpu_voltage_type_t { - CPU_VOL_1020 = 0x0e, - CPU_VOL_1040 = 0xff, - CPU_VOL_1060 = 0xf0, - CPU_VOL_1080 = 0xf1, - CPU_VOL_1100 = 0xf2, + CPU_VOL_1020 = 0xef0, + CPU_VOL_1040 = 0xfff, + CPU_VOL_1060 = 0xff0, + CPU_VOL_1080 = 0xfe0, + CPU_VOL_1100 = 0xf80, + CPU_VOL_1120 = 0xf00, }; +#define CPU_VOL_MASK 0xfff static void sys_reset_clear(ulong assert, ulong status, u32 rst) { @@ -311,7 +313,10 @@ static void get_cpu_voltage_type(struct udevice *dev) if (ret != sizeof(buf)) printf("%s: error reading CPU vol from OTP\n", __func__); else { - switch ((buf & 0xff)) { + switch ((buf & CPU_VOL_MASK)) { + case CPU_VOL_1120: + env_set("cpu_max_vol", "1120000"); + break; case CPU_VOL_1100: env_set("cpu_max_vol", "1100000"); break; diff --git a/include/configs/starfive-evb.h b/include/configs/starfive-evb.h index ffe90264f2..82d0e842b9 100644 --- a/include/configs/starfive-evb.h +++ b/include/configs/starfive-evb.h @@ -120,20 +120,27 @@ "cpu_vol_1100_set=" \ "fdt set /opp-table-0/opp-1500000000 opp-microvolt <1100000>;\0" +#define CPU_VOL_1120_SET \ + "cpu_vol_1120_set=" \ + "fdt set /opp-table-0/opp-1500000000 opp-microvolt <1120000>;\0" + #define CPU_VOL_SET \ - "cpu_vol_set=" \ - "if test ${cpu_max_vol} = 1100000; then " \ - "run cpu_vol_1100_set;" \ - "elif test ${cpu_max_vol} = 1080000; then " \ - "run cpu_vol_1080_set;" \ - "elif test ${cpu_max_vol} = 1060000; then " \ - "run cpu_vol_1060_set;" \ - "elif test ${cpu_max_vol} = 1020000; then " \ - "run cpu_vol_1020_set;" \ - "else " \ - "run cpu_vol_1040_set;" \ + "cpu_vol_set=" \ + "if test ${cpu_max_vol} = 1120000; then " \ + "run cpu_vol_1120_set;" \ + "elif test ${cpu_max_vol} = 1100000; then " \ + "run cpu_vol_1100_set;" \ + "elif test ${cpu_max_vol} = 1080000; then " \ + "run cpu_vol_1080_set;" \ + "elif test ${cpu_max_vol} = 1060000; then " \ + "run cpu_vol_1060_set;" \ + "elif test ${cpu_max_vol} = 1020000; then " \ + "run cpu_vol_1020_set;" \ + "else " \ + "run cpu_vol_1040_set;" \ "fi; \0" + #define CHIPA_GMAC_SET \ "chipa_gmac_set=" \ "fdt set /soc/ethernet@16030000/ethernet-phy@0 tx_inverted_10 <0x1>;" \ @@ -174,6 +181,7 @@ CPU_VOL_1060_SET \ CPU_VOL_1080_SET \ CPU_VOL_1100_SET \ + CPU_VOL_1120_SET \ CPU_VOL_SET \ "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index fafd1f9de6..405829faf5 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -118,9 +118,15 @@ "cpu_vol_1100_set=" \ "fdt set /opp-table-0/opp-1500000000 opp-microvolt <1100000>;\0" +#define CPU_VOL_1120_SET \ + "cpu_vol_1120_set=" \ + "fdt set /opp-table-0/opp-1500000000 opp-microvolt <1120000>;\0" + #define CPU_VOL_SET \ - "cpu_vol_set=" \ - "if test ${cpu_max_vol} = 1100000; then " \ + "cpu_vol_set=" \ + "if test ${cpu_max_vol} = 1120000; then " \ + "run cpu_vol_1120_set;" \ + "elif test ${cpu_max_vol} = 1100000; then " \ "run cpu_vol_1100_set;" \ "elif test ${cpu_max_vol} = 1080000; then " \ "run cpu_vol_1080_set;" \ @@ -273,6 +279,7 @@ CPU_VOL_1060_SET \ CPU_VOL_1080_SET \ CPU_VOL_1100_SET \ + CPU_VOL_1120_SET \ CPU_VOL_SET \ CHIPA_SET_FORCE \ VISIONFIVE2_MEM_SET \ From fcbb415e06b7fa8c8f525e4b07eb050daf8eb292 Mon Sep 17 00:00:00 2001 From: Mason Huo Date: Fri, 7 Apr 2023 09:34:08 +0800 Subject: [PATCH 13/24] board: starfive: jh7110: Modify cpu voltage set commands Update the cpu voltage set commands per binning information from OTP. Signed-off-by: Mason Huo --- board/starfive/evb/starfive_evb.c | 18 +++++++++++------- include/configs/starfive-evb.h | 30 +++++++++++++++++++----------- 2 files changed, 30 insertions(+), 18 deletions(-) diff --git a/board/starfive/evb/starfive_evb.c b/board/starfive/evb/starfive_evb.c index dc02aad206..e2e1e9b8a7 100644 --- a/board/starfive/evb/starfive_evb.c +++ b/board/starfive/evb/starfive_evb.c @@ -27,12 +27,14 @@ enum chip_type_t { }; enum cpu_voltage_type_t { - CPU_VOL_1020 = 0x0e, - CPU_VOL_1040 = 0xff, - CPU_VOL_1060 = 0xf0, - CPU_VOL_1080 = 0xf1, - CPU_VOL_1100 = 0xf2, + CPU_VOL_1020 = 0xef0, + CPU_VOL_1040 = 0xfff, + CPU_VOL_1060 = 0xff0, + CPU_VOL_1080 = 0xfe0, + CPU_VOL_1100 = 0xf80, + CPU_VOL_1120 = 0xf00, }; +#define CPU_VOL_MASK 0xfff #define SYS_CLOCK_ENABLE(clk) \ setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK) @@ -212,8 +214,10 @@ static void get_cpu_voltage_type(struct udevice *dev) if (ret != sizeof(buf)) printf("%s: error reading CPU vol from OTP\n", __func__); else { - buf = 0x0e; - switch ((buf & 0xff)) { + switch ((buf & CPU_VOL_MASK)) { + case CPU_VOL_1120: + env_set("cpu_max_vol", "1120000"); + break; case CPU_VOL_1100: env_set("cpu_max_vol", "1100000"); break; diff --git a/include/configs/starfive-evb.h b/include/configs/starfive-evb.h index ffe90264f2..82d0e842b9 100644 --- a/include/configs/starfive-evb.h +++ b/include/configs/starfive-evb.h @@ -120,20 +120,27 @@ "cpu_vol_1100_set=" \ "fdt set /opp-table-0/opp-1500000000 opp-microvolt <1100000>;\0" +#define CPU_VOL_1120_SET \ + "cpu_vol_1120_set=" \ + "fdt set /opp-table-0/opp-1500000000 opp-microvolt <1120000>;\0" + #define CPU_VOL_SET \ - "cpu_vol_set=" \ - "if test ${cpu_max_vol} = 1100000; then " \ - "run cpu_vol_1100_set;" \ - "elif test ${cpu_max_vol} = 1080000; then " \ - "run cpu_vol_1080_set;" \ - "elif test ${cpu_max_vol} = 1060000; then " \ - "run cpu_vol_1060_set;" \ - "elif test ${cpu_max_vol} = 1020000; then " \ - "run cpu_vol_1020_set;" \ - "else " \ - "run cpu_vol_1040_set;" \ + "cpu_vol_set=" \ + "if test ${cpu_max_vol} = 1120000; then " \ + "run cpu_vol_1120_set;" \ + "elif test ${cpu_max_vol} = 1100000; then " \ + "run cpu_vol_1100_set;" \ + "elif test ${cpu_max_vol} = 1080000; then " \ + "run cpu_vol_1080_set;" \ + "elif test ${cpu_max_vol} = 1060000; then " \ + "run cpu_vol_1060_set;" \ + "elif test ${cpu_max_vol} = 1020000; then " \ + "run cpu_vol_1020_set;" \ + "else " \ + "run cpu_vol_1040_set;" \ "fi; \0" + #define CHIPA_GMAC_SET \ "chipa_gmac_set=" \ "fdt set /soc/ethernet@16030000/ethernet-phy@0 tx_inverted_10 <0x1>;" \ @@ -174,6 +181,7 @@ CPU_VOL_1060_SET \ CPU_VOL_1080_SET \ CPU_VOL_1100_SET \ + CPU_VOL_1120_SET \ CPU_VOL_SET \ "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ From 5fa2c5f3d64a4fea10bc1b90f3329985ff6c1d10 Mon Sep 17 00:00:00 2001 From: Minda Chen Date: Mon, 10 Apr 2023 16:20:37 +0800 Subject: [PATCH 14/24] dts: pmu: remove pmu dts stall cycles config. class 8 and class9 cpu stall cycles hwcounter is not supported in U74. delete the configuration. Signed-off-by: Minda Chen --- arch/riscv/dts/jh7110.dtsi | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 408787334c..c675e85e19 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -165,12 +165,9 @@ pmu { compatible = "riscv,pmu"; - riscv,event-to-mhpmcounters = <0x5 0x06 0x18 - 0x08 0x09 0x18>; + riscv,event-to-mhpmcounters = <0x5 0x06 0x18>; riscv,event-to-mhpmevent = <0x05 0x00000000 0x4000 - 0x06 0x00000000 0x4001 - 0x08 0x00000000 0x4008 - 0x09 0x00000000 0x4009>; + 0x06 0x00000000 0x4001>; riscv,raw-event-to-mhpmcounters = <0x00000000 0x100 0xffffffff 0xffffffff 0x18 0x00000000 0x200 0xffffffff 0xffffffff 0x18 From b6aaea9aadcf447fe3845b82f9668d8acd9434e5 Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Mon, 17 Apr 2023 19:35:45 +0800 Subject: [PATCH 15/24] net: phy: motorcomm: add Pad Drive Strength Cfg YT8531 supports Pad Drive Strength configuration. Including rx_data/rx_clk, etc. Signed-off-by: Samin Guo --- drivers/net/phy/motorcomm.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 20e2055117..94142a5a5a 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -40,6 +40,7 @@ #define YTPHY_SPEED_MODE 0xc000 #define YTPHY_SPEED_MODE_BIT 14 #define YTPHY_RGMII_SW_DR_MASK GENMASK(5, 4) +#define YTPHY_RGMII_RXC_DR_MASK GENMASK(15, 13) #define YT8521_EXT_CLK_GATE 0xc #define YT8521_EN_SLEEP_SW_BIT 15 @@ -73,6 +74,12 @@ struct ytphy_reg_field { const u8 dflt; /* Default value */ }; +static const struct ytphy_reg_field ytphy_dr_grp[] = { + { "rgmii_sw_dr", 2, 4, 0x3}, + { "rgmii_sw_dr_2", 1, 12, 0x0}, + { "rgmii_sw_dr_rxc", 3, 13, 0x3} +}; + static const struct ytphy_reg_field ytphy_rxtxd_grp[] = { { "rx_delay_sel", 4, 10, 0x0 }, { "tx_delay_sel_fe", 4, 4, 0xf }, @@ -228,9 +235,20 @@ static int ytphy_of_config(struct phy_device *phydev) ytphy_write_ext(phydev, YTPHY_EXTREG_CHIP_CONFIG, val); } - /* set drive strenght of rxd/rx_ctl rgmii pad */ val = ytphy_read_ext(phydev, YTPHY_PAD_DRIVES_STRENGTH_CFG); - val |= YTPHY_RGMII_SW_DR_MASK; + for (i = 0; i < ARRAY_SIZE(ytphy_dr_grp); i++) { + + cfg = ofnode_read_u32_default(node, + ytphy_dr_grp[i].name, ~0); + cfg = (cfg != -1) ? cfg : ytphy_dr_grp[i].dflt; + + /*check the cfg overflow or not*/ + cfg = (cfg > ((1 << ytphy_dr_grp[i].size) - 1)) ? + ((1 << ytphy_dr_grp[i].size) - 1) : cfg; + + val = bitfield_replace(val, ytphy_dr_grp[i].off, + ytphy_dr_grp[i].size, cfg); + } ytphy_write_ext(phydev, YTPHY_PAD_DRIVES_STRENGTH_CFG, val); val = ytphy_read_ext(phydev, YTPHY_EXTREG_RGMII_CONFIG1); From fe8426ebb03dc13a06758d2c4c0571e19b3c064a Mon Sep 17 00:00:00 2001 From: Yanhong Wang Date: Sun, 23 Apr 2023 11:19:47 +0800 Subject: [PATCH 16/24] board: starfive: copyright: Standardize the copyright format Unify the content format of the copyright section Signed-off-by: Yanhong Wang --- arch/riscv/cpu/jh7110/pll.c | 2 +- arch/riscv/cpu/jh7110/spl.c | 2 +- arch/riscv/include/asm/arch-jh7110/clk.h | 2 +- arch/riscv/include/asm/arch-jh7110/gpio.h | 2 +- arch/riscv/include/asm/arch-jh7110/jh7110-regs.h | 2 +- arch/riscv/include/asm/arch-jh7110/spl.h | 2 +- board/starfive/evb/Makefile | 2 +- board/starfive/evb/spl.c | 2 +- board/starfive/evb/starfive_evb.c | 2 +- board/starfive/visionfive/Makefile | 2 +- board/starfive/visionfive/spl.c | 2 +- board/starfive/visionfive/starfive_visionfive.c | 2 +- drivers/clk/starfive/clk-jh7110.c | 2 +- drivers/gpio/starfive-gpio.c | 2 +- drivers/misc/starfive-otp.c | 2 +- drivers/pinctrl/starfive/pinctrl-starfive.c | 2 +- drivers/pinctrl/starfive/pinctrl-starfive.h | 2 +- drivers/ram/starfive/ddrcsr_boot.c | 2 +- drivers/ram/starfive/ddrphy_start.c | 3 +-- drivers/ram/starfive/ddrphy_train.c | 2 +- drivers/ram/starfive/ddrphy_utils.c | 2 +- drivers/ram/starfive/starfive_ddr.c | 2 +- drivers/ram/starfive/starfive_ddr.h | 2 +- drivers/reset/reset-jh7110.c | 2 +- drivers/usb/cdns3/cdns3-starfive.c | 2 +- include/configs/starfive-visionfive.h | 2 +- include/dt-bindings/clock/starfive-jh7110-clkgen.h | 3 ++- include/dt-bindings/clock/starfive-jh7110-isp.h | 3 ++- include/dt-bindings/reset/starfive-jh7110.h | 2 +- 29 files changed, 31 insertions(+), 30 deletions(-) diff --git a/arch/riscv/cpu/jh7110/pll.c b/arch/riscv/cpu/jh7110/pll.c index 563259476a..030e9ca2cd 100644 --- a/arch/riscv/cpu/jh7110/pll.c +++ b/arch/riscv/cpu/jh7110/pll.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * samin */ diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c index 414938bce4..2a49fbee10 100644 --- a/arch/riscv/cpu/jh7110/spl.c +++ b/arch/riscv/cpu/jh7110/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/arch/riscv/include/asm/arch-jh7110/clk.h b/arch/riscv/include/asm/arch-jh7110/clk.h index b64269d2bd..f0003b0157 100644 --- a/arch/riscv/include/asm/arch-jh7110/clk.h +++ b/arch/riscv/include/asm/arch-jh7110/clk.h @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h b/arch/riscv/include/asm/arch-jh7110/gpio.h index d83f6d2d9f..60e887c289 100644 --- a/arch/riscv/include/asm/arch-jh7110/gpio.h +++ b/arch/riscv/include/asm/arch-jh7110/gpio.h @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h index ad04e8877c..156709e6ae 100644 --- a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h +++ b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/arch/riscv/include/asm/arch-jh7110/spl.h b/arch/riscv/include/asm/arch-jh7110/spl.h index 0756020809..3d665fe0a0 100644 --- a/arch/riscv/include/asm/arch-jh7110/spl.h +++ b/arch/riscv/include/asm/arch-jh7110/spl.h @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/board/starfive/evb/Makefile b/board/starfive/evb/Makefile index fc8867306f..e9d9ad7276 100644 --- a/board/starfive/evb/Makefile +++ b/board/starfive/evb/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2021 Shanghai StarFive Technology Co., Ltd. +# Copyright (C) 2022-2023 StarFive Technology Co., Ltd. # obj-y := starfive_evb.o diff --git a/board/starfive/evb/spl.c b/board/starfive/evb/spl.c index 8d07122719..8616a61479 100644 --- a/board/starfive/evb/spl.c +++ b/board/starfive/evb/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/board/starfive/evb/starfive_evb.c b/board/starfive/evb/starfive_evb.c index 62f7129431..915ed1d4f9 100644 --- a/board/starfive/evb/starfive_evb.c +++ b/board/starfive/evb/starfive_evb.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/board/starfive/visionfive/Makefile b/board/starfive/visionfive/Makefile index 739370cb2a..841d5d9b2d 100644 --- a/board/starfive/visionfive/Makefile +++ b/board/starfive/visionfive/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2021 Shanghai StarFive Technology Co., Ltd. +# Copyright (C) 2022-2023 StarFive Technology Co., Ltd. # obj-y := starfive_visionfive.o diff --git a/board/starfive/visionfive/spl.c b/board/starfive/visionfive/spl.c index d74ecb9690..13e934de4b 100644 --- a/board/starfive/visionfive/spl.c +++ b/board/starfive/visionfive/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/board/starfive/visionfive/starfive_visionfive.c b/board/starfive/visionfive/starfive_visionfive.c index e1b0042f10..462781a526 100755 --- a/board/starfive/visionfive/starfive_visionfive.c +++ b/board/starfive/visionfive/starfive_visionfive.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index 61e46c35f5..249eb130f1 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/drivers/gpio/starfive-gpio.c b/drivers/gpio/starfive-gpio.c index 9c715c1f9c..ccdbb116c1 100644 --- a/drivers/gpio/starfive-gpio.c +++ b/drivers/gpio/starfive-gpio.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/drivers/misc/starfive-otp.c b/drivers/misc/starfive-otp.c index 8ff189c35d..9ae65fefa0 100644 --- a/drivers/misc/starfive-otp.c +++ b/drivers/misc/starfive-otp.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c index 990d7ac526..389018f28e 100755 --- a/drivers/pinctrl/starfive/pinctrl-starfive.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive.c @@ -2,7 +2,7 @@ /* * Pinctrl / GPIO driver for StarFive JH7100 SoC * - * Copyright (C) 2022 Shanghai StarFive Technology Co., Ltd. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: Lee Kuan Lim * Author: Jianlong Huang */ diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.h b/drivers/pinctrl/starfive/pinctrl-starfive.h index 02b87ca996..7d2828f653 100755 --- a/drivers/pinctrl/starfive/pinctrl-starfive.h +++ b/drivers/pinctrl/starfive/pinctrl-starfive.h @@ -2,7 +2,7 @@ /* * Pinctrl / GPIO driver for StarFive SoC * - * Copyright (C) 2022 Shanghai StarFive Technology Co., Ltd. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: Lee Kuan Lim * Author: Jianlong Huang */ diff --git a/drivers/ram/starfive/ddrcsr_boot.c b/drivers/ram/starfive/ddrcsr_boot.c index eff862a175..048b838b3d 100644 --- a/drivers/ram/starfive/ddrcsr_boot.c +++ b/drivers/ram/starfive/ddrcsr_boot.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/drivers/ram/starfive/ddrphy_start.c b/drivers/ram/starfive/ddrphy_start.c index edfd43bb42..58165e427c 100644 --- a/drivers/ram/starfive/ddrphy_start.c +++ b/drivers/ram/starfive/ddrphy_start.c @@ -1,7 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/drivers/ram/starfive/ddrphy_train.c b/drivers/ram/starfive/ddrphy_train.c index d5888c9413..6383a42126 100644 --- a/drivers/ram/starfive/ddrphy_train.c +++ b/drivers/ram/starfive/ddrphy_train.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/drivers/ram/starfive/ddrphy_utils.c b/drivers/ram/starfive/ddrphy_utils.c index ed7667b536..f21e911cd9 100644 --- a/drivers/ram/starfive/ddrphy_utils.c +++ b/drivers/ram/starfive/ddrphy_utils.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/drivers/ram/starfive/starfive_ddr.c b/drivers/ram/starfive/starfive_ddr.c index 862a834a0c..5773d57927 100644 --- a/drivers/ram/starfive/starfive_ddr.c +++ b/drivers/ram/starfive/starfive_ddr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/drivers/ram/starfive/starfive_ddr.h b/drivers/ram/starfive/starfive_ddr.h index 4877489079..d63e7e4c83 100644 --- a/drivers/ram/starfive/starfive_ddr.h +++ b/drivers/ram/starfive/starfive_ddr.h @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong * */ diff --git a/drivers/reset/reset-jh7110.c b/drivers/reset/reset-jh7110.c index 8a08dcf378..43be04e24f 100644 --- a/drivers/reset/reset-jh7110.c +++ b/drivers/reset/reset-jh7110.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: samin * yanhong * diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c index eb184394cd..d51bf30b67 100644 --- a/drivers/usb/cdns3/cdns3-starfive.c +++ b/drivers/usb/cdns3/cdns3-starfive.c @@ -2,7 +2,7 @@ /** * cdns-starfive.c - Cadence USB Controller * - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: yanhong */ diff --git a/include/configs/starfive-visionfive.h b/include/configs/starfive-visionfive.h index b732cc3122..956c6a7d12 100644 --- a/include/configs/starfive-visionfive.h +++ b/include/configs/starfive-visionfive.h @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2021 Shanghai StarFive Technology Co., Ltd. + * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. * YanHong Wang */ diff --git a/include/dt-bindings/clock/starfive-jh7110-clkgen.h b/include/dt-bindings/clock/starfive-jh7110-clkgen.h index c2df56f222..6e9afe9c3b 100644 --- a/include/dt-bindings/clock/starfive-jh7110-clkgen.h +++ b/include/dt-bindings/clock/starfive-jh7110-clkgen.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* - * Copyright 2022 StarFive, Inc + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. + * Author: XingYu Wu */ #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CLKGEN_H__ diff --git a/include/dt-bindings/clock/starfive-jh7110-isp.h b/include/dt-bindings/clock/starfive-jh7110-isp.h index b4f28731ed..b6a8a6e3b4 100644 --- a/include/dt-bindings/clock/starfive-jh7110-isp.h +++ b/include/dt-bindings/clock/starfive-jh7110-isp.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* - * Copyright 2022 StarFive, Inc + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. + * Author: XingYu Wu */ #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_ISP_H__ diff --git a/include/dt-bindings/reset/starfive-jh7110.h b/include/dt-bindings/reset/starfive-jh7110.h index 5a4d973584..58b22e9165 100644 --- a/include/dt-bindings/reset/starfive-jh7110.h +++ b/include/dt-bindings/reset/starfive-jh7110.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* - * Copyright (C) 2022 Starfive, Inc. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: samin * yanhong */ From 798fa99abc9ce732938253d759d05b8fd039ff85 Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Thu, 20 Apr 2023 09:18:07 +0800 Subject: [PATCH 17/24] riscv: dts: starfive: vf2: add Pad Drive Strength Cfg Increase the drive strength of rx_clk to increase the delay available window. Signed-off-by: Samin Guo --- arch/riscv/dts/starfive_visionfive2.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/dts/starfive_visionfive2.dts b/arch/riscv/dts/starfive_visionfive2.dts index fb00079b8c..a5fe92a2b5 100644 --- a/arch/riscv/dts/starfive_visionfive2.dts +++ b/arch/riscv/dts/starfive_visionfive2.dts @@ -314,6 +314,9 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@0 { + rgmii_sw_dr_2 = <0x0>; + rgmii_sw_dr = <0x3>; + rgmii_sw_dr_rxc = <0x6>; rxc_dly_en = <1>; tx_delay_sel_fe = <5>; tx_delay_sel = <0xa>; @@ -328,6 +331,9 @@ #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { + rgmii_sw_dr_2 = <0x0>; + rgmii_sw_dr = <0x3>; + rgmii_sw_dr_rxc = <0x6>; tx_delay_sel_fe = <5>; tx_delay_sel = <0>; rxc_dly_en = <0>; From 63cac2a17fcb8748b9b0e31bc212bf15253cfd8f Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Thu, 20 Apr 2023 09:18:50 +0800 Subject: [PATCH 18/24] riscv: dts: starfive: vf2: set gmac0 rx delay to 1500ps set gmac0 rx delay to 1500ps to to match better delays. Signed-off-by: Samin Guo --- arch/riscv/dts/starfive_visionfive2.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/dts/starfive_visionfive2.dts b/arch/riscv/dts/starfive_visionfive2.dts index a5fe92a2b5..5293cdbae6 100644 --- a/arch/riscv/dts/starfive_visionfive2.dts +++ b/arch/riscv/dts/starfive_visionfive2.dts @@ -317,7 +317,8 @@ rgmii_sw_dr_2 = <0x0>; rgmii_sw_dr = <0x3>; rgmii_sw_dr_rxc = <0x6>; - rxc_dly_en = <1>; + rxc_dly_en = <0>; + rx_delay_sel = <0xa>; tx_delay_sel_fe = <5>; tx_delay_sel = <0xa>; tx_inverted_10 = <0x1>; From c3df27a0d1d7cb7cfd4b19117fcb5dc224231a47 Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Thu, 20 Apr 2023 11:25:57 +0800 Subject: [PATCH 19/24] riscv: dts: starfive: vf2: set gmac1 rx delay to 300ps set gmac1 rx delay to 300ps to to match better delays. Signed-off-by: Samin Guo --- arch/riscv/dts/starfive_visionfive2.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/dts/starfive_visionfive2.dts b/arch/riscv/dts/starfive_visionfive2.dts index 5293cdbae6..d0268fbfeb 100644 --- a/arch/riscv/dts/starfive_visionfive2.dts +++ b/arch/riscv/dts/starfive_visionfive2.dts @@ -338,6 +338,7 @@ tx_delay_sel_fe = <5>; tx_delay_sel = <0>; rxc_dly_en = <0>; + rx_delay_sel = <0x2>; tx_inverted_10 = <0x1>; tx_inverted_100 = <0x1>; tx_inverted_1000 = <0x0>; From 2a040b7720825629103c5b1efc5ace023072db8d Mon Sep 17 00:00:00 2001 From: Clement Date: Tue, 2 May 2023 05:14:48 -0400 Subject: [PATCH 20/24] Added booting from nvme support for debian Signed-off-by: Clement --- configs/starfive_visionfive2_defconfig | 2 +- include/configs/starfive-visionfive2.h | 36 ++++++++++++++++++++------ 2 files changed, 29 insertions(+), 9 deletions(-) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 462be41022..51167de0af 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -28,7 +28,7 @@ CONFIG_SPI_BOOT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=tty1 console=ttyS0,115200 debug rootwait earlycon=sbi" CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run load_vf2_env;run importbootenv;run boot2; run load_distro_uenv;run distro_bootcmd" +CONFIG_BOOTCOMMAND="run load_vf2_env;run importbootenv;run boot2; run scan_boot_dev; run load_distro_uenv;run distro_bootcmd" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="run chipa_set_uboot;run mmcbootenv" CONFIG_DEFAULT_FDT_FILE="starfive/starfive_visionfive2.dtb" diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index 405829faf5..1ec6f9045d 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -141,32 +141,52 @@ #define VF2_DISTRO_BOOTENV \ "fatbootpart=1:3\0" \ "distroloadaddr=0xb0000000\0" \ - "load_distro_uenv=" \ - "fatload mmc ${devnum}:3 ${distroloadaddr} /${bootenv}; " \ + "bootdev=mmc\0" \ + "scan_boot_dev=" \ + "if test ${bootmode} = flash; then " \ + "if pci enum; then " \ + "nvme scan; " \ + "echo pci enum ...;" \ + "fi; " \ + "if nvme dev; then " \ + "setenv fatbootpart ${devnvme}:${nvmepart};" \ + "setenv devnum ${devnvme};" \ + "setenv bootdev nvme;" \ + "else " \ + "if mmc dev ${devnum}; then " \ + "echo found device ${devnum};" \ + "else " \ + "setenv devnum 0;" \ + "mmc dev 0;" \ + "fi; " \ + "fi; " \ + "fi; \0" \ + "load_distro_uenv=" \ + "fatload ${bootdev} ${devnum}:3 ${distroloadaddr} /${bootenv}; " \ "setenv fatbootpart ${devnum}:3; " \ "env import ${distroloadaddr} 200; \0" \ "fdt_loaddtb=" \ - "fatload mmc ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile}; fdt addr ${fdt_addr_r}; \0" \ + "fatload ${bootdev} ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile}; fdt addr ${fdt_addr_r}; \0" \ "fdt_sizecheck=" \ - "fatsize mmc ${fatbootpart} /dtbs/${fdtfile}; \0" \ + "fatsize ${bootdev} ${fatbootpart} /dtbs/${fdtfile}; \0" \ "set_fdt_distro=" \ "if test ${chip_vision} = A; then " \ "if test ${memory_size} = 200000000; then " \ "run chipa_gmac_set;" \ "run visionfive2_mem_set;" \ - "fatwrite mmc ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile} ${filesize};" \ + "fatwrite ${bootdev} ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile} ${filesize};" \ "else " \ "run chipa_gmac_set;" \ "run visionfive2_mem_set;" \ - "fatwrite mmc ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile} ${filesize};" \ + "fatwrite ${bootdev} ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile} ${filesize};" \ "fi;" \ "else " \ "run visionfive2_mem_set;" \ "run cpu_vol_set;" \ - "fatwrite mmc ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile} ${filesize};" \ + "fatwrite ${bootdev} ${fatbootpart} ${fdt_addr_r} /dtbs/${fdtfile} ${filesize};" \ "fi; \0" \ "bootcmd_distro=" \ - "run fdt_loaddtb; run fdt_sizecheck; run set_fdt_distro; sysboot mmc ${fatbootpart} fat c0000000 /${boot_syslinux_conf}; \0" \ + "run fdt_loaddtb; run fdt_sizecheck; run set_fdt_distro; sysboot ${bootdev} ${fatbootpart} fat c0000000 /${boot_syslinux_conf}; \0" \ #define PARTS_DEFAULT \ "name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \ From c82a615162564ace2078e71702f7f7ce8c578873 Mon Sep 17 00:00:00 2001 From: "shanlong.li" Date: Thu, 4 May 2023 23:19:00 -0700 Subject: [PATCH 21/24] uboot: evb support boot from nvme ssd support boot from nvme ssd Signed-off-by: shanlong.li --- configs/starfive_evb_defconfig | 2 +- include/configs/starfive-evb.h | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/configs/starfive_evb_defconfig b/configs/starfive_evb_defconfig index cb969592a2..0d6a48187c 100644 --- a/configs/starfive_evb_defconfig +++ b/configs/starfive_evb_defconfig @@ -28,7 +28,7 @@ CONFIG_SPI_BOOT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=tty1 console=ttyS0,115200 debug rootwait earlycon=sbi " CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="fatload mmc 0:3 $kernel_addr_r jh7110_uEnv.txt; env import -t $kernel_addr_r $filesize;run boot2" +CONFIG_BOOTCOMMAND="run mmcbootenv;run boot2" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="run chipa_set_uboot" CONFIG_LOG_MAX_LEVEL=4 diff --git a/include/configs/starfive-evb.h b/include/configs/starfive-evb.h index 82d0e842b9..5f856026d4 100644 --- a/include/configs/starfive-evb.h +++ b/include/configs/starfive-evb.h @@ -140,6 +140,21 @@ "run cpu_vol_1040_set;" \ "fi; \0" +#define EVB_BOOTENV_NVME \ + "sdev_cmd=mmc\0" \ + "sdev_blk=mmcblk0p4\0" \ + "scan_nvme_dev=" \ + "if pci enum; then " \ + "nvme scan; " \ + "echo pci enum ...;" \ + "fi; " \ + "if nvme dev; then " \ + "setenv sdev_cmd nvme;" \ + "setenv sdev_blk nvme0n1p4;" \ + "fi; \0" \ + "mmcbootenv=run scan_nvme_dev; " \ + "fatload ${sdev_cmd} 0:3 $kernel_addr_r jh7110_uEnv.txt; " \ + "env import -t $kernel_addr_r $filesize; \0" #define CHIPA_GMAC_SET \ "chipa_gmac_set=" \ @@ -176,6 +191,7 @@ "ramdisk_addr_r=0x46100000\0" \ CHIPA_GMAC_SET \ CHIPA_SET \ + EVB_BOOTENV_NVME \ CPU_VOL_1020_SET \ CPU_VOL_1040_SET \ CPU_VOL_1060_SET \ From fffd811e3d69b7cdd6118ddeb7ab8354f6ea2bfa Mon Sep 17 00:00:00 2001 From: Andy Hu Date: Wed, 8 Mar 2023 17:32:09 +0800 Subject: [PATCH 22/24] riscv: dts: starfive: add zicsr_zifencei to riscv,isa string Starting from gcc 12.x, csr and fence instructions have been separated from the base I instruction set. special the zicsr_zifencei string to DT riscv,isa string Signed-off-by: Andy Hu --- arch/riscv/dts/jh7110.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index c675e85e19..d02d49797d 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -20,7 +20,7 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "sifive,u74-mc", "riscv"; + compatible = "sifive,s7", "riscv"; reg = <0>; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -35,7 +35,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imacu"; + riscv,isa = "rv64imacu_zba_zbb"; tlb-split; status = "disabled"; @@ -62,7 +62,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdcbsux"; + riscv,isa = "rv64imafdcbsux_zba_zbb"; tlb-split; status = "okay"; @@ -89,7 +89,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdcbsux"; + riscv,isa = "rv64imafdcbsux_zba_zbb"; tlb-split; status = "okay"; @@ -116,7 +116,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdcbsux"; + riscv,isa = "rv64imafdcbsux_zba_zbb"; tlb-split; status = "okay"; @@ -143,7 +143,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdcbsux"; + riscv,isa = "rv64imafdcbsux_zba_zbb"; tlb-split; status = "okay"; From ec4da28612d8efe0aae9b924206291dfccd8af9f Mon Sep 17 00:00:00 2001 From: MichaIng Date: Fri, 31 Mar 2023 18:08:03 +0200 Subject: [PATCH 23/24] VisionFive 2: Add default compressed kernel address The default U-Boot environment does not provide kernel_comp_addr_r and kernel_comp_size, needed when using a compressed kernel image. These variables are listed as mandatory in upstream U-Boot to allow this feature without needed user configuration: https://github.com/u-boot/u-boot/blob/master/doc/develop/distro.rst#required-environment-variables The values are taken from the uEnv.txt shipped by StarFive's own Debian images, which does use a gzip-compressed kernel image hence proven to be valid. Adding those values to the U-Boot default environment allows them to be removed from the dedicated uEnv.txt and enables support for compressed kernel images independent of the used uEnv.txt or whether one is used at all. Signed-off-by: MichaIng --- include/configs/starfive-visionfive2.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index 1ec6f9045d..b87c4974df 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -283,6 +283,8 @@ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr_r=0x40200000\0" \ + "kernel_comp_addr_r=0x90000000\0" \ + "kernel_comp_size=0x10000000\0" \ "fdt_addr_r=0x46000000\0" \ "scriptaddr=0x43900000\0" \ "script_offset_f=0x1fff000\0" \ From b6e2b0e85c774a18ae668223a6e5f7d335895243 Mon Sep 17 00:00:00 2001 From: MichaIng Date: Fri, 31 Mar 2023 18:01:18 +0200 Subject: [PATCH 24/24] VisionFive 2: Add default device tree overlay address This is needed for device tree overlays to work when adding them via "fdtoverlays /path/to/overlay.dtbo" to extlinux.conf. Of course this can be also set in uEnv.txt, but this U-Boot build reads that environment file from partition 3 with FAT filesystem only, which makes this an unnecessary limitation. Also, this variable is listed as mandatory in upstream U-Boot docs: https://github.com/u-boot/u-boot/blob/master/doc/develop/distro.rst#required-environment-variables To allow using device tree overlays on the VisionFive 2, including the one shipped with StarFive's own kernel build, via extlinux in a generic and upstream-compatible way, this variable is hereby added. The used address is sufficiently distant from the initramfs address, also in case 0x48100000 is used (override via uEnv.txt in StarFive's Debian image). Signed-off-by: MichaIng --- include/configs/starfive-visionfive2.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index b87c4974df..7f4bc7741d 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -291,6 +291,7 @@ "script_size_f=0x1000\0" \ "pxefile_addr_r=0x45900000\0" \ "ramdisk_addr_r=0x46100000\0" \ + "fdtoverlay_addr_r=0x4f000000\0" \ VF2_DISTRO_BOOTENV \ VISIONFIVE2_BOOTENV_NVME \ VISIONFIVE2_BOOTENV \