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pcm051: Enable DDR PHY dynamic power down bit
This is done already for am335x in
59dcf970d1
and also applies for pcm051.
It powers down the IO receiver when not performing read which helps
reducing the overall power consuption in low power states
(suspend/standby).
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
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parent
76b09b8561
commit
cecac32a06
1 changed files with 2 additions and 1 deletions
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@ -104,7 +104,8 @@ static struct emif_regs ddr3_emif_reg_data = {
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.sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
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.sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
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.zq_config = MT41J256M8HX15E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY,
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.emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
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PHY_EN_DYN_PWRDN,
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};
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#endif
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