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riscv: dts: move out AE350 L2 node from cpus node
When L2 node exists inside cpus node, uclass_get_device can not parse L2 node successfully. So move it outside from cpus node. Also add tag-ram-ctl and data-ram-ctl attributes for v5l2 cache controller driver. This can adjust timing by requirement from dtb to improve performance. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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2 changed files with 22 additions and 12 deletions
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@ -62,13 +62,18 @@
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compatible = "riscv,cpu-intc";
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};
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};
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};
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L2: l2-cache@e0500000 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x40000>;
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reg = <0x0 0xe0500000 0x0 0x40000>;
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};
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L2: l2-cache@e0500000 {
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compatible = "v5l2cache";
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cache-level = <2>;
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cache-size = <0x40000>;
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reg = <0xe0500000 0x40000>;
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andes,inst-prefetch = <3>;
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andes,data-prefetch = <3>;
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/* The value format is <XRAMOCTL XRAMICTL> */
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andes,tag-ram-ctl = <0 0>;
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andes,data-ram-ctl = <0 0>;
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};
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memory@0 {
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@ -62,13 +62,18 @@
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compatible = "riscv,cpu-intc";
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};
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};
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};
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L2: l2-cache@e0500000 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x40000>;
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reg = <0x0 0xe0500000 0x0 0x40000>;
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};
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L2: l2-cache@e0500000 {
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compatible = "v5l2cache";
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cache-level = <2>;
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cache-size = <0x40000>;
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reg = <0x0 0xe0500000 0x0 0x40000>;
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andes,inst-prefetch = <3>;
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andes,data-prefetch = <3>;
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/* The value format is <XRAMOCTL XRAMICTL> */
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andes,tag-ram-ctl = <0 0>;
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andes,data-ram-ctl = <0 0>;
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};
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memory@0 {
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