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riscv: dts: move out AE350 L2 node from cpus node

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When L2 node exists inside cpus node, uclass_get_device
can not parse L2 node successfully. So move it outside
from cpus node.

Also add tag-ram-ctl and data-ram-ctl attributes for
v5l2 cache controller driver. This can adjust timing
by requirement from dtb to improve performance.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Rick Chen 2019-08-28 18:46:10 +08:00 • committed by Andes
parent 7045ed9f1a
commit cf6ee112d8
2 changed files with 22 additions and 12 deletions
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17
arch/riscv/dts/ae350_32.dts
View file

@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
};
L2: l2-cache@e0500000 {
compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
reg = <0x0 0xe0500000 0x0 0x40000>;
};
L2: l2-cache@e0500000 {
compatible = "v5l2cache";
cache-level = <2>;
cache-size = <0x40000>;
reg = <0xe0500000 0x40000>;
andes,inst-prefetch = <3>;
andes,data-prefetch = <3>;
/* The value format is <XRAMOCTL XRAMICTL> */
andes,tag-ram-ctl = <0 0>;
andes,data-ram-ctl = <0 0>;
};
memory@0 {

17
arch/riscv/dts/ae350_64.dts
View file

@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
};
L2: l2-cache@e0500000 {
compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
reg = <0x0 0xe0500000 0x0 0x40000>;
};
L2: l2-cache@e0500000 {
compatible = "v5l2cache";
cache-level = <2>;
cache-size = <0x40000>;
reg = <0x0 0xe0500000 0x0 0x40000>;
andes,inst-prefetch = <3>;
andes,data-prefetch = <3>;
/* The value format is <XRAMOCTL XRAMICTL> */
andes,tag-ram-ctl = <0 0>;
andes,data-ram-ctl = <0 0>;
};
memory@0 {