From 97b262758b7c99a644155254bee9f716573b10ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Julien=20B=C3=A9raud?= Date: Mon, 7 Jan 2019 09:17:46 +0000 Subject: [PATCH 1/4] gpio: altera_pio: fix get_value gpio_get_value should return 0 or 1, not the value of bit & (1 << pin) Acked-by: Marek Vasut Signed-off-by: Julien Beraud --- drivers/gpio/altera_pio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/altera_pio.c b/drivers/gpio/altera_pio.c index 59e30979f0..324f9c29a8 100644 --- a/drivers/gpio/altera_pio.c +++ b/drivers/gpio/altera_pio.c @@ -56,7 +56,7 @@ static int altera_pio_get_value(struct udevice *dev, unsigned pin) struct altera_pio_platdata *plat = dev_get_platdata(dev); struct altera_pio_regs *const regs = plat->regs; - return readl(®s->data) & (1 << pin); + return !!(readl(®s->data) & (1 << pin)); } From b275c9aba6d1628211287f80297048128acec964 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 13 Feb 2019 21:50:25 +0100 Subject: [PATCH 2/4] ARM: cache: Fix incorrect bitwise operation The loop implemented in the code is supposed to check whether the PL310 operation register has any bit from the mask set. Currently, the code checks whether the PL310 operation register has any bit set AND whether the mask is non-zero, which is incorrect. Fix the conditional. Signed-off-by: Marek Vasut Cc: Dalon Westergreen Cc: Dinh Nguyen Cc: Tom Rini Fixes: 93bc21930a1b ("armv7: add PL310 support to u-boot") --- arch/arm/lib/cache-pl310.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c index 1296ba6efd..bbaaaa4157 100644 --- a/arch/arm/lib/cache-pl310.c +++ b/arch/arm/lib/cache-pl310.c @@ -33,7 +33,7 @@ static void pl310_background_op_all_ways(u32 *op_reg) /* Invalidate all ways */ writel(way_mask, op_reg); /* Wait for all ways to be invalidated */ - while (readl(op_reg) && way_mask) + while (readl(op_reg) & way_mask) ; pl310_cache_sync(); } From 2c0b300bc30881c09519d1f7bfa46a04b0d6d1d5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 19 Feb 2019 01:11:24 +0100 Subject: [PATCH 3/4] ARM: socfpga: Configure PL310 latencies Configure the PL310 tag and data latency registers, which slightly improves performance and aligns the behavior with Linux. Signed-off-by: Marek Vasut Cc: Dalon Westergreen Cc: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index e1adea143c..fcf211d62b 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -62,6 +62,9 @@ void v7_outer_cache_enable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + writel(0x111, &pl310->pl310_tag_latency_ctrl); + writel(0x121, &pl310->pl310_data_latency_ctrl); + /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | From 4a9743f73c10a4b3801be3b662a892f61617256e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 19 Feb 2019 01:07:21 +0100 Subject: [PATCH 4/4] ARM: socfpga: Clear PL310 early in SPL On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux will result in stale data in PL310 L2 cache controller. Even if the L2 cache controller is disabled via the CTRL register CTRL_EN bit, those data can interfere with operation of devices using DMA, like e.g. the DWMMC controller. This can in turn cause e.g. SPL to fail reading data from SD/MMC. The obvious solution here would be to fully reset the L2 cache controller via the reset manager MPUMODRST L2 bit, however this causes bus hang even if executed entirely from L1 I-cache to avoid generating any bus traffic through the L2 cache controller. This patch thus configures and enables the L2 cache controller very early in the SPL boot process, clears the L2 cache and disables the L2 cache controller again. The reason for doing it in SPL is because we need to avoid accessing any of the potentially stale data in the L2 cache, and we are certain any of the stale data will be below the OCRAM address range. To further reduce bus traffic during the L2 cache invalidation, we enable L1 I-cache and run the invalidation code entirely out of the L1 I-cache. Signed-off-by: Marek Vasut Cc: Dalon Westergreen Cc: Dinh Nguyen --- arch/arm/mach-socfpga/spl_gen5.c | 58 ++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 4c9f7997be..142b60f887 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -23,6 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; @@ -63,6 +66,60 @@ u32 spl_boot_mode(const u32 boot_device) } #endif +static void socfpga_pl310_clear(void) +{ + u32 mask = 0xff, ena = 0; + + icache_enable(); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + + writel(0x111, &pl310->pl310_tag_latency_ctrl); + writel(0x121, &pl310->pl310_data_latency_ctrl); + + /* enable BRESP, instruction and data prefetch, full line of zeroes */ + setbits_le32(&pl310->pl310_aux_ctrl, + L310_AUX_CTRL_DATA_PREFETCH_MASK | + L310_AUX_CTRL_INST_PREFETCH_MASK | + L310_SHARED_ATT_OVERRIDE_ENABLE); + + /* Enable the L2 cache */ + ena = readl(&pl310->pl310_ctrl); + ena |= L2X0_CTRL_EN; + + /* + * Invalidate the PL310 L2 cache. Keep the invalidation code + * entirely in L1 I-cache to avoid any bus traffic through + * the L2. + */ + asm volatile( + ".align 5 \n" + " b 3f \n" + "1: str %1, [%4] \n" + " dsb \n" + " isb \n" + " str %0, [%2] \n" + " dsb \n" + " isb \n" + "2: ldr %0, [%2] \n" + " cmp %0, #0 \n" + " bne 2b \n" + " str %0, [%3] \n" + " dsb \n" + " isb \n" + " b 4f \n" + "3: b 1b \n" + "4: nop \n" + : "+r"(mask), "+r"(ena) + : "r"(&pl310->pl310_inv_way), + "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) + : "memory", "cc"); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); @@ -85,6 +142,7 @@ void board_init_f(ulong dummy) memset(__bss_start, 0, __bss_end - __bss_start); socfpga_sdram_remap_zero(); + socfpga_pl310_clear(); debug("Freezing all I/O banks\n"); /* freeze all IO banks */