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PXA: Separate PXA2xx CPU init

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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
This commit is contained in:
Marek Vasut 2011-11-26 07:32:24 +01:00 • committed by Albert ARIBAUD
parent abc20aba18
commit d10237d275
2 changed files with 32 additions and 74 deletions
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5
arch/arm/cpu/pxa/Makefile
View file

@ -27,7 +27,10 @@ LIB = $(obj)lib$(CPU).o
START = start.o START = start.o
COBJS += cpu.o COBJS-$(CONFIG_CPU_PXA25X) = pxa2xx.o
COBJS-$(CONFIG_CPU_PXA27X) = pxa2xx.o
COBJS = $(COBJS-y)
COBJS += pxafb.o COBJS += pxafb.o
COBJS += timer.o COBJS += timer.o
COBJS += usb.o COBJS += usb.o

101
arch/arm/cpu/pxa/cpu.c → arch/arm/cpu/pxa/pxa2xx.c
View file

@ -26,85 +26,49 @@
* MA 02111-1307 USA * MA 02111-1307 USA
*/ */
/*
* CPU specific code
*/
#include <asm/io.h> #include <asm/io.h>
#include <asm/system.h> #include <asm/system.h>
#include <command.h> #include <command.h>
#include <common.h> #include <common.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
static void cache_flush(void); /* Flush I/D-cache */
static void cache_flush(void)
int cleanup_before_linux (void)
{
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* just disable everything that can disturb booting linux
*/
disable_interrupts ();
/* turn off I-cache */
icache_disable();
dcache_disable();
/* flush I-cache */
cache_flush();
return (0);
}
/* flush I/D-cache */
static void cache_flush (void)
{ {
unsigned long i = 0; unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
} }
#ifndef CONFIG_CPU_MONAHANS int cleanup_before_linux(void)
void set_GPIO_mode(int gpio_mode)
{ {
int gpio = gpio_mode & GPIO_MD_MASK_NR; /*
int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; * This function is called just before we call Linux. It prepares
int val; * the processor for Linux by just disabling everything that can
* disturb booting Linux.
*/
/* This below changes direction setting of GPIO "gpio" */ disable_interrupts();
val = readl(GPDR(gpio)); icache_disable();
dcache_disable();
cache_flush();
if (gpio_mode & GPIO_MD_MASK_DIR) return 0;
val |= GPIO_bit(gpio);
else
val &= ~GPIO_bit(gpio);
writel(val, GPDR(gpio));
/* This below updates only AF of GPIO "gpio" */
val = readl(GAFR(gpio));
val &= ~(0x3 << (((gpio) & 0xf) * 2));
val |= fn << (((gpio) & 0xf) * 2);
writel(val, GAFR(gpio));
} }
#endif /* CONFIG_CPU_MONAHANS */
void pxa_wait_ticks(int ticks) void pxa_wait_ticks(int ticks)
{ {
writel(0, OSCR); writel(0, OSCR);
while (readl(OSCR) < ticks) while (readl(OSCR) < ticks)
asm volatile("":::"memory"); asm volatile("" : : : "memory");
} }
inline void writelrb(uint32_t val, uint32_t addr) inline void writelrb(uint32_t val, uint32_t addr)
{ {
writel(val, addr); writel(val, addr);
asm volatile("":::"memory"); asm volatile("" : : : "memory");
readl(addr); readl(addr);
asm volatile("":::"memory"); asm volatile("" : : : "memory");
} }
void pxa_dram_init(void) void pxa_dram_init(void)
@ -201,7 +165,7 @@ void pxa_dram_init(void)
*/ */
for (i = 9; i >= 0; i--) { for (i = 9; i >= 0; i--) {
writel(i, 0xa0000000); writel(i, 0xa0000000);
asm volatile("":::"memory"); asm volatile("" : : : "memory");
} }
/* /*
* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
@ -234,21 +198,21 @@ void pxa_gpio_setup(void)
writel(CONFIG_SYS_GPSR0_VAL, GPSR0); writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
writel(CONFIG_SYS_GPSR1_VAL, GPSR1); writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
writel(CONFIG_SYS_GPSR2_VAL, GPSR2); writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPSR3_VAL, GPSR3); writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
#endif #endif
writel(CONFIG_SYS_GPCR0_VAL, GPCR0); writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
writel(CONFIG_SYS_GPCR1_VAL, GPCR1); writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
writel(CONFIG_SYS_GPCR2_VAL, GPCR2); writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPCR3_VAL, GPCR3); writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
#endif #endif
writel(CONFIG_SYS_GPDR0_VAL, GPDR0); writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
writel(CONFIG_SYS_GPDR1_VAL, GPDR1); writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
writel(CONFIG_SYS_GPDR2_VAL, GPDR2); writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPDR3_VAL, GPDR3); writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
#endif #endif
@ -258,7 +222,7 @@ void pxa_gpio_setup(void)
writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U); writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L); writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U); writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L); writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U); writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
#endif #endif
@ -270,7 +234,7 @@ void pxa_interrupt_setup(void)
{ {
writel(0, ICLR); writel(0, ICLR);
writel(0, ICMR); writel(0, ICMR);
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #if defined(CONFIG_CPU_PXA27X)
writel(0, ICLR2); writel(0, ICLR2);
writel(0, ICMR2); writel(0, ICMR2);
#endif #endif
@ -278,18 +242,14 @@ void pxa_interrupt_setup(void)
void pxa_clock_setup(void) void pxa_clock_setup(void)
{ {
#ifndef CONFIG_CPU_MONAHANS
writel(CONFIG_SYS_CKEN, CKEN); writel(CONFIG_SYS_CKEN, CKEN);
writel(CONFIG_SYS_CCCR, CCCR); writel(CONFIG_SYS_CCCR, CCCR);
asm volatile("mcr p14, 0, %0, c6, c0, 0"::"r"(2)); asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(2));
#else
/* Set CKENA/CKENB/ACCR for MH */
#endif
/* enable the 32Khz oscillator for RTC and PowerManager */ /* enable the 32Khz oscillator for RTC and PowerManager */
writel(OSCC_OON, OSCC); writel(OSCC_OON, OSCC);
while(!(readl(OSCC) & OSCC_OOK)) while (!(readl(OSCC) & OSCC_OOK))
asm volatile("":::"memory"); asm volatile("" : : : "memory");
} }
void pxa_wakeup(void) void pxa_wakeup(void)
@ -305,14 +265,13 @@ void pxa_wakeup(void)
pxa_dram_init(); pxa_dram_init();
icache_disable(); icache_disable();
dcache_disable(); dcache_disable();
asm volatile("mov pc, %0"::"r"(readl(PSPR))); asm volatile("mov pc, %0" : : "r"(readl(PSPR)));
} }
} }
int arch_cpu_init(void) int arch_cpu_init(void)
{ {
pxa_gpio_setup(); pxa_gpio_setup();
/* pxa_wait_ticks(0x8000); */
pxa_wakeup(); pxa_wakeup();
pxa_interrupt_setup(); pxa_interrupt_setup();
pxa_clock_setup(); pxa_clock_setup();
@ -321,12 +280,8 @@ int arch_cpu_init(void)
void i2c_clk_enable(void) void i2c_clk_enable(void)
{ {
/* set the global I2C clock on */ /* Set the global I2C clock on */
#ifdef CONFIG_CPU_MONAHANS
writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
#else
writel(readl(CKEN) | CKEN14_I2C, CKEN); writel(readl(CKEN) | CKEN14_I2C, CKEN);
#endif
} }
void reset_cpu(ulong ignored) __attribute__((noreturn)); void reset_cpu(ulong ignored) __attribute__((noreturn));