mirror of
https://github.com/Fishwaldo/u-boot.git
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SPI: added support for MX51 to mxc_spi
This patch add SPI support for the MX51 processor. Signed-off-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Stefano Babic
parent
e98ecd7110
commit
d205ddcfc5
1 changed files with 211 additions and 20 deletions
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@ -31,7 +31,7 @@
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#error "i.MX27 CSPI not supported due to drastic differences in register definisions" \
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"See linux mxc_spi driver from Freescale for details."
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#else
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#elif defined(CONFIG_MX31)
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#include <asm/arch/mx31.h>
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@ -56,6 +56,9 @@
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPICTRL_TC (1 << 8)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPICTRL_MAXBITS 0x1f
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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@ -65,12 +68,63 @@ static unsigned long spi_bases[] = {
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0x53f84000,
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};
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#define OUT MX31_GPIO_DIRECTION_OUT
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#define mxc_gpio_direction mx31_gpio_direction
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#define mxc_gpio_set mx31_gpio_set
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#elif defined(CONFIG_MX51)
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#define MXC_CSPIRXDATA 0x00
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#define MXC_CSPITXDATA 0x04
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#define MXC_CSPICTRL 0x08
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#define MXC_CSPICON 0x0C
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#define MXC_CSPIINT 0x10
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#define MXC_CSPIDMA 0x14
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#define MXC_CSPISTAT 0x18
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#define MXC_CSPIPERIOD 0x1C
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#define MXC_CSPIRESET 0x00
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
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#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
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#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPICTRL_TC (1 << 7)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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/* Bit position inside CTRL register to be associated with SS */
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#define MXC_CSPICTRL_CHAN 18
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/* Bit position inside CON register to be associated with SS */
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#define MXC_CSPICON_POL 4
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#define MXC_CSPICON_PHA 0
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#define MXC_CSPICON_SSPOL 12
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static unsigned long spi_bases[] = {
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CSPI1_BASE_ADDR,
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CSPI2_BASE_ADDR,
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CSPI3_BASE_ADDR,
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};
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#define mxc_gpio_direction(gpio, dir) (0)
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#define mxc_gpio_set(gpio, value) {}
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#define OUT 1
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#else
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#error "Unsupported architecture"
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#endif
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struct mxc_spi_slave {
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struct spi_slave slave;
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unsigned long base;
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u32 ctrl_reg;
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#if defined(CONFIG_MX51)
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u32 cfg_reg;
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#endif
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int gpio;
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};
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@ -89,34 +143,161 @@ static inline void reg_write(unsigned long addr, u32 val)
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*(volatile unsigned long*)addr = val;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
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if (mxcs->gpio > 0)
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mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
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if (mxcs->gpio > 0)
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mxc_gpio_set(mxcs->gpio,
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!(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
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}
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#ifdef CONFIG_MX51
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static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
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s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
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u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
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if (max_hz == 0) {
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printf("Error: desired clock is 0\n");
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return -1;
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}
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reg_ctrl = reg_read(mxcs->base + MXC_CSPICTRL);
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/* Reset spi */
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reg_write(mxcs->base + MXC_CSPICTRL, 0);
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reg_write(mxcs->base + MXC_CSPICTRL, (reg_ctrl | 0x1));
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/*
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* The following computation is taken directly from Freescale's code.
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*/
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if (clk_src > max_hz) {
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pre_div = clk_src / max_hz;
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if (pre_div > 16) {
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post_div = pre_div / 16;
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pre_div = 15;
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}
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if (post_div != 0) {
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for (i = 0; i < 16; i++) {
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if ((1 << i) >= post_div)
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break;
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}
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if (i == 16) {
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printf("Error: no divider for the freq: %d\n",
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max_hz);
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return -1;
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}
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post_div = i;
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}
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}
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debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
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reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
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MXC_CSPICTRL_SELCHAN(cs);
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reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
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MXC_CSPICTRL_PREDIV(pre_div);
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reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
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MXC_CSPICTRL_POSTDIV(post_div);
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/* always set to master mode */
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reg_ctrl |= 1 << (cs + 4);
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/* We need to disable SPI before changing registers */
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reg_ctrl &= ~MXC_CSPICTRL_EN;
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if (mode & SPI_CS_HIGH)
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ss_pol = 1;
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if (!(mode & SPI_CPOL))
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sclkpol = 1;
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if (mode & SPI_CPHA)
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sclkpha = 1;
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reg_config = reg_read(mxcs->base + MXC_CSPICON);
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/*
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* Configuration register setup
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* The MX51 has support different setup for each SS
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*/
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reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
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(ss_pol << (cs + MXC_CSPICON_SSPOL));
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reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
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(sclkpol << (cs + MXC_CSPICON_POL));
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reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
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(sclkpha << (cs + MXC_CSPICON_PHA));
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debug("reg_ctrl = 0x%x\n", reg_ctrl);
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reg_write(mxcs->base + MXC_CSPICTRL, reg_ctrl);
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debug("reg_config = 0x%x\n", reg_config);
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reg_write(mxcs->base + MXC_CSPICON, reg_config);
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/* save config register and control register */
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mxcs->ctrl_reg = reg_ctrl;
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mxcs->cfg_reg = reg_config;
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/* clear interrupt reg */
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reg_write(mxcs->base + MXC_CSPIINT, 0);
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reg_write(mxcs->base + MXC_CSPISTAT,
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MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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return 0;
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}
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#endif
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static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen,
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unsigned long flags)
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{
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struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
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unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
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mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(slave);
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mxcs->ctrl_reg = (mxcs->ctrl_reg &
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~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
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MXC_CSPICTRL_BITCOUNT(bitlen - 1);
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if (cfg_reg != mxcs->ctrl_reg)
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reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
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reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
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#ifdef CONFIG_MX51
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reg_write(mxcs->base + MXC_CSPICON, mxcs->cfg_reg);
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#endif
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if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN))
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mx31_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
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/* Clear interrupt register */
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reg_write(mxcs->base + MXC_CSPISTAT,
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MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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debug("Sending SPI 0x%x\n", data);
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reg_write(mxcs->base + MXC_CSPITXDATA, data);
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reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_XCH);
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/* FIFO is written, now starts the transfer setting the XCH bit */
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reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg |
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MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
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while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
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/* Wait until the TC (Transfer completed) bit is set */
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while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0)
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;
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if (mxcs->gpio > 0 && (flags & SPI_XFER_END)) {
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mx31_gpio_set(mxcs->gpio,
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!(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
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}
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/* Transfer completed, clear any pending request */
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reg_write(mxcs->base + MXC_CSPISTAT,
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MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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data = reg_read(mxcs->base + MXC_CSPIRXDATA);
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debug("SPI Rx: 0x%x\n", data);
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(slave);
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return data;
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return reg_read(mxcs->base + MXC_CSPIRXDATA);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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@ -176,7 +357,7 @@ static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
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if (cs > 3) {
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mxcs->gpio = cs >> 8;
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cs &= 3;
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ret = mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT);
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ret = mxc_gpio_direction(mxcs->gpio, OUT);
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if (ret) {
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printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
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return -EINVAL;
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@ -210,6 +391,20 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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cs = ret;
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mxcs->slave.bus = bus;
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mxcs->slave.cs = cs;
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mxcs->base = spi_bases[bus];
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#ifdef CONFIG_MX51
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/* Can be used for i.MX31 too ? */
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ctrl_reg = 0;
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ret = spi_cfg(mxcs, cs, max_hz, mode);
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if (ret) {
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printf("mxc_spi: cannot setup SPI controller\n");
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free(mxcs);
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return NULL;
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}
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#else
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ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
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MXC_CSPICTRL_BITCOUNT(31) |
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MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
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@ -222,12 +417,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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ctrl_reg |= MXC_CSPICTRL_POL;
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if (mode & SPI_CS_HIGH)
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ctrl_reg |= MXC_CSPICTRL_SSPOL;
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mxcs->slave.bus = bus;
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mxcs->slave.cs = cs;
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mxcs->base = spi_bases[bus];
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mxcs->ctrl_reg = ctrl_reg;
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#endif
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return &mxcs->slave;
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}
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