mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-16 12:11:32 +00:00
Merge branch 'u-boot/master'
Conflicts: drivers/net/Makefile (trivial merge)
This commit is contained in:
commit
d2a3e91139
443 changed files with 9779 additions and 38614 deletions
4
CREDITS
4
CREDITS
|
@ -120,10 +120,6 @@ N: Dan A. Dickey
|
|||
E: ddickey@charter.net
|
||||
D: FADS Support
|
||||
|
||||
N: James F. Dougherty
|
||||
E: jfd@GigabitNetworks.COM
|
||||
D: Port to the MOUSSE board
|
||||
|
||||
N: Mike Dunn
|
||||
E: mikedunn@newsguy.com
|
||||
D: Palmtreo680 board, docg4 nand flash driver
|
||||
|
|
44
MAKEALL
44
MAKEALL
|
@ -418,50 +418,8 @@ LIST_arm="$(targets_by_arch arm | \
|
|||
## MIPS Systems (default = big endian)
|
||||
#########################################################################
|
||||
|
||||
LIST_mips4kc=" \
|
||||
incaip \
|
||||
incaip_100MHz \
|
||||
incaip_133MHz \
|
||||
incaip_150MHz \
|
||||
qemu_mips \
|
||||
vct_platinum \
|
||||
vct_platinum_small \
|
||||
vct_platinum_onenand \
|
||||
vct_platinum_onenand_small \
|
||||
vct_platinumavc \
|
||||
vct_platinumavc_small \
|
||||
vct_platinumavc_onenand \
|
||||
vct_platinumavc_onenand_small \
|
||||
vct_premium \
|
||||
vct_premium_small \
|
||||
vct_premium_onenand \
|
||||
vct_premium_onenand_small \
|
||||
"
|
||||
LIST_mips="$(targets_by_arch mips)"
|
||||
|
||||
LIST_au1xx0=" \
|
||||
dbau1000 \
|
||||
dbau1100 \
|
||||
dbau1500 \
|
||||
dbau1550 \
|
||||
"
|
||||
|
||||
LIST_mips=" \
|
||||
${LIST_mips4kc} \
|
||||
${LIST_mips5kc} \
|
||||
${LIST_au1xx0} \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## MIPS Systems (little endian)
|
||||
#########################################################################
|
||||
|
||||
LIST_au1xx0_el=" \
|
||||
dbau1550_el \
|
||||
pb1000 \
|
||||
"
|
||||
LIST_mips_el=" \
|
||||
${LIST_au1xx0_el} \
|
||||
"
|
||||
#########################################################################
|
||||
## OpenRISC Systems
|
||||
#########################################################################
|
||||
|
|
73
Makefile
73
Makefile
|
@ -127,7 +127,7 @@ saved-output := $(KBUILD_OUTPUT)
|
|||
KBUILD_OUTPUT := $(shell mkdir -p $(KBUILD_OUTPUT) && cd $(KBUILD_OUTPUT) \
|
||||
&& /bin/pwd)
|
||||
$(if $(KBUILD_OUTPUT),, \
|
||||
$(error output directory "$(saved-output)" does not exist))
|
||||
$(error failed to create output directory "$(saved-output)"))
|
||||
|
||||
PHONY += $(MAKECMDGOALS) sub-make
|
||||
|
||||
|
@ -205,7 +205,14 @@ CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
|
|||
else echo sh; fi ; fi)
|
||||
|
||||
HOSTCC = gcc
|
||||
HOSTCXX = g++
|
||||
HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
|
||||
HOSTCXXFLAGS = -O2
|
||||
|
||||
ifeq ($(shell $(HOSTCC) -v 2>&1 | grep -c "clang version"), 1)
|
||||
HOSTCFLAGS += -Wno-unused-value -Wno-unused-parameter \
|
||||
-Wno-missing-field-initializers -fno-delete-null-pointer-checks
|
||||
endif
|
||||
|
||||
ifeq ($(HOSTOS),cygwin)
|
||||
HOSTCFLAGS += -ansi
|
||||
|
@ -301,12 +308,26 @@ endif
|
|||
# If the user is running make -s (silent mode), suppress echoing of
|
||||
# commands
|
||||
|
||||
ifneq ($(filter 4.%,$(MAKE_VERSION)),) # make-4
|
||||
ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),)
|
||||
quiet=silent_
|
||||
endif
|
||||
else # make-3.8x
|
||||
ifneq ($(filter s% -s%,$(MAKEFLAGS)),)
|
||||
quiet=silent_
|
||||
endif
|
||||
endif
|
||||
|
||||
export quiet Q KBUILD_VERBOSE
|
||||
|
||||
ifneq ($(CC),)
|
||||
ifeq ($(shell $(CC) -v 2>&1 | grep -c "clang version"), 1)
|
||||
COMPILER := clang
|
||||
else
|
||||
COMPILER := gcc
|
||||
endif
|
||||
export COMPILER
|
||||
endif
|
||||
|
||||
# Look for make include files relative to root of kernel src
|
||||
MAKEFLAGS += --include-dir=$(srctree)
|
||||
|
@ -368,8 +389,9 @@ export MODVERDIR := $(if $(KBUILD_EXTMOD),$(firstword $(KBUILD_EXTMOD))/).tmp_ve
|
|||
|
||||
# Files to ignore in find ... statements
|
||||
|
||||
RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o -name CVS \
|
||||
-o -name .pc -o -name .hg -o -name .git \) -prune -o
|
||||
export RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o \
|
||||
-name CVS -o -name .pc -o -name .hg -o -name .git \) \
|
||||
-prune -o
|
||||
export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \
|
||||
--exclude CVS --exclude .pc --exclude .hg --exclude .git
|
||||
|
||||
|
@ -523,6 +545,20 @@ endif
|
|||
|
||||
KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
|
||||
|
||||
ifeq ($(COMPILER),clang)
|
||||
KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
|
||||
KBUILD_CPPFLAGS += $(call cc-option,-Wno-unknown-warning-option,)
|
||||
KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable)
|
||||
KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
|
||||
KBUILD_CFLAGS += $(call cc-disable-warning, gnu)
|
||||
# Quiet clang warning: comparison of unsigned expression < 0 is always false
|
||||
KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare)
|
||||
# CLANG uses a _MergedGlobals as optimization, but this breaks modpost, as the
|
||||
# source of a reference will be _MergedGlobals and not on of the whitelisted names.
|
||||
# See modpost pattern 2
|
||||
KBUILD_CFLAGS += $(call cc-option, -mno-global-merge,)
|
||||
endif
|
||||
|
||||
KBUILD_CFLAGS += -g
|
||||
# $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
|
||||
# option to the assembler.
|
||||
|
@ -548,6 +584,11 @@ endif
|
|||
|
||||
export CONFIG_SYS_TEXT_BASE
|
||||
|
||||
# Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments
|
||||
KBUILD_CPPFLAGS += $(KCPPFLAGS)
|
||||
KBUILD_AFLAGS += $(KAFLAGS)
|
||||
KBUILD_CFLAGS += $(KCFLAGS)
|
||||
|
||||
# Use UBOOTINCLUDE when you must reference the include/ directory.
|
||||
# Needed to be compatible with the O= option
|
||||
UBOOTINCLUDE := \
|
||||
|
@ -699,7 +740,11 @@ ALL-y += u-boot.srec u-boot.bin System.map
|
|||
|
||||
ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin
|
||||
ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
|
||||
ifeq ($(CONFIG_SPL_FSL_PBL),y)
|
||||
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
|
||||
else
|
||||
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
|
||||
endif
|
||||
ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
|
||||
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
|
||||
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
|
||||
|
@ -894,6 +939,21 @@ endif
|
|||
u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE
|
||||
$(call if_changed,cat)
|
||||
|
||||
#Add a target to create boot binary having SPL binary in PBI format
|
||||
#concatenated with u-boot binary. It is need by PowerPC SoC having
|
||||
#internal SRAM <= 512KB.
|
||||
MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
|
||||
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
|
||||
|
||||
spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
|
||||
$(call if_changed,mkimage)
|
||||
|
||||
OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
|
||||
--gap-fill=0xff
|
||||
|
||||
u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl u-boot.bin FORCE
|
||||
$(call if_changed,pad_cat)
|
||||
|
||||
# PPC4xx needs the SPL at the end of the image, since the reset vector
|
||||
# is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target
|
||||
# and need to introduce a new build target with the full blown U-Boot
|
||||
|
@ -1178,7 +1238,8 @@ CLOBBER_DIRS += $(patsubst %,spl/%, $(filter-out Makefile, \
|
|||
CLOBBER_FILES += u-boot* MLO* SPL System.map nand_spl/u-boot*
|
||||
|
||||
# Directories & files removed with 'make mrproper'
|
||||
MRPROPER_DIRS += include/config include/generated
|
||||
MRPROPER_DIRS += include/config include/generated \
|
||||
.tmp_objdiff
|
||||
MRPROPER_FILES += .config .config.old \
|
||||
tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
|
||||
include/config.h include/config.mk
|
||||
|
@ -1244,8 +1305,8 @@ distclean: mrproper
|
|||
@find $(srctree) $(RCS_FIND_IGNORE) \
|
||||
\( -name '*.orig' -o -name '*.rej' -o -name '*~' \
|
||||
-o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \
|
||||
-o -name '.*.rej' -o -name '*.pyc' \
|
||||
-o -name '*%' -o -name '.*.cmd' -o -name 'core' \) \
|
||||
-o -name '.*.rej' -o -name '*%' -o -name 'core' \
|
||||
-o -name '*.pyc' \) \
|
||||
-type f -print | xargs rm -f
|
||||
|
||||
backup:
|
||||
|
|
51
README
51
README
|
@ -132,6 +132,10 @@ Directory Hierarchy:
|
|||
====================
|
||||
|
||||
/arch Architecture specific files
|
||||
/arc Files generic to ARC architecture
|
||||
/cpu CPU specific files
|
||||
/arc700 Files specific to ARC 700 CPUs
|
||||
/lib Architecture specific library files
|
||||
/arm Files generic to ARM architecture
|
||||
/cpu CPU specific files
|
||||
/arm720t Files specific to ARM 720 CPUs
|
||||
|
@ -164,7 +168,7 @@ Directory Hierarchy:
|
|||
/mips Files generic to MIPS architecture
|
||||
/cpu CPU specific files
|
||||
/mips32 Files specific to MIPS32 CPUs
|
||||
/xburst Files specific to Ingenic XBurst CPUs
|
||||
/mips64 Files specific to MIPS64 CPUs
|
||||
/lib Architecture specific library files
|
||||
/nds32 Files generic to NDS32 architecture
|
||||
/cpu CPU specific files
|
||||
|
@ -427,6 +431,14 @@ The following options need to be configured:
|
|||
In this mode, a single differential clock is used to supply
|
||||
clocks to the sysclock, ddrclock and usbclock.
|
||||
|
||||
CONFIG_SYS_CPC_REINIT_F
|
||||
This CONFIG is defined when the CPC is configured as SRAM at the
|
||||
time of U-boot entry and is required to be re-initialized.
|
||||
|
||||
CONFIG_DEEP_SLEEP
|
||||
Inidcates this SoC supports deep sleep feature. If deep sleep is
|
||||
supported, core will start to execute uboot when wakes up.
|
||||
|
||||
- Generic CPU options:
|
||||
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
|
||||
|
||||
|
@ -454,6 +466,9 @@ The following options need to be configured:
|
|||
CONFIG_SYS_FSL_DDRC_GEN3
|
||||
Freescale DDR3 controller.
|
||||
|
||||
CONFIG_SYS_FSL_DDRC_GEN4
|
||||
Freescale DDR4 controller.
|
||||
|
||||
CONFIG_SYS_FSL_DDRC_ARM_GEN3
|
||||
Freescale DDR3 controller for ARM-based SoCs.
|
||||
|
||||
|
@ -469,7 +484,15 @@ The following options need to be configured:
|
|||
|
||||
CONFIG_SYS_FSL_DDR3
|
||||
Board config to use DDR3. It can be enabled for SoCs with
|
||||
Freescale DDR3 controllers.
|
||||
Freescale DDR3 or DDR3L controllers.
|
||||
|
||||
CONFIG_SYS_FSL_DDR3L
|
||||
Board config to use DDR3L. It can be enabled for SoCs with
|
||||
DDR3L controllers.
|
||||
|
||||
CONFIG_SYS_FSL_DDR4
|
||||
Board config to use DDR4. It can be enabled for SoCs with
|
||||
DDR4 controllers.
|
||||
|
||||
CONFIG_SYS_FSL_IFC_BE
|
||||
Defines the IFC controller register space as Big Endian
|
||||
|
@ -486,6 +509,10 @@ The following options need to be configured:
|
|||
PBI commands can be used to configure SoC before it starts the execution.
|
||||
Please refer doc/README.pblimage for more details
|
||||
|
||||
CONFIG_SPL_FSL_PBL
|
||||
It adds a target to create boot binary having SPL binary in PBI format
|
||||
concatenated with u-boot binary.
|
||||
|
||||
CONFIG_SYS_FSL_DDR_BE
|
||||
Defines the DDR controller register space as Big Endian
|
||||
|
||||
|
@ -912,6 +939,7 @@ The following options need to be configured:
|
|||
The default command configuration includes all commands
|
||||
except those marked below with a "*".
|
||||
|
||||
CONFIG_CMD_AES AES 128 CBC encrypt/decrypt
|
||||
CONFIG_CMD_ASKENV * ask for env variable
|
||||
CONFIG_CMD_BDI bdinfo
|
||||
CONFIG_CMD_BEDBUG * Include BedBug Debugger
|
||||
|
@ -1456,13 +1484,6 @@ The following options need to be configured:
|
|||
for your device
|
||||
- CONFIG_USBD_PRODUCTID 0xFFFF
|
||||
|
||||
Some USB device drivers may need to check USB cable attachment.
|
||||
In this case you can enable following config in BoardName.h:
|
||||
CONFIG_USB_CABLE_CHECK
|
||||
This enables function definition:
|
||||
- usb_cable_connected() in include/usb.h
|
||||
Implementation of this function is board-specific.
|
||||
|
||||
- ULPI Layer Support:
|
||||
The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
|
||||
the generic ULPI layer. The generic layer accesses the ULPI PHY
|
||||
|
@ -3316,6 +3337,9 @@ FIT uImage format:
|
|||
continuing (the hardware starts execution after just
|
||||
loading the first page rather than the full 4K).
|
||||
|
||||
CONFIG_SPL_SKIP_RELOCATE
|
||||
Avoid SPL relocation
|
||||
|
||||
CONFIG_SPL_NAND_BASE
|
||||
Include nand_base.c in the SPL. Requires
|
||||
CONFIG_SPL_NAND_DRIVERS.
|
||||
|
@ -4510,8 +4534,13 @@ This firmware often needs to be loaded during U-Boot booting, so macros
|
|||
are used to identify the storage device (NOR flash, SPI, etc) and the address
|
||||
within that device.
|
||||
|
||||
- CONFIG_SYS_QE_FMAN_FW_ADDR
|
||||
The address in the storage device where the firmware is located. The
|
||||
- CONFIG_SYS_FMAN_FW_ADDR
|
||||
The address in the storage device where the FMAN microcode is located. The
|
||||
meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
|
||||
is also specified.
|
||||
|
||||
- CONFIG_SYS_QE_FW_ADDR
|
||||
The address in the storage device where the QE microcode is located. The
|
||||
meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
|
||||
is also specified.
|
||||
|
||||
|
|
|
@ -1,3 +1,6 @@
|
|||
obj-$(CONFIG_AT91FAMILY) += at91-common/
|
||||
obj-$(CONFIG_TEGRA) += $(SOC)-common/
|
||||
obj-$(CONFIG_TEGRA20) += tegra20-common/
|
||||
obj-$(CONFIG_TEGRA30) += tegra30-common/
|
||||
obj-$(CONFIG_TEGRA114) += tegra114-common/
|
||||
obj-$(CONFIG_TEGRA124) += tegra124-common/
|
||||
obj-$(CONFIG_TEGRA) += tegra-common/
|
||||
|
|
|
@ -19,74 +19,6 @@ enum security_op {
|
|||
SECURITY_ENCRYPT = 1 << 1, /* Encrypt the data */
|
||||
};
|
||||
|
||||
static void debug_print_vector(char *name, u32 num_bytes, u8 *data)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
debug("%s [%d] @0x%08x", name, num_bytes, (u32)data);
|
||||
for (i = 0; i < num_bytes; i++) {
|
||||
if (i % 16 == 0)
|
||||
debug(" = ");
|
||||
debug("%02x", data[i]);
|
||||
if ((i+1) % 16 != 0)
|
||||
debug(" ");
|
||||
}
|
||||
debug("\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* Apply chain data to the destination using EOR
|
||||
*
|
||||
* Each array is of length AES_AES_KEY_LENGTH.
|
||||
*
|
||||
* \param cbc_chain_data Chain data
|
||||
* \param src Source data
|
||||
* \param dst Destination data, which is modified here
|
||||
*/
|
||||
static void apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 16; i++)
|
||||
*dst++ = *src++ ^ *cbc_chain_data++;
|
||||
}
|
||||
|
||||
/**
|
||||
* Encrypt some data with AES.
|
||||
*
|
||||
* \param key_schedule Expanded key to use
|
||||
* \param src Source data to encrypt
|
||||
* \param dst Destination buffer
|
||||
* \param num_aes_blocks Number of AES blocks to encrypt
|
||||
*/
|
||||
static void encrypt_object(u8 *key_schedule, u8 *src, u8 *dst,
|
||||
u32 num_aes_blocks)
|
||||
{
|
||||
u8 tmp_data[AES_KEY_LENGTH];
|
||||
u8 *cbc_chain_data;
|
||||
u32 i;
|
||||
|
||||
cbc_chain_data = zero_key; /* Convenient array of 0's for IV */
|
||||
|
||||
for (i = 0; i < num_aes_blocks; i++) {
|
||||
debug("encrypt_object: block %d of %d\n", i, num_aes_blocks);
|
||||
debug_print_vector("AES Src", AES_KEY_LENGTH, src);
|
||||
|
||||
/* Apply the chain data */
|
||||
apply_cbc_chain_data(cbc_chain_data, src, tmp_data);
|
||||
debug_print_vector("AES Xor", AES_KEY_LENGTH, tmp_data);
|
||||
|
||||
/* encrypt the AES block */
|
||||
aes_encrypt(tmp_data, key_schedule, dst);
|
||||
debug_print_vector("AES Dst", AES_KEY_LENGTH, dst);
|
||||
|
||||
/* Update pointers for next loop. */
|
||||
cbc_chain_data = dst;
|
||||
src += AES_KEY_LENGTH;
|
||||
dst += AES_KEY_LENGTH;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Shift a vector left by one bit
|
||||
*
|
||||
|
@ -129,39 +61,31 @@ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst,
|
|||
for (i = 0; i < AES_KEY_LENGTH; i++)
|
||||
tmp_data[i] = 0;
|
||||
|
||||
encrypt_object(key_schedule, tmp_data, left, 1);
|
||||
debug_print_vector("AES(key, nonce)", AES_KEY_LENGTH, left);
|
||||
aes_cbc_encrypt_blocks(key_schedule, tmp_data, left, 1);
|
||||
|
||||
left_shift_vector(left, k1, sizeof(left));
|
||||
debug_print_vector("L", AES_KEY_LENGTH, left);
|
||||
|
||||
if ((left[0] >> 7) != 0) /* get MSB of L */
|
||||
k1[AES_KEY_LENGTH-1] ^= AES_CMAC_CONST_RB;
|
||||
debug_print_vector("K1", AES_KEY_LENGTH, k1);
|
||||
|
||||
/* compute the AES-CMAC value */
|
||||
for (i = 0; i < num_aes_blocks; i++) {
|
||||
/* Apply the chain data */
|
||||
apply_cbc_chain_data(cbc_chain_data, src, tmp_data);
|
||||
aes_apply_cbc_chain_data(cbc_chain_data, src, tmp_data);
|
||||
|
||||
/* for the final block, XOR K1 into the IV */
|
||||
if (i == num_aes_blocks - 1)
|
||||
apply_cbc_chain_data(tmp_data, k1, tmp_data);
|
||||
aes_apply_cbc_chain_data(tmp_data, k1, tmp_data);
|
||||
|
||||
/* encrypt the AES block */
|
||||
aes_encrypt(tmp_data, key_schedule, dst);
|
||||
|
||||
debug("sign_obj: block %d of %d\n", i, num_aes_blocks);
|
||||
debug_print_vector("AES-CMAC Src", AES_KEY_LENGTH, src);
|
||||
debug_print_vector("AES-CMAC Xor", AES_KEY_LENGTH, tmp_data);
|
||||
debug_print_vector("AES-CMAC Dst", AES_KEY_LENGTH, dst);
|
||||
|
||||
/* Update pointers for next loop. */
|
||||
cbc_chain_data = dst;
|
||||
src += AES_KEY_LENGTH;
|
||||
}
|
||||
|
||||
debug_print_vector("AES-CMAC Hash", AES_KEY_LENGTH, dst);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -180,7 +104,6 @@ static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src,
|
|||
u8 key_schedule[AES_EXPAND_KEY_LENGTH];
|
||||
|
||||
debug("encrypt_and_sign: length = %d\n", length);
|
||||
debug_print_vector("AES key", AES_KEY_LENGTH, key);
|
||||
|
||||
/*
|
||||
* The only need for a key is for signing/checksum purposes, so
|
||||
|
@ -193,7 +116,7 @@ static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src,
|
|||
if (oper & SECURITY_ENCRYPT) {
|
||||
/* Perform this in place, resulting in src being encrypted. */
|
||||
debug("encrypt_and_sign: begin encryption\n");
|
||||
encrypt_object(key_schedule, src, src, num_aes_blocks);
|
||||
aes_cbc_encrypt_blocks(key_schedule, src, src, num_aes_blocks);
|
||||
debug("encrypt_and_sign: end encryption\n");
|
||||
}
|
||||
|
||||
|
|
147
arch/arm/include/asm/arch-rmobile/ehci-rmobile.h
Normal file
147
arch/arm/include/asm/arch-rmobile/ehci-rmobile.h
Normal file
|
@ -0,0 +1,147 @@
|
|||
/*
|
||||
* Copyright (C) 2013,2014 Renesas Electronics Corporation
|
||||
* Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __EHCI_RMOBILE_H__
|
||||
#define __EHCI_RMOBILE_H__
|
||||
|
||||
/* Register offset */
|
||||
#define OHCI_OFFSET 0x00
|
||||
#define OHCI_SIZE 0x1000
|
||||
#define EHCI_OFFSET 0x1000
|
||||
#define EHCI_SIZE 0x1000
|
||||
|
||||
#define EHCI_USBCMD (EHCI_OFFSET + 0x0020)
|
||||
|
||||
/* USBCTR */
|
||||
#define DIRPD (1 << 8)
|
||||
#define PLL_RST (1 << 2)
|
||||
#define PCICLK_MASK (1 << 1)
|
||||
#define USBH_RST (1 << 0)
|
||||
|
||||
/* CMND_STS */
|
||||
#define SERREN (1 << 8)
|
||||
#define PERREN (1 << 6)
|
||||
#define MASTEREN (1 << 2)
|
||||
#define MEMEN (1 << 1)
|
||||
|
||||
/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */
|
||||
#define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0))
|
||||
|
||||
/* AHBPCI_WIN1_CTR */
|
||||
#define PCIWIN1_PCICMD ((1 << 3)|(1 << 1))
|
||||
#define AHB_CFG_AHBPCI 0x40000000
|
||||
#define AHB_CFG_HOST 0x80000000
|
||||
|
||||
/* AHBPCI_WIN2_CTR */
|
||||
#define PCIWIN2_PCICMD ((1 << 2)|(1 << 1))
|
||||
|
||||
/* PCI_INT_ENABLE */
|
||||
#define USBH_PMEEN (1 << 19)
|
||||
#define USBH_INTBEN (1 << 17)
|
||||
#define USBH_INTAEN (1 << 16)
|
||||
|
||||
/* AHB_BUS_CTR */
|
||||
#define SMODE_READY_CTR (1 << 17)
|
||||
#define SMODE_READ_BURST (1 << 16)
|
||||
#define MMODE_HBUSREQ (1 << 7)
|
||||
#define MMODE_BOUNDARY ((1 << 6)|(1 << 5))
|
||||
#define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3))
|
||||
#define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3))
|
||||
#define MMODE_WR_INCR (1 << 2)
|
||||
#define MMODE_BYTE_BURST (1 << 1)
|
||||
#define MMODE_HTRANS (1 << 0)
|
||||
|
||||
/* PCI_ARBITER_CTR */
|
||||
#define PCIBUS_PARK_TIMER 0x00FF0000
|
||||
#define PCIBUS_PARK_TIMER_SET 0x00070000
|
||||
#define PCIBP_MODE (1 << 12)
|
||||
#define PCIREQ7 (1 << 7)
|
||||
#define PCIREQ6 (1 << 6)
|
||||
#define PCIREQ5 (1 << 5)
|
||||
#define PCIREQ4 (1 << 4)
|
||||
#define PCIREQ3 (1 << 3)
|
||||
#define PCIREQ2 (1 << 2)
|
||||
#define PCIREQ1 (1 << 1)
|
||||
#define PCIREQ0 (1 << 0)
|
||||
|
||||
#define SMSTPCR7 0xE615014C
|
||||
#define SMSTPCR703 (1 << 3)
|
||||
|
||||
/* Init AHB master and slave functions of the host logic */
|
||||
#define AHB_BUS_CTR_INIT \
|
||||
(SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \
|
||||
MMODE_BYTE_BURST | MMODE_HTRANS)
|
||||
|
||||
#define USBCTR_WIN_SIZE_1GB 0x800
|
||||
|
||||
/* PCI Configuration Registers */
|
||||
#define PCI_CONF_OHCI_OFFSET 0x10000
|
||||
#define PCI_CONF_EHCI_OFFSET 0x10100
|
||||
struct ahb_pciconf {
|
||||
u32 vid_did;
|
||||
u32 cmnd_sts;
|
||||
u32 rev;
|
||||
u32 cache_line;
|
||||
u32 basead;
|
||||
};
|
||||
|
||||
/* PCI Configuration Registers for AHB-PCI Bridge Registers */
|
||||
#define PCI_CONF_AHBPCI_OFFSET 0x10000
|
||||
struct ahbconf_pci_bridge {
|
||||
u32 vid_did; /* 0x00 */
|
||||
u32 cmnd_sts;
|
||||
u32 revid_cc;
|
||||
u32 cls_lt_ht_bist;
|
||||
u32 basead; /* 0x10 */
|
||||
u32 win1_basead;
|
||||
u32 win2_basead;
|
||||
u32 dummy0[5];
|
||||
u32 ssvdi_ssid; /* 0x2C */
|
||||
u32 dummy1[4];
|
||||
u32 intr_line_pin;
|
||||
};
|
||||
|
||||
/* AHB-PCI Bridge PCI Communication Registers */
|
||||
#define AHBPCI_OFFSET 0x10800
|
||||
struct ahbcom_pci_bridge {
|
||||
u32 pciahb_win1_ctr; /* 0x00 */
|
||||
u32 pciahb_win2_ctr;
|
||||
u32 pciahb_dct_ctr;
|
||||
u32 dummy0;
|
||||
u32 ahbpci_win1_ctr; /* 0x10 */
|
||||
u32 ahbpci_win2_ctr;
|
||||
u32 dummy1;
|
||||
u32 ahbpci_dct_ctr;
|
||||
u32 pci_int_enable; /* 0x20 */
|
||||
u32 pci_int_status;
|
||||
u32 dummy2[2];
|
||||
u32 ahb_bus_ctr; /* 0x30 */
|
||||
u32 usbctr;
|
||||
u32 dummy3[2];
|
||||
u32 pci_arbiter_ctr; /* 0x40 */
|
||||
u32 dummy4;
|
||||
u32 pci_unit_rev; /* 0x48 */
|
||||
};
|
||||
|
||||
struct rmobile_ehci_reg {
|
||||
u32 hciversion; /* hciversion/caplength */
|
||||
u32 hcsparams; /* hcsparams */
|
||||
u32 hccparams; /* hccparams */
|
||||
u32 hcsp_portroute; /* hcsp_portroute */
|
||||
u32 usbcmd; /* usbcmd */
|
||||
u32 usbsts; /* usbsts */
|
||||
u32 usbintr; /* usbintr */
|
||||
u32 frindex; /* frindex */
|
||||
u32 ctrldssegment; /* ctrldssegment */
|
||||
u32 periodiclistbase; /* periodiclistbase */
|
||||
u32 asynclistaddr; /* asynclistaddr */
|
||||
u32 dummy[9];
|
||||
u32 configflag; /* configflag */
|
||||
u32 portsc; /* portsc */
|
||||
};
|
||||
|
||||
#endif /* __EHCI_RMOBILE_H__ */
|
|
@ -759,6 +759,54 @@ void bfin_reset_boot_spi_cs(unsigned short pin)
|
|||
udelay(1);
|
||||
}
|
||||
|
||||
int name_to_gpio(const char *name)
|
||||
{
|
||||
int port_base;
|
||||
|
||||
if (tolower(*name) == 'p') {
|
||||
++name;
|
||||
|
||||
switch (tolower(*name)) {
|
||||
#ifdef GPIO_PA0
|
||||
case 'a': port_base = GPIO_PA0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PB0
|
||||
case 'b': port_base = GPIO_PB0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PC0
|
||||
case 'c': port_base = GPIO_PC0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PD0
|
||||
case 'd': port_base = GPIO_PD0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PE0
|
||||
case 'e': port_base = GPIO_PE0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PF0
|
||||
case 'f': port_base = GPIO_PF0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PG0
|
||||
case 'g': port_base = GPIO_PG0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PH0
|
||||
case 'h': port_base = GPIO_PH0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PI0
|
||||
case 'i': port_base = GPIO_PI0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PJ
|
||||
case 'j': port_base = GPIO_PJ0; break;
|
||||
#endif
|
||||
default: return -1;
|
||||
}
|
||||
|
||||
++name;
|
||||
} else
|
||||
port_base = 0;
|
||||
|
||||
return port_base + simple_strtoul(name, NULL, 10);
|
||||
}
|
||||
|
||||
void gpio_labels(void)
|
||||
{
|
||||
int c, gpio;
|
||||
|
|
|
@ -160,55 +160,6 @@ static inline int gpio_is_valid(int number)
|
|||
|
||||
#include <linux/ctype.h>
|
||||
|
||||
static inline int name_to_gpio(const char *name)
|
||||
{
|
||||
int port_base;
|
||||
|
||||
if (tolower(*name) == 'p') {
|
||||
++name;
|
||||
|
||||
switch (tolower(*name)) {
|
||||
#ifdef GPIO_PA0
|
||||
case 'a': port_base = GPIO_PA0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PB0
|
||||
case 'b': port_base = GPIO_PB0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PC0
|
||||
case 'c': port_base = GPIO_PC0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PD0
|
||||
case 'd': port_base = GPIO_PD0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PE0
|
||||
case 'e': port_base = GPIO_PE0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PF0
|
||||
case 'f': port_base = GPIO_PF0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PG0
|
||||
case 'g': port_base = GPIO_PG0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PH0
|
||||
case 'h': port_base = GPIO_PH0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PI0
|
||||
case 'i': port_base = GPIO_PI0; break;
|
||||
#endif
|
||||
#ifdef GPIO_PJ
|
||||
case 'j': port_base = GPIO_PJ0; break;
|
||||
#endif
|
||||
default: return -1;
|
||||
}
|
||||
|
||||
++name;
|
||||
} else
|
||||
port_base = 0;
|
||||
|
||||
return port_base + simple_strtoul(name, NULL, 10);
|
||||
}
|
||||
#define name_to_gpio(n) name_to_gpio(n)
|
||||
|
||||
#define gpio_status() gpio_labels()
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
|
|
@ -27,6 +27,8 @@ ENDIANNESS ?= -EB
|
|||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
|
||||
|
||||
__HAVE_ARCH_GENERIC_BOARD := y
|
||||
|
||||
#
|
||||
# From Linux arch/mips/Makefile
|
||||
#
|
||||
|
@ -52,4 +54,5 @@ PLATFORM_CPPFLAGS += -msoft-float
|
|||
PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS)
|
||||
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
|
||||
LDFLAGS_FINAL += --gc-sections -pie
|
||||
OBJCOPYFLAGS += --remove-section=.dynsym
|
||||
OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .got
|
||||
OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn
|
||||
|
|
|
@ -1,9 +0,0 @@
|
|||
#
|
||||
# (C) Copyright 2011
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y = incaip_wdt.o
|
||||
obj-y += incaip_clock.o asc_serial.o
|
|
@ -1,300 +0,0 @@
|
|||
/*
|
||||
* (INCA) ASC UART support
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/inca-ip.h>
|
||||
#include <serial.h>
|
||||
#include <linux/compiler.h>
|
||||
#include "asc_serial.h"
|
||||
|
||||
|
||||
#define SET_BIT(reg, mask) reg |= (mask)
|
||||
#define CLEAR_BIT(reg, mask) reg &= (~mask)
|
||||
#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
|
||||
#define SET_BITS(reg, mask) SET_BIT(reg, mask)
|
||||
#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
|
||||
|
||||
extern uint incaip_get_fpiclk(void);
|
||||
|
||||
static int serial_setopt (void);
|
||||
|
||||
/* pointer to ASC register base address */
|
||||
static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC;
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* serial_init - initialize a INCAASC channel
|
||||
*
|
||||
* This routine initializes the number of data bits, parity
|
||||
* and set the selected baud rate. Interrupts are disabled.
|
||||
* Set the modem control signals if the option is selected.
|
||||
*
|
||||
* RETURNS: N/A
|
||||
*/
|
||||
|
||||
static int asc_serial_init(void)
|
||||
{
|
||||
/* we have to set PMU.EN13 bit to enable an ASC device*/
|
||||
INCAASC_PMU_ENABLE(13);
|
||||
|
||||
/* and we have to set CLC register*/
|
||||
CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
|
||||
SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
|
||||
|
||||
/* initialy we are in async mode */
|
||||
pAsc->asc_con = ASCCON_M_8ASYNC;
|
||||
|
||||
/* select input port */
|
||||
pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
|
||||
|
||||
/* TXFIFO's filling level */
|
||||
SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
|
||||
ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL);
|
||||
/* enable TXFIFO */
|
||||
SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
|
||||
|
||||
/* RXFIFO's filling level */
|
||||
SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
|
||||
ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL);
|
||||
/* enable RXFIFO */
|
||||
SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
|
||||
|
||||
/* enable error signals */
|
||||
SET_BIT(pAsc->asc_con, ASCCON_FEN);
|
||||
SET_BIT(pAsc->asc_con, ASCCON_OEN);
|
||||
|
||||
/* acknowledge ASC interrupts */
|
||||
ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL);
|
||||
|
||||
/* disable ASC interrupts */
|
||||
ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL);
|
||||
|
||||
/* set FIFOs into the transparent mode */
|
||||
SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN);
|
||||
SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN);
|
||||
|
||||
/* set baud rate */
|
||||
serial_setbrg();
|
||||
|
||||
/* set the options */
|
||||
serial_setopt();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void asc_serial_setbrg(void)
|
||||
{
|
||||
ulong uiReloadValue, fdv;
|
||||
ulong f_ASC;
|
||||
|
||||
f_ASC = incaip_get_fpiclk();
|
||||
|
||||
#ifndef INCAASC_USE_FDV
|
||||
fdv = 2;
|
||||
uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
|
||||
#else
|
||||
fdv = INCAASC_FDV_HIGH_BAUDRATE;
|
||||
uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
|
||||
#endif /* INCAASC_USE_FDV */
|
||||
|
||||
if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
|
||||
{
|
||||
#ifndef INCAASC_USE_FDV
|
||||
fdv = 3;
|
||||
uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
|
||||
#else
|
||||
fdv = INCAASC_FDV_LOW_BAUDRATE;
|
||||
uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
|
||||
#endif /* INCAASC_USE_FDV */
|
||||
|
||||
if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
|
||||
{
|
||||
return; /* can't impossibly generate that baud rate */
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable Baud Rate Generator; BG should only be written when R=0 */
|
||||
CLEAR_BIT(pAsc->asc_con, ASCCON_R);
|
||||
|
||||
#ifndef INCAASC_USE_FDV
|
||||
/*
|
||||
* Disable Fractional Divider (FDE)
|
||||
* Divide clock by reload-value + constant (BRS)
|
||||
*/
|
||||
/* FDE = 0 */
|
||||
CLEAR_BIT(pAsc->asc_con, ASCCON_FDE);
|
||||
|
||||
if ( fdv == 2 )
|
||||
CLEAR_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 0 */
|
||||
else
|
||||
SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */
|
||||
|
||||
#else /* INCAASC_USE_FDV */
|
||||
|
||||
/* Enable Fractional Divider */
|
||||
SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
|
||||
|
||||
/* Set fractional divider value */
|
||||
pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
|
||||
|
||||
#endif /* INCAASC_USE_FDV */
|
||||
|
||||
/* Set reload value in BG */
|
||||
pAsc->asc_bg = uiReloadValue;
|
||||
|
||||
/* Enable Baud Rate Generator */
|
||||
SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* serial_setopt - set the serial options
|
||||
*
|
||||
* Set the channel operating mode to that specified. Following options
|
||||
* are supported: CREAD, CSIZE, PARENB, and PARODD.
|
||||
*
|
||||
* Note, this routine disables the transmitter. The calling routine
|
||||
* may have to re-enable it.
|
||||
*
|
||||
* RETURNS:
|
||||
* Returns 0 to indicate success, otherwise -1 is returned
|
||||
*/
|
||||
|
||||
static int serial_setopt (void)
|
||||
{
|
||||
ulong con;
|
||||
|
||||
switch ( ASC_OPTIONS & ASCOPT_CSIZE )
|
||||
{
|
||||
/* 7-bit-data */
|
||||
case ASCOPT_CS7:
|
||||
con = ASCCON_M_7ASYNCPAR; /* 7-bit-data and parity bit */
|
||||
break;
|
||||
|
||||
/* 8-bit-data */
|
||||
case ASCOPT_CS8:
|
||||
if ( ASC_OPTIONS & ASCOPT_PARENB )
|
||||
con = ASCCON_M_8ASYNCPAR; /* 8-bit-data and parity bit */
|
||||
else
|
||||
con = ASCCON_M_8ASYNC; /* 8-bit-data no parity */
|
||||
break;
|
||||
|
||||
/*
|
||||
* only 7 and 8-bit frames are supported
|
||||
* if we don't use IOCTL extensions
|
||||
*/
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
if ( ASC_OPTIONS & ASCOPT_STOPB )
|
||||
SET_BIT(con, ASCCON_STP); /* 2 stop bits */
|
||||
else
|
||||
CLEAR_BIT(con, ASCCON_STP); /* 1 stop bit */
|
||||
|
||||
if ( ASC_OPTIONS & ASCOPT_PARENB )
|
||||
SET_BIT(con, ASCCON_PEN); /* enable parity checking */
|
||||
else
|
||||
CLEAR_BIT(con, ASCCON_PEN); /* disable parity checking */
|
||||
|
||||
if ( ASC_OPTIONS & ASCOPT_PARODD )
|
||||
SET_BIT(con, ASCCON_ODD); /* odd parity */
|
||||
else
|
||||
CLEAR_BIT(con, ASCCON_ODD); /* even parity */
|
||||
|
||||
if ( ASC_OPTIONS & ASCOPT_CREAD )
|
||||
SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */
|
||||
|
||||
pAsc->asc_con |= con;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void asc_serial_putc(const char c)
|
||||
{
|
||||
uint txFl = 0;
|
||||
|
||||
if (c == '\n') serial_putc ('\r');
|
||||
|
||||
/* check do we have a free space in the TX FIFO */
|
||||
/* get current filling level */
|
||||
do
|
||||
{
|
||||
txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
|
||||
}
|
||||
while ( txFl == INCAASC_TXFIFO_FULL );
|
||||
|
||||
pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
|
||||
|
||||
/* check for errors */
|
||||
if ( pAsc->asc_con & ASCCON_OE )
|
||||
{
|
||||
SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static int asc_serial_getc(void)
|
||||
{
|
||||
ulong symbol_mask;
|
||||
char c;
|
||||
|
||||
while (!serial_tstc());
|
||||
|
||||
symbol_mask =
|
||||
((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
|
||||
|
||||
c = (char)(pAsc->asc_rbuf & symbol_mask);
|
||||
|
||||
return c;
|
||||
}
|
||||
|
||||
static int asc_serial_tstc(void)
|
||||
{
|
||||
int res = 1;
|
||||
|
||||
if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
|
||||
{
|
||||
res = 0;
|
||||
}
|
||||
else if ( pAsc->asc_con & ASCCON_FE )
|
||||
{
|
||||
SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
|
||||
res = 0;
|
||||
}
|
||||
else if ( pAsc->asc_con & ASCCON_PE )
|
||||
{
|
||||
SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
|
||||
res = 0;
|
||||
}
|
||||
else if ( pAsc->asc_con & ASCCON_OE )
|
||||
{
|
||||
SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
|
||||
res = 0;
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
static struct serial_device asc_serial_drv = {
|
||||
.name = "asc_serial",
|
||||
.start = asc_serial_init,
|
||||
.stop = NULL,
|
||||
.setbrg = asc_serial_setbrg,
|
||||
.putc = asc_serial_putc,
|
||||
.puts = default_serial_puts,
|
||||
.getc = asc_serial_getc,
|
||||
.tstc = asc_serial_tstc,
|
||||
};
|
||||
|
||||
void asc_serial_initialize(void)
|
||||
{
|
||||
serial_register(&asc_serial_drv);
|
||||
}
|
||||
|
||||
__weak struct serial_device *default_serial_console(void)
|
||||
{
|
||||
return &asc_serial_drv;
|
||||
}
|
|
@ -1,177 +0,0 @@
|
|||
/* incaAscSio.h - (INCA) ASC UART tty driver header */
|
||||
|
||||
#ifndef __INCincaAscSioh
|
||||
#define __INCincaAscSioh
|
||||
|
||||
#include <asm/inca-ip.h>
|
||||
|
||||
/* channel operating modes */
|
||||
#define ASCOPT_CSIZE 0x00000003
|
||||
#define ASCOPT_CS7 0x00000001
|
||||
#define ASCOPT_CS8 0x00000002
|
||||
#define ASCOPT_PARENB 0x00000004
|
||||
#define ASCOPT_STOPB 0x00000008
|
||||
#define ASCOPT_PARODD 0x00000010
|
||||
#define ASCOPT_CREAD 0x00000020
|
||||
|
||||
#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
|
||||
|
||||
/* ASC input select (0 or 1) */
|
||||
#define CONSOLE_TTY 0
|
||||
|
||||
/* use fractional divider for baudrate settings */
|
||||
#define INCAASC_USE_FDV
|
||||
|
||||
#ifdef INCAASC_USE_FDV
|
||||
#define INCAASC_FDV_LOW_BAUDRATE 71
|
||||
#define INCAASC_FDV_HIGH_BAUDRATE 453
|
||||
#endif /*INCAASC_USE_FDV*/
|
||||
|
||||
|
||||
#define INCAASC_TXFIFO_FL 1
|
||||
#define INCAASC_RXFIFO_FL 1
|
||||
#define INCAASC_TXFIFO_FULL 16
|
||||
|
||||
/* interrupt lines masks for the ASC device interrupts*/
|
||||
/* change these macroses if it's necessary */
|
||||
#define INCAASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */
|
||||
|
||||
#define INCAASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */
|
||||
#define INCAASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */
|
||||
#define INCAASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */
|
||||
#define INCAASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/
|
||||
|
||||
/* interrupt controller access macros */
|
||||
#define ASC_INTERRUPTS_ENABLE(X) \
|
||||
*((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X;
|
||||
#define ASC_INTERRUPTS_DISABLE(X) \
|
||||
*((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X;
|
||||
#define ASC_INTERRUPTS_CLEAR(X) \
|
||||
*((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X;
|
||||
|
||||
/* CLC register's bits and bitfields */
|
||||
#define ASCCLC_DISR 0x00000001
|
||||
#define ASCCLC_DISS 0x00000002
|
||||
#define ASCCLC_RMCMASK 0x0000FF00
|
||||
#define ASCCLC_RMCOFFSET 8
|
||||
|
||||
/* CON register's bits and bitfields */
|
||||
#define ASCCON_MODEMASK 0x0007
|
||||
#define ASCCON_M_8SYNC 0x0
|
||||
#define ASCCON_M_8ASYNC 0x1
|
||||
#define ASCCON_M_8IRDAASYNC 0x2
|
||||
#define ASCCON_M_7ASYNCPAR 0x3
|
||||
#define ASCCON_M_9ASYNC 0x4
|
||||
#define ASCCON_M_8WAKEUPASYNC 0x5
|
||||
#define ASCCON_M_8ASYNCPAR 0x7
|
||||
#define ASCCON_STP 0x0008
|
||||
#define ASCCON_REN 0x0010
|
||||
#define ASCCON_PEN 0x0020
|
||||
#define ASCCON_FEN 0x0040
|
||||
#define ASCCON_OEN 0x0080
|
||||
#define ASCCON_PE 0x0100
|
||||
#define ASCCON_FE 0x0200
|
||||
#define ASCCON_OE 0x0400
|
||||
#define ASCCON_FDE 0x0800
|
||||
#define ASCCON_ODD 0x1000
|
||||
#define ASCCON_BRS 0x2000
|
||||
#define ASCCON_LB 0x4000
|
||||
#define ASCCON_R 0x8000
|
||||
|
||||
/* WHBCON register's bits and bitfields */
|
||||
#define ASCWHBCON_CLRREN 0x0010
|
||||
#define ASCWHBCON_SETREN 0x0020
|
||||
#define ASCWHBCON_CLRPE 0x0100
|
||||
#define ASCWHBCON_CLRFE 0x0200
|
||||
#define ASCWHBCON_CLROE 0x0400
|
||||
#define ASCWHBCON_SETPE 0x0800
|
||||
#define ASCWHBCON_SETFE 0x1000
|
||||
#define ASCWHBCON_SETOE 0x2000
|
||||
|
||||
/* ABCON register's bits and bitfields */
|
||||
#define ASCABCON_ABEN 0x0001
|
||||
#define ASCABCON_AUREN 0x0002
|
||||
#define ASCABCON_ABSTEN 0x0004
|
||||
#define ASCABCON_ABDETEN 0x0008
|
||||
#define ASCABCON_FCDETEN 0x0010
|
||||
#define ASCABCON_EMMASK 0x0300
|
||||
#define ASCABCON_EMOFF 8
|
||||
#define ASCABCON_EM_DISAB 0x0
|
||||
#define ASCABCON_EM_DURAB 0x1
|
||||
#define ASCABCON_EM_ALWAYS 0x2
|
||||
#define ASCABCON_TXINV 0x0400
|
||||
#define ASCABCON_RXINV 0x0800
|
||||
|
||||
/* FDV register mask, offset and bitfields*/
|
||||
#define ASCFDV_VALUE_MASK 0x000001FF
|
||||
|
||||
/* WHBABCON register's bits and bitfields */
|
||||
#define ASCWHBABCON_SETABEN 0x0001
|
||||
#define ASCWHBABCON_CLRABEN 0x0002
|
||||
|
||||
/* ABSTAT register's bits and bitfields */
|
||||
#define ASCABSTAT_FCSDET 0x0001
|
||||
#define ASCABSTAT_FCCDET 0x0002
|
||||
#define ASCABSTAT_SCSDET 0x0004
|
||||
#define ASCABSTAT_SCCDET 0x0008
|
||||
#define ASCABSTAT_DETWAIT 0x0010
|
||||
|
||||
/* WHBABSTAT register's bits and bitfields */
|
||||
#define ASCWHBABSTAT_CLRFCSDET 0x0001
|
||||
#define ASCWHBABSTAT_SETFCSDET 0x0002
|
||||
#define ASCWHBABSTAT_CLRFCCDET 0x0004
|
||||
#define ASCWHBABSTAT_SETFCCDET 0x0008
|
||||
#define ASCWHBABSTAT_CLRSCSDET 0x0010
|
||||
#define ASCWHBABSTAT_SETSCSDET 0x0020
|
||||
#define ASCWHBABSTAT_SETSCCDET 0x0040
|
||||
#define ASCWHBABSTAT_CLRSCCDET 0x0080
|
||||
#define ASCWHBABSTAT_CLRDETWAIT 0x0100
|
||||
#define ASCWHBABSTAT_SETDETWAIT 0x0200
|
||||
|
||||
/* TXFCON register's bits and bitfields */
|
||||
#define ASCTXFCON_TXFEN 0x0001
|
||||
#define ASCTXFCON_TXFFLU 0x0002
|
||||
#define ASCTXFCON_TXTMEN 0x0004
|
||||
#define ASCTXFCON_TXFITLMASK 0x3F00
|
||||
#define ASCTXFCON_TXFITLOFF 8
|
||||
|
||||
/* RXFCON register's bits and bitfields */
|
||||
#define ASCRXFCON_RXFEN 0x0001
|
||||
#define ASCRXFCON_RXFFLU 0x0002
|
||||
#define ASCRXFCON_RXTMEN 0x0004
|
||||
#define ASCRXFCON_RXFITLMASK 0x3F00
|
||||
#define ASCRXFCON_RXFITLOFF 8
|
||||
|
||||
/* FSTAT register's bits and bitfields */
|
||||
#define ASCFSTAT_RXFFLMASK 0x003F
|
||||
#define ASCFSTAT_TXFFLMASK 0x3F00
|
||||
#define ASCFSTAT_TXFFLOFF 8
|
||||
|
||||
#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT);
|
||||
|
||||
typedef struct /* incaAsc_t */
|
||||
{
|
||||
volatile unsigned long asc_clc; /*0x0000*/
|
||||
volatile unsigned long asc_pisel; /*0x0004*/
|
||||
volatile unsigned long asc_rsvd1[2]; /* for mapping */ /*0x0008*/
|
||||
volatile unsigned long asc_con; /*0x0010*/
|
||||
volatile unsigned long asc_bg; /*0x0014*/
|
||||
volatile unsigned long asc_fdv; /*0x0018*/
|
||||
volatile unsigned long asc_pmw; /* not used */ /*0x001C*/
|
||||
volatile unsigned long asc_tbuf; /*0x0020*/
|
||||
volatile unsigned long asc_rbuf; /*0x0024*/
|
||||
volatile unsigned long asc_rsvd2[2]; /* for mapping */ /*0x0028*/
|
||||
volatile unsigned long asc_abcon; /*0x0030*/
|
||||
volatile unsigned long asc_abstat; /* not used */ /*0x0034*/
|
||||
volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0038*/
|
||||
volatile unsigned long asc_rxfcon; /*0x0040*/
|
||||
volatile unsigned long asc_txfcon; /*0x0044*/
|
||||
volatile unsigned long asc_fstat; /*0x0048*/
|
||||
volatile unsigned long asc_rsvd4; /* for mapping */ /*0x004C*/
|
||||
volatile unsigned long asc_whbcon; /*0x0050*/
|
||||
volatile unsigned long asc_whbabcon; /*0x0054*/
|
||||
volatile unsigned long asc_whbabstat; /* not used */ /*0x0058*/
|
||||
|
||||
} incaAsc_t;
|
||||
|
||||
#endif /* __INCincaAscSioh */
|
|
@ -1,8 +0,0 @@
|
|||
#
|
||||
# (C) Copyright 2011
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
PLATFORM_CPPFLAGS += -mtune=4kc
|
|
@ -1,100 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/inca-ip.h>
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* get_cpuclk - returns the frequency of the CPU.
|
||||
*
|
||||
* Gets the value directly from the INCA-IP hardware.
|
||||
*
|
||||
* RETURNS:
|
||||
* 150.000.000 for 150 MHz
|
||||
* 133.333.333 for 133 MHz (= 400MHz/3)
|
||||
* 100.000.000 for 100 MHz (= 400MHz/4)
|
||||
* NOTE:
|
||||
* This functions should be used by the hardware driver to get the correct
|
||||
* frequency of the CPU. Don't use the macros, which are set to init the CPU
|
||||
* frequency in the ROM code.
|
||||
*/
|
||||
uint incaip_get_cpuclk (void)
|
||||
{
|
||||
/*-------------------------------------------------------------------------*/
|
||||
/* CPU Clock Input Multiplexer (MUX I) */
|
||||
/* Multiplexer MUX I selects the maximum input clock to the CPU. */
|
||||
/*-------------------------------------------------------------------------*/
|
||||
if (*((volatile ulong *) INCA_IP_CGU_CGU_MUXCR) &
|
||||
INCA_IP_CGU_CGU_MUXCR_MUXI) {
|
||||
/* MUX I set to 150 MHz clock */
|
||||
return 150000000;
|
||||
} else {
|
||||
/* MUX I set to 100/133 MHz clock */
|
||||
if (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0x40) {
|
||||
/* Division value is 1/3, maximum CPU operating */
|
||||
/* frequency is 133.3 MHz */
|
||||
return 133333333;
|
||||
} else {
|
||||
/* Division value is 1/4, maximum CPU operating */
|
||||
/* frequency is 100 MHz */
|
||||
return 100000000;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* get_fpiclk - returns the frequency of the FPI bus.
|
||||
*
|
||||
* Gets the value directly from the INCA-IP hardware.
|
||||
*
|
||||
* RETURNS: Frquency in Hz
|
||||
*
|
||||
* NOTE:
|
||||
* This functions should be used by the hardware driver to get the correct
|
||||
* frequency of the CPU. Don't use the macros, which are set to init the CPU
|
||||
* frequency in the ROM code.
|
||||
* The calculation for the
|
||||
*/
|
||||
uint incaip_get_fpiclk (void)
|
||||
{
|
||||
uint clkCPU;
|
||||
|
||||
clkCPU = incaip_get_cpuclk ();
|
||||
|
||||
switch (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0xC) {
|
||||
case 0x4:
|
||||
return clkCPU >> 1; /* devided by 2 */
|
||||
break;
|
||||
case 0x8:
|
||||
return clkCPU >> 2; /* devided by 4 */
|
||||
break;
|
||||
default:
|
||||
return clkCPU;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
int incaip_set_cpuclk (void)
|
||||
{
|
||||
extern void ebu_init(long);
|
||||
extern void cgu_init(long);
|
||||
extern void sdram_init(long);
|
||||
char tmp[64];
|
||||
ulong cpuclk;
|
||||
|
||||
if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) {
|
||||
cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
|
||||
cgu_init (cpuclk);
|
||||
ebu_init (cpuclk);
|
||||
sdram_init (cpuclk);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -1,55 +0,0 @@
|
|||
/*
|
||||
* INCA-IP Watchdog timer management code.
|
||||
*
|
||||
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/regdef.h>
|
||||
|
||||
|
||||
#define WD_BASE 0xb8000000
|
||||
#define WD_CON0(value) 0x0020(value)
|
||||
#define WD_CON1(value) 0x0024(value)
|
||||
#define WD_DISABLE 0x00000008
|
||||
#define WD_ENABLE 0x00000000
|
||||
#define WD_WRITE_PW 0xFFFC00F8
|
||||
#define WD_WRITE_ENDINIT 0xFFFC00F3
|
||||
#define WD_WRITE_INIT 0xFFFC00F2
|
||||
|
||||
|
||||
.globl disable_incaip_wdt
|
||||
disable_incaip_wdt:
|
||||
li t0, WD_BASE
|
||||
|
||||
/* Calculate password.
|
||||
*/
|
||||
lw t2, WD_CON1(t0)
|
||||
and t2, 0xC
|
||||
|
||||
lw t3, WD_CON0(t0)
|
||||
and t3, 0xFFFFFF01
|
||||
|
||||
or t3, t2
|
||||
or t3, 0xF0
|
||||
|
||||
sw t3, WD_CON0(t0) /* write password */
|
||||
|
||||
/* Clear ENDINIT.
|
||||
*/
|
||||
li t1, WD_WRITE_INIT
|
||||
sw t1, WD_CON0(t0)
|
||||
|
||||
|
||||
li t1, WD_DISABLE
|
||||
sw t1, WD_CON1(t0) /* disable watchdog */
|
||||
li t1, WD_WRITE_PW
|
||||
sw t1, WD_CON0(t0) /* write password */
|
||||
li t1, WD_WRITE_ENDINIT
|
||||
sw t1, WD_CON0(t0) /* end command */
|
||||
|
||||
jr ra
|
||||
nop
|
|
@ -7,6 +7,11 @@
|
|||
|
||||
#include <common.h>
|
||||
|
||||
int interrupt_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void enable_interrupts(void)
|
||||
{
|
||||
}
|
||||
|
|
|
@ -7,6 +7,11 @@
|
|||
|
||||
#include <common.h>
|
||||
|
||||
int interrupt_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void enable_interrupts(void)
|
||||
{
|
||||
}
|
||||
|
|
|
@ -53,6 +53,7 @@ SECTIONS
|
|||
|
||||
. = ALIGN(4);
|
||||
__image_copy_end = .;
|
||||
__init_end = .;
|
||||
|
||||
.rel.dyn : {
|
||||
__rel_dyn_start = .;
|
||||
|
@ -60,27 +61,7 @@ SECTIONS
|
|||
__rel_dyn_end = .;
|
||||
}
|
||||
|
||||
.deadcode : {
|
||||
/*
|
||||
* Workaround for a binutils feature (or bug?).
|
||||
*
|
||||
* The GNU ld from binutils puts the dynamic relocation
|
||||
* entries into the .rel.dyn section. Sometimes it
|
||||
* allocates more dynamic relocation entries than it needs
|
||||
* and the unused slots are set to R_MIPS_NONE entries.
|
||||
*
|
||||
* However the size of the .rel.dyn section in the ELF
|
||||
* section header does not cover the unused entries, so
|
||||
* objcopy removes those during stripping.
|
||||
*
|
||||
* Create a small section here to avoid that.
|
||||
*/
|
||||
LONG(0xffffffff);
|
||||
}
|
||||
|
||||
.dynsym : {
|
||||
*(.dynsym)
|
||||
}
|
||||
_end = .;
|
||||
|
||||
.bss __rel_dyn_start (OVERLAY) : {
|
||||
__bss_start = .;
|
||||
|
@ -91,15 +72,39 @@ SECTIONS
|
|||
__bss_end = .;
|
||||
}
|
||||
|
||||
/DISCARD/ : {
|
||||
.dynsym _end : {
|
||||
*(.dynsym)
|
||||
}
|
||||
|
||||
.dynbss : {
|
||||
*(.dynbss)
|
||||
}
|
||||
|
||||
.dynstr : {
|
||||
*(.dynstr)
|
||||
}
|
||||
|
||||
.dynamic : {
|
||||
*(.dynamic)
|
||||
*(.interp)
|
||||
*(.hash)
|
||||
*(.gnu.*)
|
||||
}
|
||||
|
||||
.plt : {
|
||||
*(.plt)
|
||||
*(.got.plt)
|
||||
*(.rel.plt)
|
||||
}
|
||||
|
||||
.interp : {
|
||||
*(.interp)
|
||||
}
|
||||
|
||||
.gnu : {
|
||||
*(.gnu*)
|
||||
}
|
||||
|
||||
.MIPS.stubs : {
|
||||
*(.MIPS.stubs)
|
||||
}
|
||||
|
||||
.hash : {
|
||||
*(.hash)
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1,9 +0,0 @@
|
|||
#
|
||||
# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
extra-y = start.o
|
||||
obj-y = cpu.o timer.o jz_serial.o
|
||||
obj-$(CONFIG_JZ4740) += jz4740.o
|
|
@ -1,16 +0,0 @@
|
|||
#
|
||||
# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
PLATFORM_CPPFLAGS += -march=mips32
|
||||
PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
|
||||
ifdef CONFIG_SYS_BIG_ENDIAN
|
||||
PLATFORM_LDFLAGS += -m elf32btsmip
|
||||
else
|
||||
PLATFORM_LDFLAGS += -m elf32ltsmip
|
||||
endif
|
||||
|
||||
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
|
||||
-T $(srctree)/examples/standalone/mips.lds
|
|
@ -1,136 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
|
||||
* (C) Copyright 2011
|
||||
* Xiangfu Liu <xiangfu@openmobilefree.net>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/cacheops.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/jz4740.h>
|
||||
|
||||
#define cache_op(op, addr) \
|
||||
__asm__ __volatile__( \
|
||||
".set push\n" \
|
||||
".set noreorder\n" \
|
||||
".set mips3\n" \
|
||||
"cache %0, %1\n" \
|
||||
".set pop\n" \
|
||||
: \
|
||||
: "i" (op), "R" (*(unsigned char *)(addr)))
|
||||
|
||||
void __attribute__((weak)) _machine_restart(void)
|
||||
{
|
||||
struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
|
||||
struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
|
||||
u16 tmp;
|
||||
|
||||
/* wdt_select_extalclk() */
|
||||
tmp = readw(&wdt->tcsr);
|
||||
tmp &= ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN);
|
||||
tmp |= WDT_TCSR_EXT_EN;
|
||||
writew(tmp, &wdt->tcsr);
|
||||
|
||||
/* wdt_select_clk_div64() */
|
||||
tmp = readw(&wdt->tcsr);
|
||||
tmp &= ~WDT_TCSR_PRESCALE_MASK;
|
||||
tmp |= WDT_TCSR_PRESCALE64,
|
||||
writew(tmp, &wdt->tcsr);
|
||||
|
||||
writew(100, &wdt->tdr); /* wdt_set_data(100) */
|
||||
writew(0, &wdt->tcnt); /* wdt_set_count(0); */
|
||||
writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
|
||||
writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */
|
||||
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
_machine_restart();
|
||||
|
||||
fprintf(stderr, "*** reset failed ***\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
void flush_cache(ulong start_addr, ulong size)
|
||||
{
|
||||
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
|
||||
unsigned long addr = start_addr & ~(lsize - 1);
|
||||
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
|
||||
|
||||
for (; addr <= aend; addr += lsize) {
|
||||
cache_op(HIT_WRITEBACK_INV_D, addr);
|
||||
cache_op(HIT_INVALIDATE_I, addr);
|
||||
}
|
||||
}
|
||||
|
||||
void flush_dcache_range(ulong start_addr, ulong stop)
|
||||
{
|
||||
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
|
||||
unsigned long addr = start_addr & ~(lsize - 1);
|
||||
unsigned long aend = (stop - 1) & ~(lsize - 1);
|
||||
|
||||
for (; addr <= aend; addr += lsize)
|
||||
cache_op(HIT_WRITEBACK_INV_D, addr);
|
||||
}
|
||||
|
||||
void invalidate_dcache_range(ulong start_addr, ulong stop)
|
||||
{
|
||||
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
|
||||
unsigned long addr = start_addr & ~(lsize - 1);
|
||||
unsigned long aend = (stop - 1) & ~(lsize - 1);
|
||||
|
||||
for (; addr <= aend; addr += lsize)
|
||||
cache_op(HIT_INVALIDATE_D, addr);
|
||||
}
|
||||
|
||||
void flush_icache_all(void)
|
||||
{
|
||||
u32 addr, t = 0;
|
||||
|
||||
__asm__ __volatile__("mtc0 $0, $28"); /* Clear Taglo */
|
||||
__asm__ __volatile__("mtc0 $0, $29"); /* Clear TagHi */
|
||||
|
||||
for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
|
||||
addr += CONFIG_SYS_CACHELINE_SIZE) {
|
||||
cache_op(INDEX_STORE_TAG_I, addr);
|
||||
}
|
||||
|
||||
/* invalidate btb */
|
||||
__asm__ __volatile__(
|
||||
".set mips32\n\t"
|
||||
"mfc0 %0, $16, 7\n\t"
|
||||
"nop\n\t"
|
||||
"ori %0,2\n\t"
|
||||
"mtc0 %0, $16, 7\n\t"
|
||||
".set mips2\n\t"
|
||||
:
|
||||
: "r" (t));
|
||||
}
|
||||
|
||||
void flush_dcache_all(void)
|
||||
{
|
||||
u32 addr;
|
||||
|
||||
for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
|
||||
addr += CONFIG_SYS_CACHELINE_SIZE) {
|
||||
cache_op(INDEX_WRITEBACK_INV_D, addr);
|
||||
}
|
||||
|
||||
__asm__ __volatile__("sync");
|
||||
}
|
||||
|
||||
void flush_cache_all(void)
|
||||
{
|
||||
flush_dcache_all();
|
||||
flush_icache_all();
|
||||
}
|
|
@ -1,235 +0,0 @@
|
|||
/*
|
||||
* Jz4740 common routines
|
||||
* Copyright (c) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/jz4740.h>
|
||||
|
||||
void enable_interrupts(void)
|
||||
{
|
||||
}
|
||||
|
||||
int disable_interrupts(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* PLL output clock = EXTAL * NF / (NR * NO)
|
||||
* NF = FD + 2, NR = RD + 2
|
||||
* NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
|
||||
*/
|
||||
void pll_init(void)
|
||||
{
|
||||
struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
|
||||
|
||||
register unsigned int cfcr, plcr1;
|
||||
int n2FR[33] = {
|
||||
0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
|
||||
7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
|
||||
9
|
||||
};
|
||||
int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
|
||||
int nf, pllout2;
|
||||
|
||||
cfcr = CPM_CPCCR_CLKOEN |
|
||||
CPM_CPCCR_PCS |
|
||||
(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
|
||||
(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
|
||||
(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
|
||||
(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
|
||||
(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
|
||||
|
||||
pllout2 = (cfcr & CPM_CPCCR_PCS) ?
|
||||
CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
|
||||
|
||||
/* Init USB Host clock, pllout2 must be n*48MHz */
|
||||
writel(pllout2 / 48000000 - 1, &cpm->uhccdr);
|
||||
|
||||
nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
|
||||
plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
|
||||
(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
|
||||
(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
|
||||
(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
|
||||
CPM_CPPCR_PLLEN; /* enable PLL */
|
||||
|
||||
/* init PLL */
|
||||
writel(cfcr, &cpm->cpccr);
|
||||
writel(plcr1, &cpm->cppcr);
|
||||
}
|
||||
|
||||
void sdram_init(void)
|
||||
{
|
||||
struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
|
||||
|
||||
register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
|
||||
|
||||
unsigned int cas_latency_sdmr[2] = {
|
||||
EMC_SDMR_CAS_2,
|
||||
EMC_SDMR_CAS_3,
|
||||
};
|
||||
|
||||
unsigned int cas_latency_dmcr[2] = {
|
||||
1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
|
||||
2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
|
||||
};
|
||||
|
||||
int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
|
||||
|
||||
cpu_clk = CONFIG_SYS_CPU_SPEED;
|
||||
mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
|
||||
|
||||
writel(0, &emc->bcr); /* Disable bus release */
|
||||
writew(0, &emc->rtcsr); /* Disable clock for counting */
|
||||
|
||||
/* Fault DMCR value for mode register setting*/
|
||||
#define SDRAM_ROW0 11
|
||||
#define SDRAM_COL0 8
|
||||
#define SDRAM_BANK40 0
|
||||
|
||||
dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
|
||||
((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
|
||||
(SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
|
||||
(SDRAM_BW16 << EMC_DMCR_BW_BIT) |
|
||||
EMC_DMCR_EPIN |
|
||||
cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
|
||||
|
||||
/* Basic DMCR value */
|
||||
dmcr = ((SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
|
||||
((SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
|
||||
(SDRAM_BANK4 << EMC_DMCR_BA_BIT) |
|
||||
(SDRAM_BW16 << EMC_DMCR_BW_BIT) |
|
||||
EMC_DMCR_EPIN |
|
||||
cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
|
||||
|
||||
/* SDRAM timimg */
|
||||
ns = 1000000000 / mem_clk;
|
||||
tmp = SDRAM_TRAS / ns;
|
||||
if (tmp < 4)
|
||||
tmp = 4;
|
||||
if (tmp > 11)
|
||||
tmp = 11;
|
||||
dmcr |= (tmp - 4) << EMC_DMCR_TRAS_BIT;
|
||||
tmp = SDRAM_RCD / ns;
|
||||
|
||||
if (tmp > 3)
|
||||
tmp = 3;
|
||||
dmcr |= tmp << EMC_DMCR_RCD_BIT;
|
||||
tmp = SDRAM_TPC / ns;
|
||||
|
||||
if (tmp > 7)
|
||||
tmp = 7;
|
||||
dmcr |= tmp << EMC_DMCR_TPC_BIT;
|
||||
tmp = SDRAM_TRWL / ns;
|
||||
|
||||
if (tmp > 3)
|
||||
tmp = 3;
|
||||
dmcr |= tmp << EMC_DMCR_TRWL_BIT;
|
||||
tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
|
||||
|
||||
if (tmp > 14)
|
||||
tmp = 14;
|
||||
dmcr |= ((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT;
|
||||
|
||||
/* SDRAM mode value */
|
||||
sdmode = EMC_SDMR_BT_SEQ |
|
||||
EMC_SDMR_OM_NORMAL |
|
||||
EMC_SDMR_BL_4 |
|
||||
cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
|
||||
|
||||
/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
|
||||
writel(dmcr, &emc->dmcr);
|
||||
writeb(0, JZ4740_EMC_SDMR0 | sdmode);
|
||||
|
||||
/* Wait for precharge, > 200us */
|
||||
tmp = (cpu_clk / 1000000) * 1000;
|
||||
while (tmp--)
|
||||
;
|
||||
|
||||
/* Stage 2. Enable auto-refresh */
|
||||
writel(dmcr | EMC_DMCR_RFSH, &emc->dmcr);
|
||||
|
||||
tmp = SDRAM_TREF / ns;
|
||||
tmp = tmp / 64 + 1;
|
||||
if (tmp > 0xff)
|
||||
tmp = 0xff;
|
||||
writew(tmp, &emc->rtcor);
|
||||
writew(0, &emc->rtcnt);
|
||||
/* Divisor is 64, CKO/64 */
|
||||
writew(EMC_RTCSR_CKS_64, &emc->rtcsr);
|
||||
|
||||
/* Wait for number of auto-refresh cycles */
|
||||
tmp = (cpu_clk / 1000000) * 1000;
|
||||
while (tmp--)
|
||||
;
|
||||
|
||||
/* Stage 3. Mode Register Set */
|
||||
writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
|
||||
writeb(0, JZ4740_EMC_SDMR0 | sdmode);
|
||||
|
||||
/* Set back to basic DMCR value */
|
||||
writel(dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
|
||||
|
||||
/* everything is ok now */
|
||||
}
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void calc_clocks(void)
|
||||
{
|
||||
unsigned int pllout;
|
||||
unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
|
||||
|
||||
pllout = __cpm_get_pllout();
|
||||
|
||||
gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
|
||||
gd->arch.sys_clk = pllout / div[__cpm_get_hdiv()];
|
||||
gd->arch.per_clk = pllout / div[__cpm_get_pdiv()];
|
||||
gd->mem_clk = pllout / div[__cpm_get_mdiv()];
|
||||
gd->arch.dev_clk = CONFIG_SYS_EXTAL;
|
||||
}
|
||||
|
||||
void rtc_init(void)
|
||||
{
|
||||
struct jz4740_rtc *rtc = (struct jz4740_rtc *)JZ4740_RTC_BASE;
|
||||
|
||||
while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
|
||||
;
|
||||
writel(readl(&rtc->rcr) | RTC_RCR_AE, &rtc->rcr); /* enable alarm */
|
||||
|
||||
while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
|
||||
;
|
||||
writel(0x00007fff, &rtc->rgr); /* type value */
|
||||
|
||||
while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
|
||||
;
|
||||
writel(0x0000ffe0, &rtc->hwfcr); /* Power on delay 2s */
|
||||
|
||||
while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
|
||||
;
|
||||
writel(0x00000fe0, &rtc->hrcr); /* reset delay 125ms */
|
||||
}
|
||||
|
||||
/* U-Boot common routines */
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
|
||||
u32 dmcr;
|
||||
u32 rows, cols, dw, banks;
|
||||
ulong size;
|
||||
|
||||
dmcr = readl(&emc->dmcr);
|
||||
rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
|
||||
cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
|
||||
dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
|
||||
banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
|
||||
|
||||
size = (1 << (rows + cols)) * dw * banks;
|
||||
|
||||
return size;
|
||||
}
|
|
@ -1,118 +0,0 @@
|
|||
/*
|
||||
* Jz4740 UART support
|
||||
* Copyright (c) 2011
|
||||
* Qi Hardware, Xiangfu Liu <xiangfu@sharism.cc>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/jz4740.h>
|
||||
#include <serial.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
/*
|
||||
* serial_init - initialize a channel
|
||||
*
|
||||
* This routine initializes the number of data bits, parity
|
||||
* and set the selected baud rate. Interrupts are disabled.
|
||||
* Set the modem control signals if the option is selected.
|
||||
*
|
||||
* RETURNS: N/A
|
||||
*/
|
||||
struct jz4740_uart *uart = (struct jz4740_uart *)CONFIG_SYS_UART_BASE;
|
||||
|
||||
static int jz_serial_init(void)
|
||||
{
|
||||
/* Disable port interrupts while changing hardware */
|
||||
writeb(0, &uart->dlhr_ier);
|
||||
|
||||
/* Disable UART unit function */
|
||||
writeb(~UART_FCR_UUE, &uart->iir_fcr);
|
||||
|
||||
/* Set both receiver and transmitter in UART mode (not SIR) */
|
||||
writeb(~(SIRCR_RSIRE | SIRCR_TSIRE), &uart->isr);
|
||||
|
||||
/*
|
||||
* Set databits, stopbits and parity.
|
||||
* (8-bit data, 1 stopbit, no parity)
|
||||
*/
|
||||
writeb(UART_LCR_WLEN_8 | UART_LCR_STOP_1, &uart->lcr);
|
||||
|
||||
/* Set baud rate */
|
||||
serial_setbrg();
|
||||
|
||||
/* Enable UART unit, enable and clear FIFO */
|
||||
writeb(UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS,
|
||||
&uart->iir_fcr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void jz_serial_setbrg(void)
|
||||
{
|
||||
u32 baud_div, tmp;
|
||||
|
||||
baud_div = CONFIG_SYS_EXTAL / 16 / CONFIG_BAUDRATE;
|
||||
|
||||
tmp = readb(&uart->lcr);
|
||||
tmp |= UART_LCR_DLAB;
|
||||
writeb(tmp, &uart->lcr);
|
||||
|
||||
writeb((baud_div >> 8) & 0xff, &uart->dlhr_ier);
|
||||
writeb(baud_div & 0xff, &uart->rbr_thr_dllr);
|
||||
|
||||
tmp &= ~UART_LCR_DLAB;
|
||||
writeb(tmp, &uart->lcr);
|
||||
}
|
||||
|
||||
static int jz_serial_tstc(void)
|
||||
{
|
||||
if (readb(&uart->lsr) & UART_LSR_DR)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void jz_serial_putc(const char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
serial_putc('\r');
|
||||
|
||||
/* Wait for fifo to shift out some bytes */
|
||||
while (!((readb(&uart->lsr) & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60))
|
||||
;
|
||||
|
||||
writeb((u8)c, &uart->rbr_thr_dllr);
|
||||
}
|
||||
|
||||
static int jz_serial_getc(void)
|
||||
{
|
||||
while (!serial_tstc())
|
||||
;
|
||||
|
||||
return readb(&uart->rbr_thr_dllr);
|
||||
}
|
||||
|
||||
static struct serial_device jz_serial_drv = {
|
||||
.name = "jz_serial",
|
||||
.start = jz_serial_init,
|
||||
.stop = NULL,
|
||||
.setbrg = jz_serial_setbrg,
|
||||
.putc = jz_serial_putc,
|
||||
.puts = default_serial_puts,
|
||||
.getc = jz_serial_getc,
|
||||
.tstc = jz_serial_tstc,
|
||||
};
|
||||
|
||||
void jz_serial_initialize(void)
|
||||
{
|
||||
serial_register(&jz_serial_drv);
|
||||
}
|
||||
|
||||
__weak struct serial_device *default_serial_console(void)
|
||||
{
|
||||
return &jz_serial_drv;
|
||||
}
|
|
@ -1,179 +0,0 @@
|
|||
/*
|
||||
* Startup Code for MIPS32 XBURST CPU-core
|
||||
*
|
||||
* Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/cacheops.h>
|
||||
|
||||
.set noreorder
|
||||
|
||||
.globl _start
|
||||
.text
|
||||
_start:
|
||||
/* Initialize $gp */
|
||||
bal 1f
|
||||
nop
|
||||
.word _gp
|
||||
1:
|
||||
lw gp, 0(ra)
|
||||
|
||||
/* Set up temporary stack */
|
||||
li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
|
||||
|
||||
la t9, board_init_f
|
||||
jr t9
|
||||
nop
|
||||
|
||||
/*
|
||||
* void relocate_code (addr_sp, gd, addr_moni)
|
||||
*
|
||||
* This "function" does not return, instead it continues in RAM
|
||||
* after relocating the monitor code.
|
||||
*
|
||||
* a0 = addr_sp
|
||||
* a1 = gd
|
||||
* a2 = destination address
|
||||
*/
|
||||
.globl relocate_code
|
||||
.ent relocate_code
|
||||
relocate_code:
|
||||
move sp, a0 # set new stack pointer
|
||||
|
||||
move s0, a1 # save gd in s0
|
||||
move s2, a2 # save destination address in s2
|
||||
|
||||
li t0, CONFIG_SYS_MONITOR_BASE
|
||||
sub s1, s2, t0 # s1 <-- relocation offset
|
||||
|
||||
la t3, in_ram
|
||||
lw t2, -12(t3) # t2 <-- __image_copy_end
|
||||
move t1, a2
|
||||
|
||||
add gp, s1 # adjust gp
|
||||
|
||||
/*
|
||||
* t0 = source address
|
||||
* t1 = target address
|
||||
* t2 = source end address
|
||||
*/
|
||||
1:
|
||||
lw t3, 0(t0)
|
||||
sw t3, 0(t1)
|
||||
addu t0, 4
|
||||
blt t0, t2, 1b
|
||||
addu t1, 4
|
||||
|
||||
/* If caches were enabled, we would have to flush them here. */
|
||||
|
||||
/* flush d-cache */
|
||||
li t0, KSEG0
|
||||
addi t1, t0, CONFIG_SYS_DCACHE_SIZE
|
||||
2:
|
||||
cache INDEX_WRITEBACK_INV_D, 0(t0)
|
||||
bne t0, t1, 2b
|
||||
addi t0, CONFIG_SYS_CACHELINE_SIZE
|
||||
|
||||
sync
|
||||
|
||||
/* flush i-cache */
|
||||
li t0, KSEG0
|
||||
addi t1, t0, CONFIG_SYS_ICACHE_SIZE
|
||||
3:
|
||||
cache INDEX_INVALIDATE_I, 0(t0)
|
||||
bne t0, t1, 3b
|
||||
addi t0, CONFIG_SYS_CACHELINE_SIZE
|
||||
|
||||
/* Invalidate BTB */
|
||||
mfc0 t0, CP0_CONFIG, 7
|
||||
nop
|
||||
ori t0, 2
|
||||
mtc0 t0, CP0_CONFIG, 7
|
||||
nop
|
||||
|
||||
/* Jump to where we've relocated ourselves */
|
||||
addi t0, s2, in_ram - _start
|
||||
jr t0
|
||||
nop
|
||||
|
||||
.word __rel_dyn_end
|
||||
.word __rel_dyn_start
|
||||
.word __image_copy_end
|
||||
.word _GLOBAL_OFFSET_TABLE_
|
||||
.word num_got_entries
|
||||
|
||||
in_ram:
|
||||
/*
|
||||
* Now we want to update GOT.
|
||||
*
|
||||
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
|
||||
* generated by GNU ld. Skip these reserved entries from relocation.
|
||||
*/
|
||||
lw t3, -4(t0) # t3 <-- num_got_entries
|
||||
lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
|
||||
add t8, s1 # t8 now holds relocated _G_O_T_
|
||||
addi t8, t8, 8 # skipping first two entries
|
||||
li t2, 2
|
||||
1:
|
||||
lw t1, 0(t8)
|
||||
beqz t1, 2f
|
||||
add t1, s1
|
||||
sw t1, 0(t8)
|
||||
2:
|
||||
addi t2, 1
|
||||
blt t2, t3, 1b
|
||||
addi t8, 4
|
||||
|
||||
/* Update dynamic relocations */
|
||||
lw t1, -16(t0) # t1 <-- __rel_dyn_start
|
||||
lw t2, -20(t0) # t2 <-- __rel_dyn_end
|
||||
|
||||
b 2f # skip first reserved entry
|
||||
addi t1, 8
|
||||
|
||||
1:
|
||||
lw t8, -4(t1) # t8 <-- relocation info
|
||||
|
||||
li t3, 3
|
||||
bne t8, t3, 2f # skip non R_MIPS_REL32 entries
|
||||
nop
|
||||
|
||||
lw t3, -8(t1) # t3 <-- location to fix up in FLASH
|
||||
|
||||
lw t8, 0(t3) # t8 <-- original pointer
|
||||
add t8, s1 # t8 <-- adjusted pointer
|
||||
|
||||
add t3, s1 # t3 <-- location to fix up in RAM
|
||||
sw t8, 0(t3)
|
||||
|
||||
2:
|
||||
blt t1, t2, 1b
|
||||
addi t1, 8 # each rel.dyn entry is 8 bytes
|
||||
|
||||
/*
|
||||
* Clear BSS
|
||||
*
|
||||
* GOT is now relocated. Thus __bss_start and __bss_end can be
|
||||
* accessed directly via $gp.
|
||||
*/
|
||||
la t1, __bss_start # t1 <-- __bss_start
|
||||
la t2, __bss_end # t2 <-- __bss_end
|
||||
|
||||
1:
|
||||
sw zero, 0(t1)
|
||||
blt t1, t2, 1b
|
||||
addi t1, 4
|
||||
|
||||
move a0, s0 # a0 <-- gd
|
||||
la t9, board_init_r
|
||||
jr t9
|
||||
move a1, s2
|
||||
|
||||
.end relocate_code
|
|
@ -1,149 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2006
|
||||
* Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <asm/jz4740.h>
|
||||
|
||||
#define TIMER_CHAN 0
|
||||
#define TIMER_FDATA 0xffff /* Timer full data value */
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
|
||||
|
||||
void reset_timer_masked(void)
|
||||
{
|
||||
/* reset time */
|
||||
gd->arch.lastinc = readl(&tcu->tcnt0);
|
||||
gd->arch.tbl = 0;
|
||||
}
|
||||
|
||||
ulong get_timer_masked(void)
|
||||
{
|
||||
ulong now = readl(&tcu->tcnt0);
|
||||
|
||||
if (gd->arch.lastinc <= now)
|
||||
gd->arch.tbl += now - gd->arch.lastinc; /* normal mode */
|
||||
else {
|
||||
/* we have an overflow ... */
|
||||
gd->arch.tbl += TIMER_FDATA + now - gd->arch.lastinc;
|
||||
}
|
||||
|
||||
gd->arch.lastinc = now;
|
||||
|
||||
return gd->arch.tbl;
|
||||
}
|
||||
|
||||
void udelay_masked(unsigned long usec)
|
||||
{
|
||||
ulong tmo;
|
||||
ulong endtime;
|
||||
signed long diff;
|
||||
|
||||
/* normalize */
|
||||
if (usec >= 1000) {
|
||||
tmo = usec / 1000;
|
||||
tmo *= CONFIG_SYS_HZ;
|
||||
tmo /= 1000;
|
||||
} else {
|
||||
if (usec > 1) {
|
||||
tmo = usec * CONFIG_SYS_HZ;
|
||||
tmo /= 1000*1000;
|
||||
} else
|
||||
tmo = 1;
|
||||
}
|
||||
|
||||
endtime = get_timer_masked() + tmo;
|
||||
|
||||
do {
|
||||
ulong now = get_timer_masked();
|
||||
diff = endtime - now;
|
||||
} while (diff >= 0);
|
||||
}
|
||||
|
||||
int timer_init(void)
|
||||
{
|
||||
writel(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);
|
||||
|
||||
writel(0, &tcu->tcnt0);
|
||||
writel(0, &tcu->tdhr0);
|
||||
writel(TIMER_FDATA, &tcu->tdfr0);
|
||||
|
||||
/* mask irqs */
|
||||
writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr);
|
||||
writel(1 << TIMER_CHAN, &tcu->tscr); /* enable timer clock */
|
||||
writeb(1 << TIMER_CHAN, &tcu->tesr); /* start counting up */
|
||||
|
||||
gd->arch.lastinc = 0;
|
||||
gd->arch.tbl = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_timer(void)
|
||||
{
|
||||
reset_timer_masked();
|
||||
}
|
||||
|
||||
ulong get_timer(ulong base)
|
||||
{
|
||||
return get_timer_masked() - base;
|
||||
}
|
||||
|
||||
void set_timer(ulong t)
|
||||
{
|
||||
gd->arch.tbl = t;
|
||||
}
|
||||
|
||||
void __udelay(unsigned long usec)
|
||||
{
|
||||
ulong tmo, tmp;
|
||||
|
||||
/* normalize */
|
||||
if (usec >= 1000) {
|
||||
tmo = usec / 1000;
|
||||
tmo *= CONFIG_SYS_HZ;
|
||||
tmo /= 1000;
|
||||
} else {
|
||||
if (usec >= 1) {
|
||||
tmo = usec * CONFIG_SYS_HZ;
|
||||
tmo /= 1000 * 1000;
|
||||
} else
|
||||
tmo = 1;
|
||||
}
|
||||
|
||||
/* check for rollover during this delay */
|
||||
tmp = get_timer(0);
|
||||
if ((tmp + tmo) < tmp)
|
||||
reset_timer_masked(); /* timer would roll over */
|
||||
else
|
||||
tmo += tmp;
|
||||
|
||||
while (get_timer_masked() < tmo)
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long).
|
||||
* On MIPS it just returns the timer value.
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
return get_timer(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On MIPS it returns the number of timer ticks per second.
|
||||
*/
|
||||
ulong get_tbclk(void)
|
||||
{
|
||||
return CONFIG_SYS_HZ;
|
||||
}
|
File diff suppressed because it is too large
Load diff
|
@ -21,5 +21,3 @@ static inline unsigned long image_copy_end(void)
|
|||
extern char __image_copy_end[];
|
||||
return (unsigned long) &__image_copy_end;
|
||||
}
|
||||
|
||||
extern int incaip_set_cpuclk(void);
|
||||
|
|
|
@ -15,6 +15,13 @@
|
|||
#ifndef _U_BOOT_H_
|
||||
#define _U_BOOT_H_ 1
|
||||
|
||||
#ifdef CONFIG_SYS_GENERIC_BOARD
|
||||
|
||||
/* Use the generic board which requires a unified bd_info */
|
||||
#include <asm-generic/u-boot.h>
|
||||
|
||||
#else /* !CONFIG_SYS_GENERIC_BOARD */
|
||||
|
||||
typedef struct bd_info {
|
||||
unsigned int bi_baudrate; /* serial console baudrate */
|
||||
unsigned long bi_arch_number; /* unique id for this board */
|
||||
|
@ -26,6 +33,8 @@ typedef struct bd_info {
|
|||
unsigned long bi_flashoffset; /* reserved area for startup monitor */
|
||||
} bd_t;
|
||||
|
||||
#endif /* !CONFIG_SYS_GENERIC_BOARD */
|
||||
|
||||
/* For image.h:image_check_target_arch() */
|
||||
#define IH_ARCH_DEFAULT IH_ARCH_MIPS
|
||||
|
||||
|
|
|
@ -5,7 +5,11 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifndef CONFIG_SYS_GENERIC_BOARD
|
||||
obj-y += board.o
|
||||
endif
|
||||
obj-y += io.o
|
||||
|
||||
obj-$(CONFIG_CMD_BOOTM) += bootm.o
|
||||
|
||||
lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o
|
||||
|
|
|
@ -27,12 +27,6 @@ ulong monitor_flash_len;
|
|||
|
||||
static char *failed = "*** failed ***\n";
|
||||
|
||||
/*
|
||||
* mips_io_port_base is the begin of the address space to which x86 style
|
||||
* I/O ports are mapped.
|
||||
*/
|
||||
const unsigned long mips_io_port_base = -1;
|
||||
|
||||
int __board_early_init_f(void)
|
||||
{
|
||||
/*
|
||||
|
@ -109,9 +103,6 @@ init_fnc_t *init_sequence[] = {
|
|||
board_early_init_f,
|
||||
timer_init,
|
||||
env_init, /* initialize environment */
|
||||
#ifdef CONFIG_INCA_IP
|
||||
incaip_set_cpuclk, /* set cpu clock according to env. variable */
|
||||
#endif
|
||||
init_baudrate, /* initialize baudrate settings */
|
||||
serial_init, /* serial communications setup */
|
||||
console_init_f,
|
||||
|
|
12
arch/mips/lib/io.c
Normal file
12
arch/mips/lib/io.c
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* mips_io_port_base is the begin of the address space to which x86 style
|
||||
* I/O ports are mapped.
|
||||
*/
|
||||
const unsigned long mips_io_port_base = -1;
|
|
@ -46,8 +46,6 @@
|
|||
void
|
||||
cpu_init_f (void)
|
||||
{
|
||||
/* MOUSSE board is initialized in asm */
|
||||
#if !defined(CONFIG_MOUSSE)
|
||||
register unsigned long val;
|
||||
CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
|
||||
/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
|
||||
|
@ -302,98 +300,12 @@ cpu_init_f (void)
|
|||
CONFIG_READ_WORD(MCCR1, val);
|
||||
CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
|
||||
__asm__ __volatile__("eieio");
|
||||
|
||||
#endif /* !CONFIG_MOUSSE */
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_MOUSSE
|
||||
#ifdef INCLUDE_MPC107_REPORT
|
||||
struct MPC107_s {
|
||||
unsigned int iobase;
|
||||
char desc[120];
|
||||
} MPC107Regs[] = {
|
||||
{ BMC_BASE + 0x00, "MPC107 Vendor/Device ID" },
|
||||
{ BMC_BASE + 0x04, "MPC107 PCI Command/Status Register" },
|
||||
{ BMC_BASE + 0x08, "MPC107 Revision" },
|
||||
{ BMC_BASE + 0x0C, "MPC107 Cache Line Size" },
|
||||
{ BMC_BASE + 0x10, "MPC107 LMBAR" },
|
||||
{ BMC_BASE + 0x14, "MPC824x PCSR" },
|
||||
{ BMC_BASE + 0xA8, "MPC824x PICR1" },
|
||||
{ BMC_BASE + 0xAC, "MPC824x PICR2" },
|
||||
{ BMC_BASE + 0x46, "MPC824x PACR" },
|
||||
{ BMC_BASE + 0x310, "MPC824x ITWR" },
|
||||
{ BMC_BASE + 0x300, "MPC824x OMBAR" },
|
||||
{ BMC_BASE + 0x308, "MPC824x OTWR" },
|
||||
{ BMC_BASE + 0x14, "MPC107 Peripheral Control and Status Register" },
|
||||
{ BMC_BASE + 0x78, "MPC107 EUMBAR" },
|
||||
{ BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status" },
|
||||
{ BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status" },
|
||||
{ BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address" },
|
||||
{ BMC_BASE + 0xE0, "MPC107 AMBOR Register" },
|
||||
{ BMC_BASE + 0xF0, "MPC107 MCCR1 Register" },
|
||||
{ BMC_BASE + 0xF4, "MPC107 MCCR2 Register" },
|
||||
{ BMC_BASE + 0xF8, "MPC107 MCCR3 Register" },
|
||||
{ BMC_BASE + 0xFC, "MPC107 MCCR4 Register" },
|
||||
};
|
||||
#define N_MPC107_Regs (sizeof(MPC107Regs)/sizeof(MPC107Regs[0]))
|
||||
#endif /* INCLUDE_MPC107_REPORT */
|
||||
#endif /* CONFIG_MOUSSE */
|
||||
|
||||
/*
|
||||
* initialize higher level parts of CPU like time base and timers
|
||||
*/
|
||||
int cpu_init_r (void)
|
||||
{
|
||||
#ifdef CONFIG_MOUSSE
|
||||
#ifdef INCLUDE_MPC107_REPORT
|
||||
unsigned int tmp = 0, i;
|
||||
#endif
|
||||
/*
|
||||
* Initialize the EUMBBAR (Embedded Util Mem Block Base Addr Reg).
|
||||
* This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can
|
||||
* be accessed.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_MPC8240 /* only on MPC8240 */
|
||||
mpc824x_mpc107_setreg (EUMBBAR, EUMBBAR_VAL);
|
||||
/* MOT/SPS: Issue #10002, PCI (FD Alias enable) */
|
||||
mpc824x_mpc107_setreg (AMBOR, 0x000000C0);
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef INCLUDE_MPC107_REPORT
|
||||
/* Check MPC824x PCI Device and Vendor ID */
|
||||
while ((tmp = mpc824x_mpc107_getreg (BMC_BASE)) != 0x31057) {
|
||||
printf (" MPC107: offset=0x%x, val = 0x%x\n",
|
||||
BMC_BASE,
|
||||
tmp);
|
||||
}
|
||||
|
||||
for (i = 0; i < N_MPC107_Regs; i++) {
|
||||
printf (" 0x%x/%s = 0x%x\n",
|
||||
MPC107Regs[i].iobase,
|
||||
MPC107Regs[i].desc,
|
||||
mpc824x_mpc107_getreg (MPC107Regs[i].iobase));
|
||||
}
|
||||
|
||||
printf ("IBAT0L = 0x%08X\n", mfspr (IBAT0L));
|
||||
printf ("IBAT0U = 0x%08X\n", mfspr (IBAT0U));
|
||||
printf ("IBAT1L = 0x%08X\n", mfspr (IBAT1L));
|
||||
printf ("IBAT1U = 0x%08X\n", mfspr (IBAT1U));
|
||||
printf ("IBAT2L = 0x%08X\n", mfspr (IBAT2L));
|
||||
printf ("IBAT2U = 0x%08X\n", mfspr (IBAT2U));
|
||||
printf ("IBAT3L = 0x%08X\n", mfspr (IBAT3L));
|
||||
printf ("IBAT3U = 0x%08X\n", mfspr (IBAT3U));
|
||||
printf ("DBAT0L = 0x%08X\n", mfspr (DBAT0L));
|
||||
printf ("DBAT0U = 0x%08X\n", mfspr (DBAT0U));
|
||||
printf ("DBAT1L = 0x%08X\n", mfspr (DBAT1L));
|
||||
printf ("DBAT1U = 0x%08X\n", mfspr (DBAT1U));
|
||||
printf ("DBAT2L = 0x%08X\n", mfspr (DBAT2L));
|
||||
printf ("DBAT2U = 0x%08X\n", mfspr (DBAT2U));
|
||||
printf ("DBAT3L = 0x%08X\n", mfspr (DBAT3L));
|
||||
printf ("DBAT3U = 0x%08X\n", mfspr (DBAT3U));
|
||||
#endif /* INCLUDE_MPC107_REPORT */
|
||||
#endif /* CONFIG_MOUSSE */
|
||||
return (0);
|
||||
}
|
||||
|
|
|
@ -19,7 +19,7 @@
|
|||
#include <tsec.h>
|
||||
#include <netdev.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#ifdef CONFIG_BOOTCOUNT_LIMIT
|
||||
#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
|
||||
#include <asm/immap_qe.h>
|
||||
#include <asm/io.h>
|
||||
#endif
|
||||
|
|
|
@ -17,7 +17,7 @@ extern void ft_qe_setup(void *blob);
|
|||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
|
||||
(defined(CONFIG_QE))
|
||||
(defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
|
||||
#include <asm/immap_qe.h>
|
||||
|
||||
void fdt_fixup_muram (void *blob)
|
||||
|
@ -124,7 +124,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
|
|||
|
||||
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
|
||||
|
||||
#if defined(CONFIG_BOOTCOUNT_LIMIT)
|
||||
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
|
||||
(defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
|
||||
fdt_fixup_muram (blob);
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -102,7 +102,9 @@ obj-y += cpu.o
|
|||
obj-y += cpu_init.o
|
||||
obj-y += cpu_init_early.o
|
||||
obj-y += interrupts.o
|
||||
ifneq ($(CONFIG_QEMU_E500),y)
|
||||
obj-y += speed.o
|
||||
endif
|
||||
obj-y += tlb.o
|
||||
obj-y += traps.o
|
||||
|
||||
|
|
|
@ -113,6 +113,21 @@ static void check_erratum_a4580(uint32_t svr)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
|
||||
/*
|
||||
* This workaround can be implemented in PBI, or by u-boot.
|
||||
*/
|
||||
static void check_erratum_a007212(void)
|
||||
{
|
||||
u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
|
||||
|
||||
if (in_be32(plldgdcr) & 0x1fe) {
|
||||
/* check if PLL ratio is set by workaround */
|
||||
puts("Work-around for Erratum A007212 enabled\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
|
||||
|
@ -268,6 +283,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|||
#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
puts("Work-around for Erratum A005125 enabled\n");
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A007075
|
||||
if (has_erratum_a007075())
|
||||
puts("Work-around for Erratum A007075 enabled\n");
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
||||
if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
|
||||
(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
|
||||
|
@ -277,6 +296,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|||
if (has_erratum_a006261())
|
||||
puts("Work-around for Erratum A006261 enabled\n");
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
|
||||
check_erratum_a007212();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -130,6 +130,11 @@ int checkcpu (void)
|
|||
|
||||
get_sys_info(&sysinfo);
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
|
||||
if (sysinfo.diff_sysclk == 1)
|
||||
puts("Single Source Clock Configuration\n");
|
||||
#endif
|
||||
|
||||
puts("Clock Configuration:");
|
||||
for_each_cpu(i, core, nr_cores, mask) {
|
||||
if (!(i & 3))
|
||||
|
@ -272,7 +277,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|||
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 8
|
||||
#endif
|
||||
unsigned long get_tbclk (void)
|
||||
__weak unsigned long get_tbclk (void)
|
||||
{
|
||||
unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
|
||||
|
||||
|
@ -338,7 +343,8 @@ void mpc85xx_reginfo(void)
|
|||
!defined(CONFIG_SYS_INIT_L2_ADDR)
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
|
||||
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
|
||||
defined(CONFIG_QEMU_E500)
|
||||
return fsl_ddr_sdram_size();
|
||||
#else
|
||||
return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
|
||||
|
|
|
@ -33,9 +33,35 @@
|
|||
#endif
|
||||
|
||||
#include "../../../../drivers/block/fsl_sata.h"
|
||||
#ifdef CONFIG_U_QE
|
||||
#include "../../../../drivers/qe/qe.h"
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
|
||||
/*
|
||||
* For deriving usb clock from 100MHz sysclk, reference divisor is set
|
||||
* to a value of 5, which gives an intermediate value 20(100/5). The
|
||||
* multiplication factor integer is set to 24, which when multiplied to
|
||||
* above intermediate value provides clock for usb ip.
|
||||
*/
|
||||
void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
|
||||
{
|
||||
sys_info_t sysinfo;
|
||||
|
||||
get_sys_info(&sysinfo);
|
||||
if (sysinfo.diff_sysclk == 1) {
|
||||
clrbits_be32(&usb_phy->pllprg[1],
|
||||
CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
|
||||
setbits_be32(&usb_phy->pllprg[1],
|
||||
CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
|
||||
CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
|
||||
CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
|
||||
{
|
||||
|
@ -84,7 +110,7 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
|
|||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_QE
|
||||
#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
|
||||
extern qe_iop_conf_t qe_iop_conf_tab[];
|
||||
extern void qe_config_iopin(u8 port, u8 pin, int dir,
|
||||
int open_drain, int assign);
|
||||
|
@ -173,17 +199,14 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_CPC
|
||||
static void enable_cpc(void)
|
||||
#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
|
||||
static void disable_cpc_sram(void)
|
||||
{
|
||||
int i;
|
||||
u32 size = 0;
|
||||
|
||||
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
|
||||
u32 cpccfg0 = in_be32(&cpc->cpccfg0);
|
||||
size += CPC_CFG0_SZ_K(cpccfg0);
|
||||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
|
||||
/* find and disable LAW of SRAM */
|
||||
struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
|
||||
|
@ -198,8 +221,21 @@ static void enable_cpc(void)
|
|||
out_be32(&cpc->cpccsr0, 0);
|
||||
out_be32(&cpc->cpcsrcr0, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void enable_cpc(void)
|
||||
{
|
||||
int i;
|
||||
u32 size = 0;
|
||||
|
||||
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
|
||||
u32 cpccfg0 = in_be32(&cpc->cpccfg0);
|
||||
size += CPC_CFG0_SZ_K(cpccfg0);
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
|
||||
setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
|
||||
#endif
|
||||
|
@ -267,11 +303,77 @@ static void corenet_tb_init(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
|
||||
void fsl_erratum_a007212_workaround(void)
|
||||
{
|
||||
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 ddr_pll_ratio;
|
||||
u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
|
||||
u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
|
||||
u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
|
||||
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
|
||||
u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
|
||||
u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
|
||||
#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
|
||||
u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
|
||||
u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
|
||||
#endif
|
||||
#endif
|
||||
/*
|
||||
* Even this workaround applies to selected version of SoCs, it is
|
||||
* safe to apply to all versions, with the limitation of odd ratios.
|
||||
* If RCW has disabled DDR PLL, we have to apply this workaround,
|
||||
* otherwise DDR will not work.
|
||||
*/
|
||||
ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
|
||||
FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
|
||||
FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
|
||||
/* check if RCW sets ratio to 0, required by this workaround */
|
||||
if (ddr_pll_ratio != 0)
|
||||
return;
|
||||
ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
|
||||
FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
|
||||
FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
|
||||
/* check if reserved bits have the desired ratio */
|
||||
if (ddr_pll_ratio == 0) {
|
||||
printf("Error: Unknown DDR PLL ratio!\n");
|
||||
return;
|
||||
}
|
||||
ddr_pll_ratio >>= 1;
|
||||
|
||||
setbits_be32(plldadcr1, 0x02000001);
|
||||
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
|
||||
setbits_be32(plldadcr2, 0x02000001);
|
||||
#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
|
||||
setbits_be32(plldadcr3, 0x02000001);
|
||||
#endif
|
||||
#endif
|
||||
setbits_be32(dpdovrcr4, 0xe0000000);
|
||||
out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
|
||||
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
|
||||
out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
|
||||
#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
|
||||
out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
|
||||
#endif
|
||||
#endif
|
||||
udelay(100);
|
||||
clrbits_be32(plldadcr1, 0x02000001);
|
||||
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
|
||||
clrbits_be32(plldadcr2, 0x02000001);
|
||||
#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
|
||||
clrbits_be32(plldadcr3, 0x02000001);
|
||||
#endif
|
||||
#endif
|
||||
clrbits_be32(dpdovrcr4, 0xe0000000);
|
||||
}
|
||||
#endif
|
||||
|
||||
void cpu_init_f (void)
|
||||
{
|
||||
extern void m8560_cpm_reset (void);
|
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
|
||||
#endif
|
||||
#if defined(CONFIG_SECURE_BOOT)
|
||||
struct law_entry law;
|
||||
|
@ -298,6 +400,10 @@ void cpu_init_f (void)
|
|||
law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
|
||||
if (law.index != -1)
|
||||
disable_law(law.index);
|
||||
|
||||
#if defined(CONFIG_SYS_CPC_REINIT_F)
|
||||
disable_cpc_sram();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPM2
|
||||
|
@ -309,10 +415,12 @@ void cpu_init_f (void)
|
|||
#if defined(CONFIG_CPM2)
|
||||
m8560_cpm_reset();
|
||||
#endif
|
||||
#ifdef CONFIG_QE
|
||||
|
||||
#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
|
||||
/* Config QE ioports */
|
||||
config_qe_ioports();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FSL_DMA)
|
||||
dma_init();
|
||||
#endif
|
||||
|
@ -330,6 +438,17 @@ void cpu_init_f (void)
|
|||
in_be32(&gur->dcsrcr);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS
|
||||
#ifdef CONFIG_DEEP_SLEEP
|
||||
/* disable the console if boot from deep sleep */
|
||||
if (in_be32(&gur->scrtsr[0]) & (1 << 3))
|
||||
gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
|
||||
#endif
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
|
||||
fsl_erratum_a007212_workaround();
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/* Implement a dummy function for those platforms w/o SERDES */
|
||||
|
@ -598,6 +717,9 @@ skip_l2:
|
|||
puts("disabled\n");
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RAMBOOT_PBL)
|
||||
disable_cpc_sram();
|
||||
#endif
|
||||
enable_cpc();
|
||||
|
||||
#ifndef CONFIG_SYS_FSL_NO_SERDES
|
||||
|
@ -716,6 +838,9 @@ skip_l2:
|
|||
CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
|
||||
CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
|
||||
CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
|
||||
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
|
||||
usb_single_source_clk_configure(usb_phy);
|
||||
#endif
|
||||
setbits_be32(&usb_phy->port1.ctrl,
|
||||
CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
|
||||
setbits_be32(&usb_phy->port1.drvvbuscfg,
|
||||
|
@ -767,8 +892,6 @@ skip_l2:
|
|||
return 0;
|
||||
}
|
||||
|
||||
extern void setup_ivors(void);
|
||||
|
||||
void arch_preboot_os(void)
|
||||
{
|
||||
u32 msr;
|
||||
|
@ -781,8 +904,6 @@ void arch_preboot_os(void)
|
|||
msr = mfmsr();
|
||||
msr &= ~(MSR_ME|MSR_CE);
|
||||
mtmsr(msr);
|
||||
|
||||
setup_ivors();
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
|
||||
|
@ -797,21 +918,13 @@ int sata_initialize(void)
|
|||
|
||||
void cpu_secondary_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_QE
|
||||
#ifdef CONFIG_U_QE
|
||||
uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
|
||||
#elif defined CONFIG_QE
|
||||
uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
|
||||
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
|
||||
int ret;
|
||||
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
|
||||
|
||||
/* load QE firmware from NAND flash to DDR first */
|
||||
ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
|
||||
&fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
|
||||
|
||||
if (ret && ret == -EUCLEAN) {
|
||||
printf ("NAND read for QE firmware at offset %x failed %d\n",
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_QE
|
||||
qe_init(qe_base);
|
||||
qe_reset();
|
||||
#endif
|
||||
|
|
|
@ -79,7 +79,7 @@ void setup_ifc(void)
|
|||
#endif
|
||||
|
||||
/* We run cpu_init_early_f in AS = 1 */
|
||||
void cpu_init_early_f(void)
|
||||
void cpu_init_early_f(void *fdt)
|
||||
{
|
||||
u32 mas0, mas1, mas2, mas3, mas7;
|
||||
int i;
|
||||
|
@ -102,6 +102,12 @@ void cpu_init_early_f(void)
|
|||
for (i = 0; i < sizeof(gd_t); i++)
|
||||
((char *)gd)[i] = 0;
|
||||
|
||||
/*
|
||||
* CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
|
||||
* so we need to populate it before it accesses it.
|
||||
*/
|
||||
gd->fdt_blob = fdt;
|
||||
|
||||
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
|
||||
mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
|
||||
mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
|
||||
|
|
|
@ -275,12 +275,16 @@ static inline void ft_fixup_l2cache(void *blob)
|
|||
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
|
||||
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
|
||||
/* Only initialize every eighth thread */
|
||||
if (reg && !((*reg) % 8))
|
||||
#else
|
||||
if (reg)
|
||||
#endif
|
||||
if (reg && !((*reg) % 8)) {
|
||||
fdt_setprop_cell(blob, l2_off, "cache-stash-id",
|
||||
(*reg * 2) + 32 + 1);
|
||||
(*reg / 4) + 32 + 1);
|
||||
}
|
||||
#else
|
||||
if (reg) {
|
||||
fdt_setprop_cell(blob, l2_off, "cache-stash-id",
|
||||
(*reg * 2) + 32 + 1);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
|
||||
|
@ -582,6 +586,33 @@ static void fdt_fixup_usb(void *fdt)
|
|||
#define fdt_fixup_usb(x)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PPC_T1040)
|
||||
static void fdt_fixup_l2_switch(void *blob)
|
||||
{
|
||||
uchar l2swaddr[6];
|
||||
int node;
|
||||
|
||||
/* The l2switch node from device-tree has
|
||||
* compatible string "vitesse-9953" */
|
||||
node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
|
||||
if (node == -FDT_ERR_NOTFOUND)
|
||||
/* no l2switch node has been found */
|
||||
return;
|
||||
|
||||
/* Get MAC address for the l2switch from "l2switchaddr"*/
|
||||
if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr)) {
|
||||
printf("Warning: MAC address for l2switch not found\n");
|
||||
memset(l2swaddr, 0, sizeof(l2swaddr));
|
||||
}
|
||||
|
||||
/* Add MAC address to l2switch node */
|
||||
fdt_setprop(blob, node, "local-mac-address", l2swaddr,
|
||||
sizeof(l2swaddr));
|
||||
}
|
||||
#else
|
||||
#define fdt_fixup_l2_switch(x)
|
||||
#endif
|
||||
|
||||
void ft_cpu_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int off;
|
||||
|
@ -719,6 +750,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
|
|||
"clock-frequency", gd->bus_clk/2, 1);
|
||||
|
||||
fdt_fixup_usb(blob);
|
||||
|
||||
fdt_fixup_l2_switch(blob);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -1,63 +0,0 @@
|
|||
/*
|
||||
* Copyright 2009 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Kumar Gala <kumar.gala@freescale.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/* This file is intended to be included by other asm code since
|
||||
* we will want to execute this on both the primary core when
|
||||
* it does a bootm and the secondary core's that get released
|
||||
* out of the spin table */
|
||||
|
||||
#define SET_IVOR(vector_number, vector_offset) \
|
||||
li r3,vector_offset@l; \
|
||||
mtspr SPRN_IVOR##vector_number,r3;
|
||||
|
||||
#define SET_GIVOR(vector_number, vector_offset) \
|
||||
li r3,vector_offset@l; \
|
||||
mtspr SPRN_GIVOR##vector_number,r3;
|
||||
|
||||
SET_IVOR(0, 0x020) /* Critical Input */
|
||||
SET_IVOR(1, 0x000) /* Machine Check */
|
||||
SET_IVOR(2, 0x060) /* Data Storage */
|
||||
SET_IVOR(3, 0x080) /* Instruction Storage */
|
||||
SET_IVOR(4, 0x0a0) /* External Input */
|
||||
SET_IVOR(5, 0x0c0) /* Alignment */
|
||||
SET_IVOR(6, 0x0e0) /* Program */
|
||||
SET_IVOR(7, 0x100) /* FP Unavailable */
|
||||
SET_IVOR(8, 0x120) /* System Call */
|
||||
SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
|
||||
SET_IVOR(10, 0x160) /* Decrementer */
|
||||
SET_IVOR(11, 0x180) /* Fixed Interval Timer */
|
||||
SET_IVOR(12, 0x1a0) /* Watchdog Timer */
|
||||
SET_IVOR(13, 0x1c0) /* Data TLB Error */
|
||||
SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
|
||||
SET_IVOR(15, 0x040) /* Debug */
|
||||
|
||||
/* e500v1 & e500v2 only */
|
||||
#ifndef CONFIG_E500MC
|
||||
SET_IVOR(32, 0x200) /* SPE Unavailable */
|
||||
SET_IVOR(33, 0x220) /* Embedded FP Data */
|
||||
SET_IVOR(34, 0x240) /* Embedded FP Round */
|
||||
#endif
|
||||
|
||||
SET_IVOR(35, 0x260) /* Performance monitor */
|
||||
|
||||
/* e500mc only */
|
||||
#ifdef CONFIG_E500MC
|
||||
SET_IVOR(36, 0x280) /* Processor doorbell */
|
||||
SET_IVOR(37, 0x2a0) /* Processor doorbell critical */
|
||||
SET_IVOR(38, 0x2c0) /* Guest Processor doorbell */
|
||||
SET_IVOR(39, 0x2e0) /* Guest Processor critical & machine check */
|
||||
SET_IVOR(40, 0x300) /* Hypervisor system call */
|
||||
SET_IVOR(41, 0x320) /* Hypervisor Priviledge */
|
||||
|
||||
SET_GIVOR(2, 0x060) /* Guest Data Storage */
|
||||
SET_GIVOR(3, 0x080) /* Guest Instruction Storage */
|
||||
SET_GIVOR(4, 0x0a0) /* Guest External Input */
|
||||
SET_GIVOR(8, 0x120) /* Guest System Call */
|
||||
SET_GIVOR(13, 0x1c0) /* Guest Data TLB Error */
|
||||
SET_GIVOR(14, 0x1e0) /* Guest Instruction TLB Error */
|
||||
#endif
|
|
@ -12,7 +12,7 @@
|
|||
#include "asm/io.h"
|
||||
#include "asm/immap_85xx.h"
|
||||
|
||||
#if defined(CONFIG_QE)
|
||||
#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
|
||||
#define NUM_OF_PINS 32
|
||||
void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
|
||||
{
|
||||
|
|
|
@ -405,9 +405,6 @@ __second_half_boot_page:
|
|||
bne 3b
|
||||
isync
|
||||
|
||||
/* setup IVORs to match fixed offsets */
|
||||
#include "fixed_ivor.S"
|
||||
|
||||
/* get the upper bits of the addr */
|
||||
lwz r11,ENTRY_ADDR_UPPER(r10)
|
||||
|
||||
|
|
|
@ -74,28 +74,33 @@ void get_sys_info(sys_info_t *sys_info)
|
|||
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
|
||||
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
|
||||
uint mem_pll_rat;
|
||||
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
|
||||
uint single_src;
|
||||
#endif
|
||||
|
||||
sys_info->freq_systembus = sysclk;
|
||||
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
|
||||
uint ddr_refclk_sel;
|
||||
unsigned int porsr1_sys_clk;
|
||||
porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
|
||||
& FSL_DCFG_PORSR1_SYSCLK_MASK;
|
||||
if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
|
||||
sys_info->diff_sysclk = 1;
|
||||
else
|
||||
sys_info->diff_sysclk = 0;
|
||||
|
||||
/*
|
||||
* DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
|
||||
* are driven by separate DDR Refclock or single source
|
||||
* differential clock.
|
||||
*/
|
||||
single_src = (in_be32(&gur->rcwsr[5]) >>
|
||||
ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
|
||||
FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
|
||||
FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
|
||||
/*
|
||||
* For single source clocking, both ddrclock and syclock
|
||||
* For single source clocking, both ddrclock and sysclock
|
||||
* are driven by differential sysclock.
|
||||
*/
|
||||
if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
|
||||
printf("Single Source Clock Configuration\n");
|
||||
if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
|
||||
sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
|
||||
} else
|
||||
else
|
||||
#endif
|
||||
#ifdef CONFIG_DDR_CLK_FREQ
|
||||
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
|
||||
|
@ -107,6 +112,13 @@ void get_sys_info(sys_info_t *sys_info)
|
|||
mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
|
||||
FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
|
||||
& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
|
||||
if (mem_pll_rat == 0) {
|
||||
mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
|
||||
FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
|
||||
FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
|
||||
}
|
||||
#endif
|
||||
/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
|
||||
* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
|
||||
* it uses 6.
|
||||
|
@ -151,8 +163,8 @@ void get_sys_info(sys_info_t *sys_info)
|
|||
sys_info->freq_processor[cpu] =
|
||||
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
|
||||
}
|
||||
#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \
|
||||
defined(CONFIG_PPC_T2081)
|
||||
#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
|
||||
defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
|
||||
#define FM1_CLK_SEL 0xe0000000
|
||||
#define FM1_CLK_SHIFT 29
|
||||
#else
|
||||
|
@ -336,6 +348,10 @@ void get_sys_info(sys_info_t *sys_info)
|
|||
|
||||
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
|
||||
|
||||
#ifdef CONFIG_U_QE
|
||||
sys_info->freq_qe = sys_info->freq_systembus / 2;
|
||||
#endif
|
||||
|
||||
#else /* CONFIG_FSL_CORENET */
|
||||
uint plat_ratio, e500_ratio, half_freq_systembus;
|
||||
int i;
|
||||
|
|
|
@ -26,6 +26,8 @@
|
|||
#undef MSR_KERNEL
|
||||
#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
|
||||
|
||||
#define LAW_EN 0x80000000
|
||||
|
||||
#if defined(CONFIG_NAND_SPL) || \
|
||||
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
|
||||
#define MINIMAL_SPL
|
||||
|
@ -78,6 +80,13 @@ _start_e500:
|
|||
li r1,MSR_DE
|
||||
mtmsr r1
|
||||
|
||||
/*
|
||||
* If we got an ePAPR device tree pointer passed in as r3, we need that
|
||||
* later in cpu_init_early_f(). Save it to a safe register before we
|
||||
* clobber it so that we can fetch it from there later.
|
||||
*/
|
||||
mr r24, r3
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
|
||||
mfspr r3,SPRN_SVR
|
||||
rlwinm r3,r3,0,0xff
|
||||
|
@ -115,7 +124,8 @@ _start_e500:
|
|||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
|
||||
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
|
||||
!defined(CONFIG_E6500)
|
||||
/* ISBC uses L2 as stack.
|
||||
* Disable L2 cache here so that u-boot can enable it later
|
||||
* as part of it's normal flow
|
||||
|
@ -460,7 +470,8 @@ nexti: mflr r1 /* R1 = our PC */
|
|||
2: cmpw r3, r4
|
||||
blt 1b
|
||||
|
||||
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
|
||||
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
|
||||
!defined(CONFIG_SECURE_BOOT)
|
||||
/*
|
||||
* TLB entry for debuggging in AS1
|
||||
* Create temporary TLB entry in AS0 to handle debug exception
|
||||
|
@ -481,12 +492,6 @@ nexti: mflr r1 /* R1 = our PC */
|
|||
0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
|
||||
0, r6
|
||||
|
||||
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
|
||||
create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
|
||||
0, BOOKE_PAGESZ_1M, \
|
||||
CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
|
||||
CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
|
||||
0, r6
|
||||
#else
|
||||
/*
|
||||
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
|
||||
|
@ -574,7 +579,6 @@ infinite_debug_loop:
|
|||
#ifdef CONFIG_FSL_CORENET
|
||||
|
||||
#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
|
||||
#define LAW_EN 0x80000000
|
||||
#define LAW_SIZE_4K 0xb
|
||||
#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
|
||||
#define CCSRAR_C 0x80000000 /* Commit */
|
||||
|
@ -1142,6 +1146,10 @@ _start_cont:
|
|||
mr r1,r3 /* Transfer to SP(r1) */
|
||||
|
||||
GET_GOT
|
||||
|
||||
/* Pass our potential ePAPR device tree pointer to cpu_init_early_f */
|
||||
mr r3, r24
|
||||
|
||||
bl cpu_init_early_f
|
||||
|
||||
/* switch back to AS = 0 */
|
||||
|
@ -1644,6 +1652,7 @@ relocate_code:
|
|||
mr r10,r5 /* Save copy of Destination Address */
|
||||
|
||||
GET_GOT
|
||||
#ifndef CONFIG_SPL_SKIP_RELOCATE
|
||||
mr r3,r5 /* Destination Address */
|
||||
lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
|
||||
ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
|
||||
|
@ -1734,6 +1743,7 @@ relocate_code:
|
|||
|
||||
mtlr r0
|
||||
blr /* NEVER RETURNS! */
|
||||
#endif
|
||||
.globl in_ram
|
||||
in_ram:
|
||||
|
||||
|
@ -1965,10 +1975,4 @@ flush_dcache:
|
|||
isync
|
||||
|
||||
blr
|
||||
|
||||
.globl setup_ivors
|
||||
setup_ivors:
|
||||
|
||||
#include "fixed_ivor.S"
|
||||
blr
|
||||
#endif /* !MINIMAL_SPL */
|
||||
|
|
|
@ -46,6 +46,7 @@ struct liodn_id_table liodn_tbl[] = {
|
|||
SET_DMA_LIODN(2, 227),
|
||||
|
||||
/* SET_NEXUS_LIODN(557), -- not yet implemented */
|
||||
SET_QE_LIODN(559),
|
||||
};
|
||||
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
|
||||
|
||||
|
|
|
@ -24,7 +24,7 @@ void invalidate_tlb(u8 tlb)
|
|||
mtspr(MMUCSR0, 0x2);
|
||||
}
|
||||
|
||||
void init_tlbs(void)
|
||||
__weak void init_tlbs(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
@ -236,20 +236,26 @@ void init_addr_map(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
unsigned int
|
||||
setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
|
||||
uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
|
||||
enum tlb_map_type map_type)
|
||||
{
|
||||
int i;
|
||||
unsigned int tlb_size;
|
||||
unsigned int wimge = MAS2_M;
|
||||
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
|
||||
unsigned int wimge;
|
||||
unsigned int perm;
|
||||
unsigned int max_cam, tsize_mask;
|
||||
u64 size, memsize = (u64)memsize_in_meg << 20;
|
||||
|
||||
if (map_type == TLB_MAP_RAM) {
|
||||
perm = MAS3_SX|MAS3_SW|MAS3_SR;
|
||||
wimge = MAS2_M;
|
||||
#ifdef CONFIG_SYS_PPC_DDR_WIMGE
|
||||
wimge = CONFIG_SYS_PPC_DDR_WIMGE;
|
||||
wimge = CONFIG_SYS_PPC_DDR_WIMGE;
|
||||
#endif
|
||||
size = min(memsize, CONFIG_MAX_MEM_MAPPED);
|
||||
} else {
|
||||
perm = MAS3_SW|MAS3_SR;
|
||||
wimge = MAS2_I|MAS2_G;
|
||||
}
|
||||
|
||||
if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
|
||||
/* Convert (4^max) kB to (2^max) bytes */
|
||||
max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
|
||||
|
@ -261,11 +267,11 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
|
|||
}
|
||||
|
||||
for (i = 0; size && i < 8; i++) {
|
||||
int ram_tlb_index = find_free_tlbcam();
|
||||
int tlb_index = find_free_tlbcam();
|
||||
u32 camsize = __ilog2_u64(size) & tsize_mask;
|
||||
u32 align = __ilog2(ram_tlb_address) & tsize_mask;
|
||||
u32 align = __ilog2(v_addr) & tsize_mask;
|
||||
|
||||
if (ram_tlb_index == -1)
|
||||
if (tlb_index == -1)
|
||||
break;
|
||||
|
||||
if (align == -2) align = max_cam;
|
||||
|
@ -277,18 +283,29 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
|
|||
|
||||
tlb_size = camsize - 10;
|
||||
|
||||
set_tlb(1, ram_tlb_address, p_addr,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, wimge,
|
||||
0, ram_tlb_index, tlb_size, 1);
|
||||
set_tlb(1, v_addr, p_addr, perm, wimge,
|
||||
0, tlb_index, tlb_size, 1);
|
||||
|
||||
size -= 1ULL << camsize;
|
||||
memsize -= 1ULL << camsize;
|
||||
ram_tlb_address += 1UL << camsize;
|
||||
v_addr += 1UL << camsize;
|
||||
p_addr += 1UL << camsize;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
|
||||
unsigned int memsize_in_meg)
|
||||
{
|
||||
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
|
||||
u64 memsize = (u64)memsize_in_meg << 20;
|
||||
|
||||
memsize = min(memsize, CONFIG_MAX_MEM_MAPPED);
|
||||
memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM);
|
||||
|
||||
if (memsize)
|
||||
print_size(memsize, " left unmapped\n");
|
||||
|
||||
return memsize_in_meg;
|
||||
}
|
||||
|
||||
|
|
|
@ -4,6 +4,12 @@
|
|||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include "config.h" /* CONFIG_BOARDDIR */
|
||||
|
||||
#ifndef CONFIG_SYS_MONITOR_LEN
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x80000
|
||||
#endif
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
|
@ -76,7 +82,7 @@ SECTIONS
|
|||
KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
|
||||
} :text = 0xffff
|
||||
|
||||
. = ADDR(.text) + 0x80000;
|
||||
. = ADDR(.text) + CONFIG_SYS_MONITOR_LEN;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
|
|
|
@ -57,6 +57,16 @@ SECTIONS
|
|||
. = ALIGN(8);
|
||||
__init_begin = .;
|
||||
__init_end = .;
|
||||
#ifdef CONFIG_SPL_SKIP_RELOCATE
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : {
|
||||
*(.sbss*)
|
||||
*(.bss*)
|
||||
}
|
||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
#endif
|
||||
|
||||
/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
|
||||
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
|
||||
|
@ -66,11 +76,16 @@ SECTIONS
|
|||
} :text = 0xffff
|
||||
#else
|
||||
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
|
||||
.bootpg ADDR(.text) + 0x1000 :
|
||||
#ifndef BOOT_PAGE_OFFSET
|
||||
#define BOOT_PAGE_OFFSET 0x1000
|
||||
#endif
|
||||
.bootpg ADDR(.text) + BOOT_PAGE_OFFSET :
|
||||
{
|
||||
arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
|
||||
}
|
||||
#ifndef RESET_VECTOR_OFFSET
|
||||
#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
|
||||
#endif
|
||||
#elif defined(CONFIG_FSL_ELBC)
|
||||
#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
|
||||
#else
|
||||
|
@ -81,6 +96,7 @@ SECTIONS
|
|||
} = 0xffff
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SPL_SKIP_RELOCATE
|
||||
/*
|
||||
* Make sure that the bss segment isn't linked at 0x0, otherwise its
|
||||
* address won't be updated during relocation fixups.
|
||||
|
@ -95,4 +111,5 @@ SECTIONS
|
|||
}
|
||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -12,7 +12,12 @@
|
|||
#define RESET_VECTOR_ADDRESS 0xfffffffc
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_MONITOR_LEN
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x80000
|
||||
#endif
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
ENTRY(_start_e500)
|
||||
|
||||
PHDRS
|
||||
{
|
||||
|
@ -84,7 +89,7 @@ SECTIONS
|
|||
{
|
||||
KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
|
||||
} :text = 0xffff
|
||||
. = ADDR(.text) + 0x80000;
|
||||
. = ADDR(.text) + CONFIG_SYS_MONITOR_LEN;
|
||||
#else
|
||||
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
|
||||
{
|
||||
|
|
|
@ -29,12 +29,10 @@ void cpm_load_patch (volatile immap_t * immr);
|
|||
*/
|
||||
void cpu_init_f (volatile immap_t * immr)
|
||||
{
|
||||
#ifndef CONFIG_MBX
|
||||
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
||||
# ifdef CONFIG_SYS_PLPRCR
|
||||
ulong mfmask;
|
||||
# endif
|
||||
#endif
|
||||
ulong reg;
|
||||
|
||||
/* SYPCR - contains watchdog control (11-9) */
|
||||
|
@ -74,8 +72,6 @@ void cpu_init_f (volatile immap_t * immr)
|
|||
|
||||
immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
|
||||
|
||||
#ifndef CONFIG_MBX /* MBX board does things different */
|
||||
|
||||
/* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
|
||||
* set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
|
||||
* otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
|
||||
|
@ -142,7 +138,6 @@ void cpu_init_f (volatile immap_t * immr)
|
|||
defined(CONFIG_MHPC) || \
|
||||
defined(CONFIG_R360MPI) || \
|
||||
defined(CONFIG_RMU) || \
|
||||
defined(CONFIG_RPXCLASSIC) || \
|
||||
defined(CONFIG_RPXLITE) || \
|
||||
defined(CONFIG_SPC1920) || \
|
||||
defined(CONFIG_SPD823TS)
|
||||
|
@ -203,8 +198,6 @@ void cpu_init_f (volatile immap_t * immr)
|
|||
memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
|
||||
#endif
|
||||
|
||||
#endif /* ! CONFIG_MBX */
|
||||
|
||||
/*
|
||||
* Reset CPM
|
||||
*/
|
||||
|
@ -213,20 +206,6 @@ void cpu_init_f (volatile immap_t * immr)
|
|||
__asm__ ("eieio");
|
||||
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
|
||||
|
||||
#ifdef CONFIG_MBX
|
||||
/*
|
||||
* on the MBX, things are a little bit different:
|
||||
* - we need to read the VPD to get board information
|
||||
* - the plprcr is set up dynamically
|
||||
* - the memory controller is set up dynamically
|
||||
*/
|
||||
mbx_init ();
|
||||
#endif /* CONFIG_MBX */
|
||||
|
||||
#ifdef CONFIG_RPXCLASSIC
|
||||
rpxclassic_init ();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM)
|
||||
rpxlite_init ();
|
||||
#endif
|
||||
|
|
|
@ -461,23 +461,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
|
|||
#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
|
||||
/*
|
||||
* Port C is used to control the PHY,MC68160.
|
||||
*/
|
||||
immr->im_ioport.iop_pcdir |=
|
||||
(PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
|
||||
|
||||
immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
|
||||
immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
|
||||
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
|
||||
#endif /* MPC860ADS */
|
||||
|
||||
#ifdef CONFIG_RPXCLASSIC
|
||||
*((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
|
||||
*((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RPXLITE
|
||||
*((uchar *) BCSR0) |= BCSR0_ETHEN;
|
||||
#endif
|
||||
|
@ -492,10 +475,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
|
|||
immr->im_cpm.cp_pbdat &= ~0x00000010;
|
||||
#endif /* QS860T */
|
||||
|
||||
#ifdef CONFIG_MBX
|
||||
board_ether_init ();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NETVIA)
|
||||
#if defined(PA_ENET_PDN)
|
||||
immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
|
||||
|
@ -528,8 +507,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
|
|||
*/
|
||||
#if defined (CONFIG_FADS)
|
||||
udelay (10000); /* wait 10 ms */
|
||||
#elif defined(CONFIG_RPXCLASSIC)
|
||||
udelay (100000); /* wait 100 ms */
|
||||
#endif
|
||||
|
||||
return 1;
|
||||
|
|
|
@ -173,7 +173,7 @@ static int smc_init (void)
|
|||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FADS) || defined(CONFIG_ADS)
|
||||
#if defined(CONFIG_FADS)
|
||||
/* Enable RS232 */
|
||||
#if defined(CONFIG_8xx_CONS_SMC1)
|
||||
*((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
|
||||
|
@ -182,7 +182,7 @@ static int smc_init (void)
|
|||
#endif
|
||||
#endif /* CONFIG_FADS */
|
||||
|
||||
#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
|
||||
#if defined(CONFIG_RPXLITE)
|
||||
/* Enable Monitor Port Transceiver */
|
||||
*((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
|
||||
#endif /* CONFIG_RPXLITE */
|
||||
|
@ -225,10 +225,6 @@ static int smc_init (void)
|
|||
up->smc_tstate = 0;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MBX)
|
||||
board_serial_init();
|
||||
#endif /* CONFIG_MBX */
|
||||
|
||||
/* Set UART mode, 8 bit, no parity, one stop.
|
||||
* Enable receive and transmit.
|
||||
*/
|
||||
|
|
|
@ -1,20 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
|
||||
#ifdef CONFIG_WL_4PPM_KEYBOARD
|
||||
|
||||
/* WIP: Wireless keyboard on SMC
|
||||
*/
|
||||
int drv_wlkbd_init (void)
|
||||
{
|
||||
return 0 ;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_WL_4PPM_KEYBOARD */
|
|
@ -221,6 +221,32 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
|
|||
}
|
||||
#endif /* not SPL */
|
||||
|
||||
void disable_non_ddr_laws(void)
|
||||
{
|
||||
int i;
|
||||
int id;
|
||||
for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
|
||||
u32 lawar = in_be32(LAWAR_ADDR(i));
|
||||
|
||||
if (lawar & LAW_EN) {
|
||||
id = (lawar & ~LAW_EN) >> 20;
|
||||
switch (id) {
|
||||
case LAW_TRGT_IF_DDR_1:
|
||||
case LAW_TRGT_IF_DDR_2:
|
||||
case LAW_TRGT_IF_DDR_3:
|
||||
case LAW_TRGT_IF_DDR_4:
|
||||
case LAW_TRGT_IF_DDR_INTRLV:
|
||||
case LAW_TRGT_IF_DDR_INTLV_34:
|
||||
case LAW_TRGT_IF_DDR_INTLV_123:
|
||||
case LAW_TRGT_IF_DDR_INTLV_1234:
|
||||
continue;
|
||||
default:
|
||||
disable_law(i);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void init_laws(void)
|
||||
{
|
||||
int i;
|
||||
|
@ -233,6 +259,23 @@ void init_laws(void)
|
|||
#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500) && \
|
||||
!defined(CONFIG_E500MC)
|
||||
/* ISBC (Boot ROM) creates a LAW 0 entry for non PBL platforms,
|
||||
* which is not disabled before transferring the control to uboot.
|
||||
* Disable the LAW 0 entry here.
|
||||
*/
|
||||
disable_law(0);
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SECURE_BOOT)
|
||||
/*
|
||||
* if any non DDR LAWs has been created earlier, remove them before
|
||||
* LAW table is parsed.
|
||||
*/
|
||||
disable_non_ddr_laws();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Any LAWs that were set up before we booted assume they are meant to
|
||||
* be around and mark them used.
|
||||
|
@ -244,15 +287,6 @@ void init_laws(void)
|
|||
gd->arch.used_laws |= (1 << i);
|
||||
}
|
||||
|
||||
#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \
|
||||
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
|
||||
/*
|
||||
* in SPL boot we've already parsed the law_table and setup those LAWs
|
||||
* so don't do it again.
|
||||
*/
|
||||
return;
|
||||
#endif
|
||||
|
||||
for (i = 0; i < num_law_entries; i++) {
|
||||
if (law_table[i].index == -1)
|
||||
set_next_law(law_table[i].addr, law_table[i].size,
|
||||
|
|
|
@ -19,8 +19,8 @@
|
|||
*/
|
||||
#define CONFIG_PPC_SPINTABLE_COMPATIBLE
|
||||
|
||||
#define FSL_DDR_VER_4_7 47
|
||||
#define FSL_DDR_VER_5_0 50
|
||||
#include <fsl_ddrc_version.h>
|
||||
#define CONFIG_SYS_FSL_DDR_BE
|
||||
|
||||
/* IP endianness */
|
||||
#define CONFIG_SYS_FSL_IFC_BE
|
||||
|
@ -154,6 +154,7 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A007075
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
|
||||
#define CONFIG_ESDHC_HC_BLK_ADDR
|
||||
|
@ -401,6 +402,7 @@
|
|||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 32
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
||||
|
@ -442,6 +444,7 @@
|
|||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
||||
|
@ -476,6 +479,7 @@
|
|||
#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005812
|
||||
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A007075
|
||||
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
|
||||
|
||||
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
|
||||
|
@ -490,6 +494,7 @@
|
|||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 32
|
||||
|
@ -527,6 +532,7 @@
|
|||
#define CONFIG_SYS_NUM_FM2_DTSEC 5
|
||||
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
||||
|
@ -553,6 +559,7 @@
|
|||
#define CONFIG_TSECV2
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
|
||||
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
|
||||
|
@ -571,6 +578,7 @@
|
|||
#define CONFIG_TSECV2
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
|
||||
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
|
||||
|
@ -668,8 +676,10 @@
|
|||
#define CONFIG_SYS_FSL_ERRATUM_A005871
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006379
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006593
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A007075
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006475
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A006384
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A007212
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
||||
|
||||
#ifdef CONFIG_PPC_B4860
|
||||
|
@ -704,6 +714,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
||||
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
|
||||
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
||||
#ifdef CONFIG_SYS_FSL_DDR4
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN4
|
||||
#endif
|
||||
#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
|
||||
#define CONFIG_MAX_CPUS 4
|
||||
#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
||||
|
@ -736,6 +749,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
|
||||
#define QE_MURAM_SIZE 0x6000UL
|
||||
#define MAX_QE_RISC 1
|
||||
#define QE_NUM_OF_SNUM 28
|
||||
|
||||
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
|
||||
#define CONFIG_E6500
|
||||
|
@ -777,6 +793,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
|
||||
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A007212
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
||||
#define CONFIG_SYS_FSL_ISBC_VER 2
|
||||
|
@ -793,10 +810,15 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|||
#define CONFIG_SYS_FSL_SEC_COMPAT 6
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005125
|
||||
|
||||
#elif defined(CONFIG_QEMU_E500)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
|
||||
|
||||
#else
|
||||
#error Processor type not defined for this platform
|
||||
#endif
|
||||
|
@ -813,7 +835,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|||
|
||||
#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
|
||||
!defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
|
||||
!defined(CONFIG_SYS_FSL_DDRC_GEN3)
|
||||
!defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
|
||||
!defined(CONFIG_SYS_FSL_DDRC_GEN4)
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN3
|
||||
#endif
|
||||
|
||||
|
|
|
@ -60,4 +60,20 @@ static inline bool has_erratum_a006261(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
static inline bool has_erratum_a007075(void)
|
||||
{
|
||||
u32 svr = get_svr();
|
||||
u32 soc = SVR_SOC_VER(svr);
|
||||
|
||||
switch (soc) {
|
||||
case SVR_B4860:
|
||||
case SVR_B4420:
|
||||
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
|
||||
case SVR_P1010:
|
||||
return IS_SVR_REV(svr, 1, 0);
|
||||
case SVR_P4080:
|
||||
return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -99,6 +99,10 @@ extern void fdt_fixup_liodn(void *blob);
|
|||
SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
|
||||
CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
|
||||
|
||||
#define SET_QE_LIODN(liodn) \
|
||||
SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
|
||||
CONFIG_SYS_MPC85xx_QE_OFFSET)
|
||||
|
||||
#define SET_QMAN_LIODN(liodn) \
|
||||
SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
|
||||
CONFIG_SYS_FSL_QMAN_OFFSET, \
|
||||
|
|
|
@ -10,10 +10,22 @@
|
|||
#ifdef CONFIG_SECURE_BOOT
|
||||
#if defined(CONFIG_FSL_CORENET)
|
||||
#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
|
||||
#elif defined(CONFIG_BSC9132QDS)
|
||||
#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
|
||||
#else
|
||||
#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
|
||||
|
||||
#if defined(CONFIG_B4860QDS) || \
|
||||
defined(CONFIG_T4240QDS) || \
|
||||
defined(CONFIG_T2080QDS) || \
|
||||
defined(CONFIG_T1040QDS) || \
|
||||
defined(CONFIG_T1040RDB)
|
||||
#define CONFIG_SYS_CPC_REINIT_F
|
||||
#undef CONFIG_SYS_INIT_L3_ADDR
|
||||
#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
@ -59,7 +59,6 @@ typedef struct sysconf512x {
|
|||
u8 res2[0x28];
|
||||
law512x_t ddrlaw; /* DDR Local Access Window */
|
||||
u8 res3[0x18];
|
||||
u32 mbxbar; /* MBX Base Address */
|
||||
u32 srambar; /* SRAM Base Address */
|
||||
u32 nfcbar; /* NFC Base Address */
|
||||
u8 res4[0x34];
|
||||
|
|
|
@ -1583,6 +1583,12 @@ typedef struct cpc_corenet {
|
|||
typedef struct ccsr_gur {
|
||||
u32 porsr1; /* POR status 1 */
|
||||
u32 porsr2; /* POR status 2 */
|
||||
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
|
||||
#define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15
|
||||
#define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1
|
||||
#define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1
|
||||
#define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0
|
||||
#endif
|
||||
u8 res_008[0x20-0x8];
|
||||
u32 gpporcr1; /* General-purpose POR configuration */
|
||||
u32 gpporcr2; /* General-purpose POR configuration 2 */
|
||||
|
@ -1739,6 +1745,8 @@ typedef struct ccsr_gur {
|
|||
|
||||
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
|
||||
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
|
||||
/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
|
||||
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
|
||||
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
|
||||
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
|
||||
|
@ -1889,7 +1897,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
|||
u32 sata2liodnr; /* SATA 2 LIODN */
|
||||
u32 sata3liodnr; /* SATA 3 LIODN */
|
||||
u32 sata4liodnr; /* SATA 4 LIODN */
|
||||
u8 res22[32];
|
||||
u8 res22[24];
|
||||
u32 qeliodnr; /* QE LIODN */
|
||||
u8 res_57c[4];
|
||||
u32 dma1liodnr; /* DMA 1 LIODN */
|
||||
u32 dma2liodnr; /* DMA 2 LIODN */
|
||||
u32 dma3liodnr; /* DMA 3 LIODN */
|
||||
|
@ -2877,6 +2887,7 @@ struct ccsr_pman {
|
|||
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
|
||||
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
|
||||
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
|
||||
#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
|
||||
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
|
||||
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
|
||||
&& !defined(CONFIG_PPC_B4420)
|
||||
|
@ -3151,4 +3162,26 @@ struct dcsr_dcfg_regs {
|
|||
#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
|
||||
u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
|
||||
};
|
||||
|
||||
#define CONFIG_SYS_MPC85xx_SCFG \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
|
||||
/* The supplement configuration unit register */
|
||||
struct ccsr_scfg {
|
||||
u32 dpslpcr; /* 0x000 Deep Sleep Control register */
|
||||
u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
|
||||
u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
|
||||
u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
|
||||
u32 res1[4];
|
||||
u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
|
||||
u32 res2;
|
||||
u32 pixclkcr; /* 0x028 Pixel Clock Control register */
|
||||
u32 res3[245];
|
||||
u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */
|
||||
u32 emiiocr; /* 0x404 EMI MDIO Control Register */
|
||||
u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
|
||||
u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */
|
||||
u32 res4[60];
|
||||
u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */
|
||||
};
|
||||
#endif /*__IMMAP_85xx__*/
|
||||
|
|
|
@ -509,6 +509,14 @@ extern void print_tlbcam(void);
|
|||
extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
|
||||
extern void clear_ddr_tlbs(unsigned int memsize_in_meg);
|
||||
|
||||
enum tlb_map_type {
|
||||
TLB_MAP_RAM,
|
||||
TLB_MAP_IO,
|
||||
};
|
||||
|
||||
extern uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
|
||||
enum tlb_map_type map_type);
|
||||
|
||||
extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);
|
||||
|
||||
#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
|
||||
|
|
|
@ -106,9 +106,6 @@ typedef struct bd_info {
|
|||
unsigned int bi_opbfreq; /* OPB clock in Hz */
|
||||
int bi_iic_fast[2]; /* Use fast i2c mode */
|
||||
#endif
|
||||
#if defined(CONFIG_NX823)
|
||||
unsigned char bi_sernum[8];
|
||||
#endif
|
||||
#if defined(CONFIG_4xx)
|
||||
#if defined(CONFIG_440GX) || \
|
||||
defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
||||
|
|
|
@ -343,6 +343,13 @@ void board_init_f(ulong bootflag)
|
|||
#ifdef CONFIG_PRAM
|
||||
ulong reg;
|
||||
#endif
|
||||
#ifdef CONFIG_DEEP_SLEEP
|
||||
const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
|
||||
u32 start_addr;
|
||||
typedef void (*func_t)(void);
|
||||
func_t kernel_resume;
|
||||
#endif
|
||||
|
||||
/* Pointer is writable since we allocated a register for it */
|
||||
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
|
||||
|
@ -360,6 +367,15 @@ void board_init_f(ulong bootflag)
|
|||
if ((*init_fnc_ptr) () != 0)
|
||||
hang();
|
||||
|
||||
#ifdef CONFIG_DEEP_SLEEP
|
||||
/* Jump to kernel in deep sleep case */
|
||||
if (in_be32(&gur->scrtsr[0]) & (1 << 3)) {
|
||||
start_addr = in_be32(&scfg->sparecr[1]);
|
||||
kernel_resume = (func_t)start_addr;
|
||||
kernel_resume();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
post_bootmode_init();
|
||||
post_run(NULL, POST_ROM | post_bootmode_get(NULL));
|
||||
|
|
|
@ -1,96 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
|
||||
*
|
||||
* Copyright (C) 2007, 2008 Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
* Copyright (C) 2008 Renesas Solutions Corp.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
/*
|
||||
* Jump to P2 area.
|
||||
* When handling TLB or caches, we need to do it from P2 area.
|
||||
*/
|
||||
#define jump_to_P2() \
|
||||
do { \
|
||||
unsigned long __dummy; \
|
||||
__asm__ __volatile__( \
|
||||
"mov.l 1f, %0\n\t" \
|
||||
"or %1, %0\n\t" \
|
||||
"jmp @%0\n\t" \
|
||||
" nop\n\t" \
|
||||
".balign 4\n" \
|
||||
"1: .long 2f\n" \
|
||||
"2:" \
|
||||
: "=&r" (__dummy) \
|
||||
: "r" (0x20000000)); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* Back to P1 area.
|
||||
*/
|
||||
#define back_to_P1() \
|
||||
do { \
|
||||
unsigned long __dummy; \
|
||||
__asm__ __volatile__( \
|
||||
"nop;nop;nop;nop;nop;nop;nop\n\t" \
|
||||
"mov.l 1f, %0\n\t" \
|
||||
"jmp @%0\n\t" \
|
||||
" nop\n\t" \
|
||||
".balign 4\n" \
|
||||
"1: .long 2f\n" \
|
||||
"2:" \
|
||||
: "=&r" (__dummy)); \
|
||||
} while (0)
|
||||
|
||||
#define CACHE_VALID 1
|
||||
#define CACHE_UPDATED 2
|
||||
|
||||
static inline void cache_wback_all(void)
|
||||
{
|
||||
unsigned long addr, data, i, j;
|
||||
|
||||
jump_to_P2();
|
||||
for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
|
||||
for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
|
||||
addr = CACHE_OC_ADDRESS_ARRAY
|
||||
| (j << CACHE_OC_WAY_SHIFT)
|
||||
| (i << CACHE_OC_ENTRY_SHIFT);
|
||||
data = inl(addr);
|
||||
if (data & CACHE_UPDATED) {
|
||||
data &= ~CACHE_UPDATED;
|
||||
outl(data, addr);
|
||||
}
|
||||
}
|
||||
}
|
||||
back_to_P1();
|
||||
}
|
||||
|
||||
|
||||
#define CACHE_ENABLE 0
|
||||
#define CACHE_DISABLE 1
|
||||
|
||||
int cache_control(unsigned int cmd)
|
||||
{
|
||||
unsigned long ccr;
|
||||
|
||||
jump_to_P2();
|
||||
ccr = inl(CCR);
|
||||
|
||||
if (ccr & CCR_CACHE_ENABLE)
|
||||
cache_wback_all();
|
||||
|
||||
if (cmd == CACHE_DISABLE)
|
||||
outl(CCR_CACHE_STOP, CCR);
|
||||
else
|
||||
outl(CCR_CACHE_INIT, CCR);
|
||||
back_to_P1();
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -7,4 +7,4 @@
|
|||
|
||||
PLATFORM_RELFLAGS += -fPIC
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_LEON
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON2
|
||||
|
|
|
@ -7,4 +7,4 @@
|
|||
|
||||
PLATFORM_RELFLAGS += -fPIC
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_LEON
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON3
|
||||
|
|
|
@ -1,115 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifdef ECC_TEST
|
||||
static inline void ecc_off (void)
|
||||
{
|
||||
*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000;
|
||||
}
|
||||
|
||||
static inline void ecc_on (void)
|
||||
{
|
||||
*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000;
|
||||
}
|
||||
|
||||
static int putshex (const char *buf, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
printf ("%02x", buf[i]);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int char_memcpy (void *d, const void *s, int len)
|
||||
{
|
||||
int i;
|
||||
char *cd = d;
|
||||
const char *cs = s;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
*(cd++) = *(cs++);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int memory_test (char *buf)
|
||||
{
|
||||
const char src[][16] = {
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
|
||||
0x01, 0x01, 0x01, 0x01, 0x01, 0x01},
|
||||
{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
|
||||
0x02, 0x02, 0x02, 0x02, 0x02, 0x02},
|
||||
{0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
|
||||
0x04, 0x04, 0x04, 0x04, 0x04, 0x04},
|
||||
{0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
|
||||
0x08, 0x08, 0x08, 0x08, 0x08, 0x08},
|
||||
{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
|
||||
0x10, 0x10, 0x10, 0x10, 0x10, 0x10},
|
||||
{0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
|
||||
0x20, 0x20, 0x20, 0x20, 0x20, 0x20},
|
||||
{0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
|
||||
0x40, 0x40, 0x40, 0x40, 0x40, 0x40},
|
||||
{0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
|
||||
0x80, 0x80, 0x80, 0x80, 0x80, 0x80},
|
||||
{0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
|
||||
0x55, 0x55, 0x55, 0x55, 0x55, 0x55},
|
||||
{0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
|
||||
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa},
|
||||
{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
|
||||
};
|
||||
const int foo[] = { 0 };
|
||||
int i, j, a;
|
||||
|
||||
printf ("\ntest @ %d %p\n", foo[0], buf);
|
||||
for (i = 0; i < 12; i++) {
|
||||
for (a = 0; a < 8; a++) {
|
||||
const char *s = src[i] + a;
|
||||
int align = (unsigned) (s) & 0x7;
|
||||
|
||||
/* ecc_off(); */
|
||||
memcpy (buf, s, 8);
|
||||
/* ecc_on(); */
|
||||
putshex (s, 8);
|
||||
if (memcmp (buf, s, 8)) {
|
||||
putc ('\n');
|
||||
putshex (buf, 8);
|
||||
printf (" [FAIL] (%p) align=%d\n", s, align);
|
||||
for (j = 0; j < 8; j++) {
|
||||
s[j] == buf[j] ? puts (" ") :
|
||||
printf ("%02x",
|
||||
(s[j]) ^ (buf[j]));
|
||||
}
|
||||
putc ('\n');
|
||||
} else {
|
||||
printf (" [PASS] (%p) align=%d\n", s, align);
|
||||
}
|
||||
/* ecc_off(); */
|
||||
char_memcpy (buf, s, 8);
|
||||
/* ecc_on(); */
|
||||
putshex (s, 8);
|
||||
if (memcmp (buf, s, 8)) {
|
||||
putc ('\n');
|
||||
putshex (buf, 8);
|
||||
printf (" [FAIL] (%p) align=%d\n", s, align);
|
||||
for (j = 0; j < 8; j++) {
|
||||
s[j] == buf[j] ? puts (" ") :
|
||||
printf ("%02x",
|
||||
(s[j]) ^ (buf[j]));
|
||||
}
|
||||
putc ('\n');
|
||||
} else {
|
||||
printf (" [PASS] (%p) align=%d\n", s, align);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
|
@ -1,8 +0,0 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y = RPXClassic.o flash.o eccx.o
|
|
@ -1,19 +0,0 @@
|
|||
# Porting U-Boot onto RPXClassic LF_BW31 board
|
||||
# Written by Pierre AUBERT
|
||||
# E-Mail p.aubert@staubli.com
|
||||
# Stäubli Faverges - <www.staubli.com>
|
||||
#
|
||||
# Sept. 20 2001
|
||||
#
|
||||
# Cross compile: Montavista Hardhat ported on HP-UX 10.20
|
||||
#
|
||||
|
||||
Flash memories : AM29DL323B (2 banks flash memories) 16 Mb from 0xff000000
|
||||
DRAM : 16 Mb from 0
|
||||
NVRAM : 512 kb from 0xfa000000
|
||||
|
||||
|
||||
- environment is stored in NVRAM
|
||||
- Mac address is read from EEPROM
|
||||
- ethernet on SCC1 or fast ethernet on FEC are running (depending on the
|
||||
configuration flag CONFIG_FEC_ENET)
|
|
@ -1,260 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stäubli Faverges - <www.staubli.com>
|
||||
* Pierre AUBERT p.aubert@staubli.com
|
||||
* U-Boot port on RPXClassic LF (CLLF_BW31) board
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <config.h>
|
||||
#include <mpc8xx.h>
|
||||
#include <net.h>
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
static long int dram_size (long int, long int *, long int);
|
||||
static unsigned char aschex_to_byte (unsigned char *cp);
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#define _NOT_USED_ 0xFFFFCC25
|
||||
|
||||
const uint sdram_table[] =
|
||||
{
|
||||
/*
|
||||
* Single Read. (Offset 00h in UPMA RAM)
|
||||
*/
|
||||
0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
|
||||
0x3FBFCC27, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
|
||||
/*
|
||||
* Burst Read. (Offset 08h in UPMA RAM)
|
||||
*/
|
||||
0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
|
||||
0x3FBFCC27, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
|
||||
/*
|
||||
* Single Write. (Offset 18h in UPMA RAM)
|
||||
*/
|
||||
0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
|
||||
0x3FFFCC27, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
|
||||
/*
|
||||
* Burst Write. (Offset 20h in UPMA RAM)
|
||||
*/
|
||||
0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
|
||||
0x0CFFCC00, 0x33FFCC27, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_,
|
||||
|
||||
/*
|
||||
* Refresh. (Offset 30h in UPMA RAM)
|
||||
*/
|
||||
0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
|
||||
0x3FFFCC27, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
|
||||
/*
|
||||
* Exception. (Offset 3Ch in UPMA RAM)
|
||||
*/
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
|
||||
};
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
puts ("Board: RPXClassic\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* board_get_enetaddr -- Read the MAC Address in the I2C EEPROM
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
static void board_get_enetaddr(uchar *enet)
|
||||
{
|
||||
int i;
|
||||
char buff[256], *cp;
|
||||
|
||||
/* Initialize I2C */
|
||||
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
|
||||
/* Read 256 bytes in EEPROM */
|
||||
i2c_read (0x54, 0, 1, (uchar *)buff, 128);
|
||||
i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128);
|
||||
|
||||
/* Retrieve MAC address in buffer (key EA) */
|
||||
for (cp = buff;;) {
|
||||
if (cp[0] == 'E' && cp[1] == 'A') {
|
||||
cp += 3;
|
||||
/* Read MAC address */
|
||||
for (i = 0; i < 6; i++, cp += 2) {
|
||||
enet[i] = aschex_to_byte ((unsigned char *)cp);
|
||||
}
|
||||
}
|
||||
/* Scan to the end of the record */
|
||||
while ((*cp != '\n') && (*cp != (char)0xff)) {
|
||||
cp++;
|
||||
}
|
||||
/* If the next character is a \n, 0 or ff, we are done. */
|
||||
cp++;
|
||||
if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff))
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FEC_ENET
|
||||
/* The MAC address is the same as normal ethernet except the 3rd byte */
|
||||
/* (See the E.P. Planet Core Overview manual */
|
||||
enet[3] |= 0x80;
|
||||
#endif
|
||||
|
||||
printf("MAC address = %pM\n", enet);
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
uchar enetaddr[6];
|
||||
|
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
|
||||
board_get_enetaddr(enetaddr);
|
||||
eth_setenv_enetaddr("ethaddr", enetaddr);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void rpxclassic_init (void)
|
||||
{
|
||||
/* Enable NVRAM */
|
||||
*((uchar *) BCSR0) |= BCSR0_ENNVRAM;
|
||||
|
||||
#ifdef CONFIG_FEC_ENET
|
||||
|
||||
/* Validate the fast ethernet tranceiver */
|
||||
*((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL;
|
||||
*((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN;
|
||||
*((volatile uchar *) BCSR2) |= BCSR2_MIIRST;
|
||||
*((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
phys_size_t initdram (int board_type)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
long int size10;
|
||||
|
||||
upmconfig (UPMA, (uint *) sdram_table,
|
||||
sizeof (sdram_table) / sizeof (uint));
|
||||
|
||||
/* Refresh clock prescalar */
|
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
|
||||
|
||||
memctl->memc_mar = 0x00000000;
|
||||
|
||||
/* Map controller banks 1 to the SDRAM bank */
|
||||
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
|
||||
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
|
||||
|
||||
memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
|
||||
|
||||
udelay (200);
|
||||
|
||||
/* perform SDRAM initializsation sequence */
|
||||
|
||||
memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */
|
||||
udelay (1);
|
||||
|
||||
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
|
||||
|
||||
udelay (1000);
|
||||
|
||||
/* Check Bank 0 Memory Size
|
||||
* try 10 column mode
|
||||
*/
|
||||
|
||||
size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
|
||||
SDRAM_MAX_SIZE);
|
||||
|
||||
return (size10);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Check memory range for valid RAM. A simple memory test determines
|
||||
* the actually available RAM size between addresses `base' and
|
||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
||||
* - short between address lines
|
||||
* - short between data lines
|
||||
*/
|
||||
|
||||
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
|
||||
memctl->memc_mamr = mamr_value;
|
||||
|
||||
return (get_ram_size(base, maxsize));
|
||||
}
|
||||
/*-----------------------------------------------------------------------------
|
||||
* aschex_to_byte --
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
static unsigned char aschex_to_byte (unsigned char *cp)
|
||||
{
|
||||
u_char byte, c;
|
||||
|
||||
c = *cp++;
|
||||
|
||||
if ((c >= 'A') && (c <= 'F')) {
|
||||
c -= 'A';
|
||||
c += 10;
|
||||
} else if ((c >= 'a') && (c <= 'f')) {
|
||||
c -= 'a';
|
||||
c += 10;
|
||||
} else {
|
||||
c -= '0';
|
||||
}
|
||||
|
||||
byte = c * 16;
|
||||
|
||||
c = *cp;
|
||||
|
||||
if ((c >= 'A') && (c <= 'F')) {
|
||||
c -= 'A';
|
||||
c += 10;
|
||||
} else if ((c >= 'a') && (c <= 'f')) {
|
||||
c -= 'a';
|
||||
c += 10;
|
||||
} else {
|
||||
c -= '0';
|
||||
}
|
||||
|
||||
byte += c;
|
||||
|
||||
return (byte);
|
||||
}
|
|
@ -1,335 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Stäubli Faverges - <www.staubli.com>
|
||||
* Pierre AUBERT p.aubert@staubli.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
/* Video support for the ECCX daughter board */
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
|
||||
#ifdef CONFIG_VIDEO_SED13806
|
||||
#include <sed13806.h>
|
||||
|
||||
|
||||
/* Screen configurations: the initialization of the SD13806 depends on
|
||||
screen and on display mode. We handle only 8bpp and 16 bpp modes */
|
||||
|
||||
/* ECCX board is supplied with a NEC NL6448BC20 screen */
|
||||
#ifdef CONFIG_NEC_NL6448BC20
|
||||
#define DISPLAY_WIDTH 640
|
||||
#define DISPLAY_HEIGHT 480
|
||||
|
||||
#ifdef CONFIG_VIDEO_SED13806_8BPP
|
||||
static const S1D_REGS init_regs [] =
|
||||
{
|
||||
{0x0001,0x00}, /* Miscellaneous Register */
|
||||
{0x01FC,0x00}, /* Display Mode Register */
|
||||
{0x0004,0x1b}, /* General IO Pins Configuration Register 0 */
|
||||
{0x0005,0x00}, /* General IO Pins Configuration Register 1 */
|
||||
{0x0008,0xe5}, /* General IO Pins Control Register 0 */
|
||||
{0x0009,0x1f}, /* General IO Pins Control Register 1 */
|
||||
{0x0010,0x02}, /* Memory Clock Configuration Register */
|
||||
{0x0014,0x10}, /* LCD Pixel Clock Configuration Register */
|
||||
{0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
|
||||
{0x001C,0x02}, /* MediaPlug Clock Configuration Register */
|
||||
{0x001E,0x01}, /* CPU To Memory Wait State Select Register */
|
||||
{0x0021,0x04}, /* DRAM Refresh Rate Register */
|
||||
{0x002A,0x00}, /* DRAM Timings Control Register 0 */
|
||||
{0x002B,0x01}, /* DRAM Timings Control Register 1 */
|
||||
{0x0020,0x80}, /* Memory Configuration Register */
|
||||
{0x0030,0x25}, /* Panel Type Register */
|
||||
{0x0031,0x00}, /* MOD Rate Register */
|
||||
{0x0032,0x4F}, /* LCD Horizontal Display Width Register */
|
||||
{0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
|
||||
{0x0035,0x01}, /* TFT FPLINE Start Position Register */
|
||||
{0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
|
||||
{0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
|
||||
{0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
|
||||
{0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
|
||||
{0x003B,0x00}, /* TFT FPFRAME Start Position Register */
|
||||
{0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
|
||||
{0x0040,0x03}, /* LCD Display Mode Register */
|
||||
{0x0041,0x02}, /* LCD Miscellaneous Register */
|
||||
{0x0042,0x00}, /* LCD Display Start Address Register 0 */
|
||||
{0x0043,0x00}, /* LCD Display Start Address Register 1 */
|
||||
{0x0044,0x00}, /* LCD Display Start Address Register 2 */
|
||||
{0x0046,0x40}, /* LCD Memory Address Offset Register 0 */
|
||||
{0x0047,0x01}, /* LCD Memory Address Offset Register 1 */
|
||||
{0x0048,0x00}, /* LCD Pixel Panning Register */
|
||||
{0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
|
||||
{0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
|
||||
{0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
|
||||
{0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
|
||||
{0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
|
||||
{0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
|
||||
{0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
|
||||
{0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
|
||||
{0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
|
||||
{0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
|
||||
{0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
|
||||
{0x005B,0x00}, /* TV Output Control Register */
|
||||
{0x0060,0x03}, /* CRT/TV Display Mode Register */
|
||||
{0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
|
||||
{0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
|
||||
{0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
|
||||
{0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */
|
||||
{0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */
|
||||
{0x0068,0x00}, /* CRT/TV Pixel Panning Register */
|
||||
{0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
|
||||
{0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
|
||||
{0x0070,0x00}, /* LCD Ink/Cursor Control Register */
|
||||
{0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */
|
||||
{0x0072,0x00}, /* LCD Cursor X Position Register 0 */
|
||||
{0x0073,0x00}, /* LCD Cursor X Position Register 1 */
|
||||
{0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
|
||||
{0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
|
||||
{0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
|
||||
{0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
|
||||
{0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
|
||||
{0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
|
||||
{0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
|
||||
{0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
|
||||
{0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
|
||||
{0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
|
||||
{0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */
|
||||
{0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
|
||||
{0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
|
||||
{0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
|
||||
{0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
|
||||
{0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
|
||||
{0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
|
||||
{0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
|
||||
{0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
|
||||
{0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
|
||||
{0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
|
||||
{0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
|
||||
{0x0100,0x00}, /* BitBlt Control Register 0 */
|
||||
{0x0101,0x00}, /* BitBlt Control Register 1 */
|
||||
{0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
|
||||
{0x0103,0x00}, /* BitBlt Operation Register */
|
||||
{0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
|
||||
{0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
|
||||
{0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
|
||||
{0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
|
||||
{0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
|
||||
{0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
|
||||
{0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
|
||||
{0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
|
||||
{0x0110,0x00}, /* BitBlt Width Register 0 */
|
||||
{0x0111,0x00}, /* BitBlt Width Register 1 */
|
||||
{0x0112,0x00}, /* BitBlt Height Register 0 */
|
||||
{0x0113,0x00}, /* BitBlt Height Register 1 */
|
||||
{0x0114,0x00}, /* BitBlt Background Color Register 0 */
|
||||
{0x0115,0x00}, /* BitBlt Background Color Register 1 */
|
||||
{0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
|
||||
{0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
|
||||
{0x01E0,0x00}, /* Look-Up Table Mode Register */
|
||||
{0x01E2,0x00}, /* Look-Up Table Address Register */
|
||||
{0x01E4,0x00}, /* Look-Up Table Data Register */
|
||||
{0x01F0,0x10}, /* Power Save Configuration Register */
|
||||
{0x01F1,0x00}, /* Power Save Status Register */
|
||||
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
|
||||
{0x01FC,0x01}, /* Display Mode Register */
|
||||
{0, 0}
|
||||
};
|
||||
#endif /* CONFIG_VIDEO_SED13806_8BPP */
|
||||
|
||||
#ifdef CONFIG_VIDEO_SED13806_16BPP
|
||||
|
||||
static const S1D_REGS init_regs [] =
|
||||
{
|
||||
{0x0001,0x00}, /* Miscellaneous Register */
|
||||
{0x01FC,0x00}, /* Display Mode Register */
|
||||
{0x0004,0x1b}, /* General IO Pins Configuration Register 0 */
|
||||
{0x0005,0x00}, /* General IO Pins Configuration Register 1 */
|
||||
{0x0008,0xe5}, /* General IO Pins Control Register 0 */
|
||||
{0x0009,0x1f}, /* General IO Pins Control Register 1 */
|
||||
{0x0010,0x02}, /* Memory Clock Configuration Register */
|
||||
{0x0014,0x10}, /* LCD Pixel Clock Configuration Register */
|
||||
{0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
|
||||
{0x001C,0x02}, /* MediaPlug Clock Configuration Register */
|
||||
{0x001E,0x01}, /* CPU To Memory Wait State Select Register */
|
||||
{0x0021,0x04}, /* DRAM Refresh Rate Register */
|
||||
{0x002A,0x00}, /* DRAM Timings Control Register 0 */
|
||||
{0x002B,0x01}, /* DRAM Timings Control Register 1 */
|
||||
{0x0020,0x80}, /* Memory Configuration Register */
|
||||
{0x0030,0x25}, /* Panel Type Register */
|
||||
{0x0031,0x00}, /* MOD Rate Register */
|
||||
{0x0032,0x4F}, /* LCD Horizontal Display Width Register */
|
||||
{0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
|
||||
{0x0035,0x01}, /* TFT FPLINE Start Position Register */
|
||||
{0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
|
||||
{0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
|
||||
{0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
|
||||
{0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
|
||||
{0x003B,0x00}, /* TFT FPFRAME Start Position Register */
|
||||
{0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
|
||||
{0x0040,0x05}, /* LCD Display Mode Register */
|
||||
{0x0041,0x02}, /* LCD Miscellaneous Register */
|
||||
{0x0042,0x00}, /* LCD Display Start Address Register 0 */
|
||||
{0x0043,0x00}, /* LCD Display Start Address Register 1 */
|
||||
{0x0044,0x00}, /* LCD Display Start Address Register 2 */
|
||||
{0x0046,0x80}, /* LCD Memory Address Offset Register 0 */
|
||||
{0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
|
||||
{0x0048,0x00}, /* LCD Pixel Panning Register */
|
||||
{0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
|
||||
{0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
|
||||
{0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
|
||||
{0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
|
||||
{0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
|
||||
{0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
|
||||
{0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
|
||||
{0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
|
||||
{0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
|
||||
{0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
|
||||
{0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
|
||||
{0x005B,0x00}, /* TV Output Control Register */
|
||||
{0x0060,0x05}, /* CRT/TV Display Mode Register */
|
||||
{0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
|
||||
{0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
|
||||
{0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
|
||||
{0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */
|
||||
{0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */
|
||||
{0x0068,0x00}, /* CRT/TV Pixel Panning Register */
|
||||
{0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
|
||||
{0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
|
||||
{0x0070,0x00}, /* LCD Ink/Cursor Control Register */
|
||||
{0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */
|
||||
{0x0072,0x00}, /* LCD Cursor X Position Register 0 */
|
||||
{0x0073,0x00}, /* LCD Cursor X Position Register 1 */
|
||||
{0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
|
||||
{0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
|
||||
{0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
|
||||
{0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
|
||||
{0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
|
||||
{0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
|
||||
{0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
|
||||
{0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
|
||||
{0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
|
||||
{0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
|
||||
{0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */
|
||||
{0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
|
||||
{0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
|
||||
{0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
|
||||
{0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
|
||||
{0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
|
||||
{0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
|
||||
{0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
|
||||
{0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
|
||||
{0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
|
||||
{0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
|
||||
{0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
|
||||
{0x0100,0x00}, /* BitBlt Control Register 0 */
|
||||
{0x0101,0x00}, /* BitBlt Control Register 1 */
|
||||
{0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
|
||||
{0x0103,0x00}, /* BitBlt Operation Register */
|
||||
{0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
|
||||
{0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
|
||||
{0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
|
||||
{0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
|
||||
{0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
|
||||
{0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
|
||||
{0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
|
||||
{0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
|
||||
{0x0110,0x00}, /* BitBlt Width Register 0 */
|
||||
{0x0111,0x00}, /* BitBlt Width Register 1 */
|
||||
{0x0112,0x00}, /* BitBlt Height Register 0 */
|
||||
{0x0113,0x00}, /* BitBlt Height Register 1 */
|
||||
{0x0114,0x00}, /* BitBlt Background Color Register 0 */
|
||||
{0x0115,0x00}, /* BitBlt Background Color Register 1 */
|
||||
{0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
|
||||
{0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
|
||||
{0x01E0,0x01}, /* Look-Up Table Mode Register */
|
||||
{0x01E2,0x00}, /* Look-Up Table Address Register */
|
||||
{0x01E4,0x00}, /* Look-Up Table Data Register */
|
||||
{0x01F0,0x10}, /* Power Save Configuration Register */
|
||||
{0x01F1,0x00}, /* Power Save Status Register */
|
||||
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
|
||||
{0x01FC,0x01}, /* Display Mode Register */
|
||||
{0, 0}
|
||||
};
|
||||
|
||||
#endif /* CONFIG_VIDEO_SED13806_16BPP */
|
||||
#endif /* CONFIG_NEC_NL6448BC20 */
|
||||
|
||||
|
||||
#ifdef CONFIG_CONSOLE_EXTRA_INFO
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* video_get_info_str -- setup a board string: type, speed, etc.
|
||||
* line_number= location to place info string beside logo
|
||||
* info= buffer for info string
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
void video_get_info_str (int line_number, char *info)
|
||||
{
|
||||
if (line_number == 1) {
|
||||
strcpy (info, " RPXClassic board");
|
||||
}
|
||||
else {
|
||||
info [0] = '\0';
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* board_video_init -- init de l'EPSON, config du CS
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
unsigned int board_video_init (void)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
|
||||
/* Program ECCX registers */
|
||||
*(ECCX_CSR12) |= ECCX_860;
|
||||
*(ECCX_CSR8) |= ECCX_BE | ECCX_CS2;
|
||||
*(ECCX_CSR8) |= ECCX_ENEPSON;
|
||||
|
||||
memctl->memc_or2 = SED13806_OR;
|
||||
memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES;
|
||||
|
||||
return (SED13806_REG_ADDR);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* board_validate_screen --
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
void board_validate_screen (unsigned int base)
|
||||
{
|
||||
/* Activate the panel bias power */
|
||||
*(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80;
|
||||
}
|
||||
/*-----------------------------------------------------------------------------
|
||||
* board_get_regs --
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
const S1D_REGS *board_get_regs (void)
|
||||
{
|
||||
return (init_regs);
|
||||
}
|
||||
/*-----------------------------------------------------------------------------
|
||||
* board_get_width --
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
int board_get_width (void)
|
||||
{
|
||||
return (DISPLAY_WIDTH);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* board_get_height --
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
int board_get_height (void)
|
||||
{
|
||||
return (DISPLAY_HEIGHT);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_VIDEO_SED13806 */
|
|
@ -1,431 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stäubli Faverges - <www.staubli.com>
|
||||
* Pierre AUBERT p.aubert@staubli.com
|
||||
* U-Boot port on RPXClassic LF (CLLF_BW31) board
|
||||
*
|
||||
* RPXClassic uses Am29DL323B flash memory with 2 banks
|
||||
*
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc8xx.h>
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data);
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0 ;
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
|
||||
|
||||
|
||||
flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
|
||||
|
||||
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
|
||||
/* monitor protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_SYS_MONITOR_BASE,
|
||||
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00008000;
|
||||
info->start[2] = base + 0x00010000;
|
||||
info->start[3] = base + 0x00018000;
|
||||
info->start[4] = base + 0x00020000;
|
||||
info->start[5] = base + 0x00028000;
|
||||
info->start[6] = base + 0x00030000;
|
||||
info->start[7] = base + 0x00038000;
|
||||
for (i = 8; i < info->sector_count; i++) {
|
||||
info->start[i] = base + ((i-7) * 0x00040000) ;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD: printf ("AMD "); break;
|
||||
default: printf ("Unknown Vendor "); break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_AMDL323B:
|
||||
printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i=0; i<info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " "
|
||||
);
|
||||
}
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
|
||||
{
|
||||
short i;
|
||||
ulong value;
|
||||
ulong base = (ulong)addr;
|
||||
|
||||
/* Reset flash componeny */
|
||||
addr [0] = 0xf0f0f0f0;
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
addr[0xAAA] = 0xAAAAAAAA ;
|
||||
addr[0x555] = 0x55555555 ;
|
||||
addr[0xAAA] = 0x90909090 ;
|
||||
|
||||
value = addr[0] ;
|
||||
|
||||
switch (value & 0x00FF00FF) {
|
||||
case AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
value = addr[2] ; /* device ID */
|
||||
|
||||
switch (value & 0x00FF00FF) {
|
||||
case (AMD_ID_DL323B & 0x00FF00FF):
|
||||
info->flash_id += FLASH_AMDL323B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x01000000; /* 16 Mb */
|
||||
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* => no or unknown flash */
|
||||
|
||||
}
|
||||
/* set up sector start address table */
|
||||
/* set sector offsets for bottom boot block type */
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00008000;
|
||||
info->start[2] = base + 0x00010000;
|
||||
info->start[3] = base + 0x00018000;
|
||||
info->start[4] = base + 0x00020000;
|
||||
info->start[5] = base + 0x00028000;
|
||||
info->start[6] = base + 0x00030000;
|
||||
info->start[7] = base + 0x00038000;
|
||||
for (i = 8; i < info->sector_count; i++) {
|
||||
info->start[i] = base + ((i-7) * 0x00040000) ;
|
||||
}
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < 23; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
addr = (volatile unsigned long *)(info->start[i]);
|
||||
info->protect[i] = addr[4] & 1 ;
|
||||
}
|
||||
/* Check for protected sectors in the 2nd bank */
|
||||
addr[0x100AAA] = 0xAAAAAAAA ;
|
||||
addr[0x100555] = 0x55555555 ;
|
||||
addr[0x100AAA] = 0x90909090 ;
|
||||
|
||||
for (i = 23; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
addr = (volatile unsigned long *)(info->start[i]);
|
||||
info->protect[i] = addr[4] & 1 ;
|
||||
}
|
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH.
|
||||
*/
|
||||
if (info->flash_id != FLASH_UNKNOWN) {
|
||||
addr = (volatile unsigned long *)info->start[0];
|
||||
|
||||
*addr = 0xF0F0F0F0; /* reset bank 1 */
|
||||
addr = (volatile unsigned long *)info->start[23];
|
||||
|
||||
*addr = 0xF0F0F0F0; /* reset bank 2 */
|
||||
|
||||
}
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
vu_long *addr = (vu_long*)(info->start[0]);
|
||||
int flag, prot, sect, l_sect;
|
||||
ulong start, now, last;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if ((info->flash_id == FLASH_UNKNOWN) ||
|
||||
(info->flash_id > FLASH_AMD_COMP)) {
|
||||
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
||||
info->flash_id);
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0xAAA] = 0xAAAAAAAA;
|
||||
addr[0x555] = 0x55555555;
|
||||
addr[0xAAA] = 0x80808080;
|
||||
addr[0xAAA] = 0xAAAAAAAA;
|
||||
addr[0x555] = 0x55555555;
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr = (vu_long *)(info->start[sect]) ;
|
||||
addr[0] = 0x30303030 ;
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
addr = (vu_long *)(info->start[l_sect]);
|
||||
while ((addr[0] & 0x80808080) != 0x80808080) {
|
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
addr = (vu_long *)info->start[0];
|
||||
addr[0] = 0xF0F0F0F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<4 && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i=0; i<4; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
return (write_word(info, wp, data));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
vu_long *addr = (vu_long *)(info->start[0]);
|
||||
ulong start;
|
||||
int flag;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((vu_long *)dest) & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0xAAA] = 0xAAAAAAAA;
|
||||
addr[0x555] = 0x55555555;
|
||||
addr[0xAAA] = 0xA0A0A0A0;
|
||||
|
||||
*((vu_long *)dest) = data;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
|
@ -1,82 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2010
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.text :
|
||||
{
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*)
|
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
|
||||
|
||||
*(.text*)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
_GOT2_TABLE_ = .;
|
||||
KEEP(*(.got2))
|
||||
KEEP(*(.got))
|
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
|
||||
_FIXUP_TABLE_ = .;
|
||||
KEEP(*(.fixup))
|
||||
}
|
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
|
@ -1,121 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib/vsprintf.o (.text)
|
||||
lib/crc32.o (.text)
|
||||
|
||||
. = env_offset;
|
||||
common/env_embedded.o(.text)
|
||||
|
||||
*(.text)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
|
@ -1,8 +0,0 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y = RPXlite.o flash.o
|
|
@ -1,877 +0,0 @@
|
|||
# Porting U-Boot onto RPXlite board
|
||||
# Written by Yoo. Jonghoon
|
||||
# E-Mail : yooth@ipone.co.kr
|
||||
# IP ONE Inc.
|
||||
|
||||
# Since 2001. 1. 29
|
||||
|
||||
# Shell : bash
|
||||
# Cross-compile tools : Montavista Hardhat
|
||||
# Debugging tools : Windriver VisionProbe (PowerPC BDM)
|
||||
# ppcboot ver. : ppcboot-0.8.1
|
||||
|
||||
###############################################################
|
||||
# 1. Hardware setting
|
||||
###############################################################
|
||||
|
||||
1.1. Board, BDM settings
|
||||
Install board, BDM, connect each other
|
||||
|
||||
1.2. Save Register value
|
||||
Boot with board-on monitor program and save the
|
||||
register values with BDM.
|
||||
|
||||
1.3. Configure flash programmer
|
||||
Check flash memory area in the memory map.
|
||||
0xFFC00000 - 0xFFFFFFFF
|
||||
|
||||
Boot monitor program is at
|
||||
0xFFF00000
|
||||
|
||||
You can program on-board flash memory with VisionClick
|
||||
flash programmer. Set the target flash device as:
|
||||
|
||||
29DL800B
|
||||
|
||||
(?) The flash memory device in the board *is* 29LV800B,
|
||||
but I cannot program it with '29LV800B' option.
|
||||
(in VisionClick flash programming tools)
|
||||
I don't know why...
|
||||
|
||||
1.4. Save boot monitor program *IMPORTANT*
|
||||
Upload boot monitor program from board to file.
|
||||
boot monitor program starts at 0xFFF00000
|
||||
|
||||
1.5. Test flash memory programming
|
||||
Try to erase boot program in the flash memory,
|
||||
and re-write them.
|
||||
*WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE
|
||||
BEFORE ERASING FLASH
|
||||
|
||||
###############################################################
|
||||
# 2. U-Boot setting
|
||||
###############################################################
|
||||
|
||||
2.1. Download U-Boot tarball at
|
||||
ftp://ftp.denx.de
|
||||
(The latest version is ppcboot-0.8.1.tar.bz2)
|
||||
|
||||
To extract the archive use the following syntax :
|
||||
> bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf -
|
||||
|
||||
2.2. Add the following lines in '.profile'
|
||||
export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin
|
||||
|
||||
2.3. Make board specific config, for example:
|
||||
> cd ppcboot-0.8.1
|
||||
> make TQM860L_config
|
||||
|
||||
Now we can build ppcboot bin files.
|
||||
After make all, you must see these files in your
|
||||
ppcboot root directory.
|
||||
|
||||
ppcboot
|
||||
ppcboot.bin
|
||||
ppcboot.srec
|
||||
ppcboot.map
|
||||
|
||||
2.4. Make your own board directory into the
|
||||
ppcboot-0.8.1/board
|
||||
and make your board-specific files here.
|
||||
|
||||
For exmanple, tqm8xx files are composed of
|
||||
.depend : Nothing
|
||||
Makefile : To make config file
|
||||
config.mk : Sets base address
|
||||
flash.c : Flash memory control files
|
||||
ppcboot.lds : linker(ld) script? (I don't know this yet)
|
||||
tqm8xx.c : DRAM control and board check routines
|
||||
|
||||
And, add your board config lines in the
|
||||
ppcboot-0.8.1/Makefile
|
||||
|
||||
Finally, add config_(your board).h file in the
|
||||
ppcboot-0.8.1/include/
|
||||
|
||||
I've made board/rpxlite directory, and just copied
|
||||
tqm8xx settings for now.
|
||||
|
||||
Rebuild ppcboot for rpxlite board:
|
||||
> make rpxlite_config
|
||||
> make
|
||||
|
||||
###############################################################
|
||||
# 3. U-Boot porting
|
||||
###############################################################
|
||||
|
||||
3.1. My RPXlite files are based on tqm8xx board files.
|
||||
> cd board
|
||||
> cp -r tqm8xx RPXLITE
|
||||
> cd RPXLITE
|
||||
> mv tqm8xx.c RPXLITE.c
|
||||
> cd ../../include
|
||||
> cp config_tqm8xx.h config_RPXLITE.h
|
||||
|
||||
3.2. Modified files are:
|
||||
board/RPXLITE/RPXLITE.c /* DRAM-related routines */
|
||||
board/RPXLITE/flash.c /* flash-related routines */
|
||||
board/RPXLITE/config.mk /* set text base address */
|
||||
arch/powerpc/cpu/mpc8xx/serial.c /* board specific register setting */
|
||||
include/config_RPXLITE.h /* board specific registers */
|
||||
|
||||
See 'reg_config.txt' for register values in detail.
|
||||
|
||||
###############################################################
|
||||
# 4. Running Linux
|
||||
###############################################################
|
||||
|
||||
|
||||
###############################################################
|
||||
# Misc Information
|
||||
###############################################################
|
||||
|
||||
mem_config.txt:
|
||||
===============
|
||||
|
||||
Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device
|
||||
manufacturer id : 01 (AMD)
|
||||
device id : 5B (AM29LV800B)
|
||||
size : 4Mbyte
|
||||
sector # : 19
|
||||
|
||||
Sector information :
|
||||
|
||||
number start addr. size
|
||||
00 FFC0_0000 64
|
||||
01 FFC1_0000 32
|
||||
02 FFC1_8000 32
|
||||
03 FFC2_0000 128
|
||||
04 FFC4_0000 256
|
||||
05 FFC8_0000 256
|
||||
06 FFCC_0000 256
|
||||
07 FFD0_0000 256
|
||||
08 FFD4_0000 256
|
||||
09 FFD8_0000 256
|
||||
10 FFDC_0000 256
|
||||
11 FFE0_0000 256
|
||||
12 FFE4_0000 256
|
||||
13 FFE8_0000 256
|
||||
14 FFEC_0000 256
|
||||
15 FFF0_0000 256
|
||||
16 FFF4_0000 256
|
||||
17 FFF8_0000 256
|
||||
18 FFFC_0000 256
|
||||
|
||||
|
||||
reg_config.txt:
|
||||
===============
|
||||
|
||||
|
||||
/*------------------------------------------------------------------- */
|
||||
/*------------------------------------------------------------------- */
|
||||
/* SIU (System Interface Unit) */
|
||||
/* */
|
||||
/*------------------------------------------------------------------- */
|
||||
/*------------------------------------------------------------------- */
|
||||
|
||||
|
||||
/*### IMMR */
|
||||
/*### Internal Memory Map Register */
|
||||
/*### Chap. 11.4.1 */
|
||||
|
||||
ISB = 0xFA20 /* Set the Immap base = 0xFA20 0000 */
|
||||
PARTNUM = 0x21
|
||||
MASKNUM = 0x00
|
||||
|
||||
=> 0xFA20 2100
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### SIUMCR */
|
||||
/*### SIU Module Configuration Register */
|
||||
/*### Chap. 11.4.2 */
|
||||
/*### Offset : 0x0000 0000 */
|
||||
|
||||
EARB = 0
|
||||
EARP = 0
|
||||
DSHW = 0
|
||||
DBGC = 0
|
||||
DBPC = 0
|
||||
FRC = 0
|
||||
DLK = 0
|
||||
OPAR = 0
|
||||
PNCS = 0
|
||||
DPC = 0
|
||||
MPRE = 0
|
||||
MLRC = 10 /* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */
|
||||
AEME = 0
|
||||
SEME = 0
|
||||
BSC = 0
|
||||
GB5E = 0
|
||||
B2DD = 0
|
||||
B3DD = 0
|
||||
|
||||
=> 0x0000 0800
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### SYPCR */
|
||||
/*### System Protection Control Register */
|
||||
/*### Chap. 11.4.3 */
|
||||
/*### Offset : 0x0000 0004 */
|
||||
|
||||
SWTC = 0xFFFF /* SW watchdog timer count = 0xFFFF */
|
||||
BMT = 0x06 /* BUS monitoring timing */
|
||||
BME = 1 /* BUS monitor enable */
|
||||
SWF = 1
|
||||
SWE = 0 /* SW watchdog disable */
|
||||
SWRI = 0
|
||||
SWP = 1
|
||||
|
||||
=> 0xFFFF 0689
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### TESR */
|
||||
/*### Transfer Error Status Register */
|
||||
/*### Chap. 11.4.4 */
|
||||
/*### Offset : 0x0000 0020 */
|
||||
|
||||
IEXT = 0
|
||||
ITMT = 0
|
||||
IPB = 0000
|
||||
DEXT = 0
|
||||
DTMT = 0
|
||||
DPB = 0000
|
||||
|
||||
=> 0x0000 0000
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### SIPEND */
|
||||
/*### SIU Interrupt Pending Register */
|
||||
/*### Chap. 11.5.4.1 */
|
||||
/*### Offset : 0x0000 0010 */
|
||||
|
||||
IRQ0~IRQ7 = 0
|
||||
LVL0~LVL7 = 0
|
||||
|
||||
=> 0x0000 0000
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### SIMASK */
|
||||
/*### SIU Interrupt Mask Register */
|
||||
/*### Chap. 11.5.4.2 */
|
||||
/*### Offset : 0x0000 0014 */
|
||||
|
||||
IRM0~IRM7 = 0 /* Mask all interrupts */
|
||||
LVL0~LVL7 = 0
|
||||
|
||||
=> 0x0000 0000
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### SIEL */
|
||||
/*### SIU Interrupt Edge/Level Register */
|
||||
/*### Chap. 11.5.4.3 */
|
||||
/*### Offset : 0x0000 0018 */
|
||||
|
||||
ED0~ED7 = 0 /* Low level triggered */
|
||||
WMn0~WMn7 = 0 /* Not allowed to exit from low-power mode */
|
||||
|
||||
=> 0x0000 0000
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### SIVEC */
|
||||
/*### SIU Interrupt Vector Register */
|
||||
/*### Chap. 11.5.4.4 */
|
||||
/*### Offset : 0x0000 001C */
|
||||
|
||||
INTC = 3C /* The lowest interrupt is pending..(?) */
|
||||
|
||||
=> 0x3C00 0000
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### SWSR */
|
||||
/*### Software Service Register */
|
||||
/*### Chap. 11.7.1 */
|
||||
/*### Offset : 0x0000 001E */
|
||||
|
||||
SEQ = 0
|
||||
|
||||
=> 0x0000
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### SDCR */
|
||||
/*### SDMA Configuration Register */
|
||||
/*### Chap. 20.2.1 */
|
||||
/*### Offset : 0x0000 0032 */
|
||||
|
||||
FRZ = 0
|
||||
RAID = 01 /* Priority level 5 (BR5) (normal operation) */
|
||||
|
||||
=> 0x0000 0001
|
||||
|
||||
|
||||
/*------------------------------------------------------------------- */
|
||||
/*------------------------------------------------------------------- */
|
||||
/* UPMA (User Programmable Machine A) */
|
||||
/* */
|
||||
/*------------------------------------------------------------------- */
|
||||
/*------------------------------------------------------------------- */
|
||||
|
||||
/*### Chap. 16.6.4.1 */
|
||||
/*### Offset = 0x0000 017c */
|
||||
|
||||
T0 = CFFF CC24 /* Single Read */
|
||||
T1 = 0FFF CC04
|
||||
T2 = 0CAF CC04
|
||||
T3 = 03AF CC08
|
||||
T4 = 3FBF CC27 /* last */
|
||||
T5 = FFFF CC25
|
||||
T6 = FFFF CC25
|
||||
T7 = FFFF CC25
|
||||
T8 = CFFF CC24 /* Burst Read */
|
||||
T9 = 0FFF CC04
|
||||
T10 = 0CAF CC84
|
||||
T11 = 03AF CC88
|
||||
T12 = 3FBF CC27 /* last */
|
||||
T13 = FFFF CC25
|
||||
T14 = FFFF CC25
|
||||
T15 = FFFF CC25
|
||||
T16 = FFFF CC25
|
||||
T17 = FFFF CC25
|
||||
T18 = FFFF CC25
|
||||
T19 = FFFF CC25
|
||||
T20 = FFFF CC25
|
||||
T21 = FFFF CC25
|
||||
T22 = FFFF CC25
|
||||
T23 = FFFF CC25
|
||||
T24 = CFFF CC24 /* Single Write */
|
||||
T25 = 0FFF CC04
|
||||
T26 = 0CFF CC04
|
||||
T27 = 03FF CC00
|
||||
T28 = 3FFF CC27 /* last */
|
||||
T29 = FFFF CC25
|
||||
T30 = FFFF CC25
|
||||
T31 = FFFF CC25
|
||||
T32 = CFFF CC24 /* Burst Write */
|
||||
T33 = 0FFF CC04
|
||||
T34 = 0CFF CC80
|
||||
T35 = 03FF CC8C
|
||||
T36 = 0CFF CC00
|
||||
T37 = 33FF CC27 /* last */
|
||||
T38 = FFFF CC25
|
||||
T39 = FFFF CC25
|
||||
T40 = FFFF CC25
|
||||
T41 = FFFF CC25
|
||||
T42 = FFFF CC25
|
||||
T43 = FFFF CC25
|
||||
T44 = FFFF CC25
|
||||
T45 = FFFF CC25
|
||||
T46 = FFFF CC25
|
||||
T47 = FFFF CC25
|
||||
T48 = C0FF CC24 /* Refresh */
|
||||
T49 = 03FF CC24
|
||||
T50 = 0FFF CC24
|
||||
T51 = 0FFF CC24
|
||||
T52 = 3FFF CC27 /* last */
|
||||
T53 = FFFF CC25
|
||||
T54 = FFFF CC25
|
||||
T55 = FFFF CC25
|
||||
T56 = FFFF CC25
|
||||
T57 = FFFF CC25
|
||||
T58 = FFFF CC25
|
||||
T59 = FFFF CC25
|
||||
T60 = FFFF CC25 /* Exception */
|
||||
T61 = FFFF CC25
|
||||
T62 = FFFF CC25
|
||||
T63 = FFFF CC25
|
||||
|
||||
|
||||
/*------------------------------------------------------------------- */
|
||||
/*------------------------------------------------------------------- */
|
||||
/* UPMB */
|
||||
/* */
|
||||
/*------------------------------------------------------------------- */
|
||||
/*------------------------------------------------------------------- */
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### Chap. 16.6.4.1 */
|
||||
|
||||
|
||||
/*------------------------------------------------------------------- */
|
||||
/*------------------------------------------------------------------- */
|
||||
/* MEMC */
|
||||
/* */
|
||||
/*------------------------------------------------------------------- */
|
||||
/*------------------------------------------------------------------- */
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### BR0 & OR0 */
|
||||
/*### Base Registers & Option Registers */
|
||||
/*### Chap. 16.4.1 & 16.4.2 */
|
||||
/*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */
|
||||
/*### Flash memory */
|
||||
|
||||
BA = 1111 1110 0000 0000 0 /* Base addr = 0xFE00 0000 */
|
||||
AT = 000
|
||||
PS = 00
|
||||
PARE = 0
|
||||
WP = 0
|
||||
MS = 0 /* GPCM */
|
||||
V = 1 /* Valid */
|
||||
|
||||
=> 0xFE00 0001
|
||||
|
||||
AM = 1111 1110 0000 0000 0 /* 32MBytes */
|
||||
ATM = 000
|
||||
CSNT/SAM = 0
|
||||
ACS/G5LA,G5LS = 00
|
||||
BIH = 1 /* Burst inhibited */
|
||||
SCY = 0100 /* cycle length = 4 */
|
||||
SETA = 0
|
||||
TRLX = 0
|
||||
EHTR = 0
|
||||
|
||||
=> 0xFE00 0140
|
||||
|
||||
/*### BR1 & OR1 */
|
||||
/*### Base Registers & Option Registers */
|
||||
/*### Chap. 16.4.1 & 16.4.2 */
|
||||
/*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */
|
||||
/*### SDRAM */
|
||||
|
||||
BA = 0000 0000 0000 0000 0 /* Base addr = 0x0000 0000 */
|
||||
AT = 000
|
||||
PS = 00
|
||||
PARE = 0
|
||||
WP = 0
|
||||
MS = 1 /* UPMA */
|
||||
V = 1 /* Valid */
|
||||
|
||||
=> 0x0000 0081
|
||||
|
||||
AM = 1111 1110 0000 0000 /* 32MBytes */
|
||||
ATM = 000
|
||||
CSNT/SAM = 1
|
||||
ACS/G5LA,G5LS = 11
|
||||
BIH = 0
|
||||
SCY = 0000 /* cycle length = 0 */
|
||||
SETA = 0
|
||||
TRLX = 0
|
||||
EHTR = 0
|
||||
|
||||
=> 0xFE00 0E00
|
||||
|
||||
/*### BR2 & OR2 */
|
||||
/*### Base Registers & Option Registers */
|
||||
/*### Chap. 16.4.1 & 16.4.2 */
|
||||
/*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */
|
||||
|
||||
BR2 & OR2 = 0x0000 0000 /* Not used */
|
||||
|
||||
/*### BR3 & OR3 */
|
||||
/*### Base Registers & Option Registers */
|
||||
/*### Chap. 16.4.1 & 16.4.2 */
|
||||
/*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */
|
||||
/*### BCSR */
|
||||
|
||||
BA = 1111 1010 0100 0000 0 /* Base addr = 0xFA40 0000 */
|
||||
AT = 000
|
||||
PS = 00
|
||||
PARE = 0
|
||||
WP = 0
|
||||
MS = 0 /* GPCM */
|
||||
V = 1 /* Valid */
|
||||
|
||||
=> 0xFA40 0001
|
||||
|
||||
AM = 1111 1111 0111 1111 1 /* (?) */
|
||||
ATM = 000
|
||||
CSNT/SAM = 1
|
||||
ACS/G5LA,G5LS = 00
|
||||
BIH = 1 /* Burst inhibited */
|
||||
SCY = 0001 /* cycle length = 1 */
|
||||
SETA = 0
|
||||
TRLX = 0
|
||||
|
||||
=> 0xFF7F 8910
|
||||
|
||||
/*### BR4 & OR4 */
|
||||
/*### Base Registers & Option Registers */
|
||||
/*### Chap. 16.4.1 & 16.4.2 */
|
||||
/*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */
|
||||
/*### NVRAM & SRAM */
|
||||
|
||||
BA = 1111 1010 0000 0000 0 /* Base addr = 0xFA00 0000 */
|
||||
AT = 000
|
||||
PS = 01
|
||||
PARE = 0
|
||||
WP = 0
|
||||
MS = 0 /* GPCM */
|
||||
V = 1 /* Valid */
|
||||
|
||||
=> 0xFA00 0401
|
||||
|
||||
AM = 1111 1111 1111 1000 0 /* 8MByte */
|
||||
ATM = 000
|
||||
CSNT/SAM = 1
|
||||
ACS/G5LA,G5LS = 00
|
||||
BIH = 1 /* Burst inhibited */
|
||||
SCY = 0111 /* cycle length = 7 */
|
||||
SETA = 0
|
||||
TRLX = 0
|
||||
|
||||
=> 0xFFF8 0970
|
||||
|
||||
/*### BR5 & OR5 */
|
||||
/*### Base Registers & Option Registers */
|
||||
/*### Chap. 16.4.1 & 16.4.2 */
|
||||
/*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */
|
||||
|
||||
BR5 & OR5 = 0x0000 0000 /* Not used */
|
||||
|
||||
/*### BR6 & OR6 */
|
||||
/*### Base Registers & Option Registers */
|
||||
/*### Chap. 16.4.1 & 16.4.2 */
|
||||
/*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */
|
||||
|
||||
BR6 & OR6 = 0x0000 0000 /* Not used */
|
||||
|
||||
/*### BR7 & OR7 */
|
||||
/*### Base Registers & Option Registers */
|
||||
/*### Chap. 16.4.1 & 16.4.2 */
|
||||
/*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */
|
||||
|
||||
BR7 & OR7 = 0x0000 0000 /* Not used */
|
||||
|
||||
/*### MAR */
|
||||
/*### Memory Address Register */
|
||||
/*### Chap. 16.4.7 */
|
||||
/*### Offset : 0x0000 0164 */
|
||||
|
||||
MA = External memory address
|
||||
|
||||
/*### MCR */
|
||||
/*### Memory Command Register */
|
||||
/*### Chap. 16.4.5 */
|
||||
/*### Offset : 0x0000 0168 */
|
||||
|
||||
OP = xx /* Command op code */
|
||||
UM = 1 /* Select UPMA */
|
||||
MB = 001 /* Select CS1 */
|
||||
MCLF = xxxx /* Loop times */
|
||||
MAD = xx xxxx /* Memory array index */
|
||||
|
||||
/*### MAMR */
|
||||
/*### Machine A Mode Register */
|
||||
/*### Chap. 16.4.4 */
|
||||
/*### Offset : 0x0000 0170 */
|
||||
|
||||
PTA = 0101 1000
|
||||
PTAE = 1 /* Periodic timer A enabled */
|
||||
AMA = 010
|
||||
DSA = 00
|
||||
G0CLA = 000
|
||||
GPLA4DIS = 1
|
||||
RLFA = 0100
|
||||
WLFA = 0011
|
||||
TLFA = 0000
|
||||
|
||||
=> 0x58A0 1430
|
||||
|
||||
/*### MBMR */
|
||||
/*### Machine B Mode Register */
|
||||
/*### Chap. 16.4.4 */
|
||||
/*### Offset : 0x0000 0174 */
|
||||
|
||||
PTA = 0100 1110
|
||||
PTAE = 0 /* Periodic timer B disabled */
|
||||
AMA = 000
|
||||
DSA = 00
|
||||
G0CLA = 000
|
||||
GPLA4DIS = 1
|
||||
RLFA = 0000
|
||||
WLFA = 0000
|
||||
TLFA = 0000
|
||||
|
||||
=> 0x4E00 1000
|
||||
|
||||
/*### MSTAT */
|
||||
/*### Memory Status Register */
|
||||
/*### Chap. 16.4.3 */
|
||||
/*### Offset : 0x0000 0178 */
|
||||
|
||||
PER0~PER7 = Parity error
|
||||
WPER = Write protection error
|
||||
|
||||
=> 0x0000
|
||||
|
||||
/*### MPTPR */
|
||||
/*### Memory Periodic Timer Prescaler Register */
|
||||
/*### Chap. 16.4.8 */
|
||||
/*### Offset : 0x0000 017A */
|
||||
|
||||
PTP = 0000 1000 /* Divide by 8 */
|
||||
|
||||
=> 0x0800
|
||||
|
||||
/*### MDR */
|
||||
/*### Memory Data Register */
|
||||
/*### Chap. 16.4.6 */
|
||||
/*### Offset : 0x0000 017C */
|
||||
|
||||
MD = Memory data contains the RAM array word
|
||||
|
||||
|
||||
/*------------------------------------------------------------------- */
|
||||
/*------------------------------------------------------------------- */
|
||||
/* TIMERS */
|
||||
/* */
|
||||
/*------------------------------------------------------------------- */
|
||||
/*------------------------------------------------------------------- */
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### TBREFx */
|
||||
/*### Timebase Reference Registers */
|
||||
/*### Chap. 11.9.2 */
|
||||
/*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */
|
||||
/*### (Locked) */
|
||||
|
||||
TBREFF0 = 0xFFFF FFFF
|
||||
TBREFF1 = 0xFFFF FFFF
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### TBSCR */
|
||||
/*### Timebase Status and Control Registers */
|
||||
/*### Chap. 11.9.3 */
|
||||
/*### Offset : 0x0000 0200 */
|
||||
/*### (Locked) */
|
||||
|
||||
TBIRQ = 00000000
|
||||
REF0 = 0
|
||||
REF1 = 0
|
||||
REFE0 = 0 /* Reference interrupt disable */
|
||||
REFE1 = 0
|
||||
TBF = 1
|
||||
TBE = 1 /* Timebase enable */
|
||||
|
||||
=> 0x0003
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### RTCSC */
|
||||
/*### Real-Time Clock Status and Control Registers */
|
||||
/*### Chap. 11.10.1 */
|
||||
/*### Offset : 0x0000 0220 */
|
||||
/*### (Locked) */
|
||||
|
||||
RTCIRQ = 00000000
|
||||
SEC = 1
|
||||
ALR = 0
|
||||
38K = 0 /* PITRTCLK is driven by 32.768KHz */
|
||||
SIE = 0
|
||||
ALE = 0
|
||||
RTF = 0
|
||||
RTE = 1 /* Real-Time clock enabled */
|
||||
|
||||
=> 0x0081
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### RTC */
|
||||
/*### Real-Time Clock Registers */
|
||||
/*### Chap. 11.10.2 */
|
||||
/*### Offset : 0x0000 0224 */
|
||||
/*### (Locked) */
|
||||
|
||||
RTC = Real time clock measured in second
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### RTCAL */
|
||||
/*### Real-Time Clock Alarm Registers */
|
||||
/*### Chap. 11.10.3 */
|
||||
/*### Offset : 0x0000 022C */
|
||||
/*### (Locked) */
|
||||
|
||||
ALARM = 0xFFFF FFFF
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### RTSEC */
|
||||
/*### Real-Time Clock Alarm Second Registers */
|
||||
/*### Chap. 11.10.4 */
|
||||
/*### Offset : 0x0000 0228 */
|
||||
/*### (Locked) */
|
||||
|
||||
COUNTER = Counter bits(fraction of a second)
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### PISCR */
|
||||
/*### Periodic Interrupt Status and Control Register */
|
||||
/*### Chap. 11.11.1 */
|
||||
/*### Offset : 0x0000 0240 */
|
||||
/*### (Locked) */
|
||||
|
||||
PIRQ = 0
|
||||
PS = 0 /* Write 1 to clear */
|
||||
PIE = 0
|
||||
PITF = 1
|
||||
PTE = 0 /* PIT disabled */
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### PITC */
|
||||
/*### PIT Count Register */
|
||||
/*### Chap. 11.11.2 */
|
||||
/*### Offset : 0x0000 0244 */
|
||||
/*### (Locked) */
|
||||
|
||||
PITC = PIT count
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### PITR */
|
||||
/*### PIT Register */
|
||||
/*### Chap. 11.11.3 */
|
||||
/*### Offset : 0x0000 0248 */
|
||||
/*### (Locked) */
|
||||
|
||||
PIT = PIT count /* Read only */
|
||||
|
||||
|
||||
/*------------------------------------------------------------------- */
|
||||
/*------------------------------------------------------------------- */
|
||||
/* CLOCKS */
|
||||
/* */
|
||||
/*------------------------------------------------------------------- */
|
||||
/*------------------------------------------------------------------- */
|
||||
---------------------------------------------------------------------
|
||||
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### SCCR */
|
||||
/*### System Clock and Reset Control Register */
|
||||
/*### Chap. 15.6.1 */
|
||||
/*### Offset : 0x0000 0280 */
|
||||
/*### (Locked) */
|
||||
|
||||
COM = 11 /* Clock output disabled */
|
||||
TBS = 1 /* Timebase frequency source is GCLK2 divided by 16 */
|
||||
RTDIV = 0 /* The clock is divided by 4 */
|
||||
RTSEL = 0 /* OSCM(Crystal oscillator) is selected */
|
||||
CRQEN = 0
|
||||
PRQEN = 0
|
||||
EBDF = 00 /* CLKOUT is GCLK2 divided by 1 */
|
||||
DFSYNC = 00 /* Divided by 1 (normal operation) */
|
||||
DFBRG = 00 /* Divided by 1 (normal operation) */
|
||||
DFNL = 000
|
||||
DFNH = 000
|
||||
|
||||
=> 0x6200 0000
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### PLPRCR */
|
||||
/*### PLL, Low-Power, and Reset Control Register */
|
||||
/*### Chap. 15.6.2 */
|
||||
/*### Offset : 0x0000 0284 */
|
||||
/*### (Locked) */
|
||||
|
||||
MF = 0x005 /* 48MHz (?) ( = 8MHz * (MF+1) ) */
|
||||
SPLSS = 0
|
||||
TEXPS = 0
|
||||
TMIST = 0
|
||||
CSRC = 0 /* The general system clock is generated by the DFNH field */
|
||||
LPM = 00 /* Normal high/normal low mode */
|
||||
CSR = 0
|
||||
LOLRE = 0
|
||||
FIOPD = 0
|
||||
|
||||
=> 0x0050 0000
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### RSR */
|
||||
/*### Reset Status Register */
|
||||
/*### Chap. 12.2 */
|
||||
/*### Offset : 0x0000 0288 */
|
||||
/*### (Locked) */
|
||||
|
||||
EHRS = External hard reset
|
||||
ESRS = External soft reset
|
||||
LLRS = Loss-of-lock reset
|
||||
SWRS = Software watchdog reset
|
||||
CSRS = Check stop reset
|
||||
DBHRS = Debug port hard reset
|
||||
DBSRS = Debug port soft reset
|
||||
JTRS = JTAG reset
|
||||
|
||||
|
||||
/*------------------------------------------------------------------- */
|
||||
/*------------------------------------------------------------------- */
|
||||
/* DMA */
|
||||
/* */
|
||||
/*------------------------------------------------------------------- */
|
||||
/*------------------------------------------------------------------- */
|
||||
---------------------------------------------------------------------
|
||||
|
||||
/*### SDSR */
|
||||
/*### SDMA Status Register */
|
||||
/*### Chap. 20.2.2 */
|
||||
/*### Offset : 0x0000 0908 */
|
||||
|
||||
SBER = 0 /* SDMA channel bus error */
|
||||
DSP2 = 0 /* DSP chain2 (Tx) interrupt */
|
||||
DSP1 = 0 /* DSP chain1 (Rx) interrupt */
|
||||
|
||||
=> 0x00
|
||||
|
||||
/*### SDMR */
|
||||
/*### SDMA Mask Register */
|
||||
/*### Chap. 20.2.3 */
|
||||
/*### Offset : 0x0000 090C */
|
||||
|
||||
SBER = 0
|
||||
DSP2 = 0
|
||||
DSP1 = 0 /* All interrupts are masked */
|
||||
|
||||
=> 0x00
|
||||
|
||||
/*### SDAR */
|
||||
/*### SDMA Address Register */
|
||||
/*### Chap. 20.2.4 */
|
||||
/*### Offset : 0x0000 0904 */
|
||||
|
||||
AR = 0xxxxx xxxx /* current system address */
|
||||
|
||||
=> 0xFA20 23AC
|
||||
|
||||
/*### IDSRx */
|
||||
/*### IDMA Status Register */
|
||||
/*### Chap. 20.3.3.2 */
|
||||
/*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */
|
||||
|
||||
AD = 0
|
||||
DONE = 0
|
||||
OB = 0
|
||||
|
||||
=> 0x00
|
||||
|
||||
/*### IDMRx */
|
||||
/*### IDMA Mask Register */
|
||||
/*### Chap. 20.3.3.3 */
|
||||
/*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */
|
||||
|
||||
AD = 0
|
||||
DONE = 0
|
||||
OB = 0
|
|
@ -1,163 +0,0 @@
|
|||
After several heart-struck failure, I got one workable way to program
|
||||
each other in FLASH between PlanetCore and U-Boot.
|
||||
|
||||
Hardware Platform : RPXlite DW(EP 823 H1 DW)
|
||||
|
||||
1. From U-Boot to PlanetCore
|
||||
|
||||
Utilities : PlanetCore Boot Loader - PCL200.mot
|
||||
|
||||
[root@sam tftpboot]# ppc_8xx-objcopy -O ppcboot
|
||||
PCL200.mot pcl200.bin
|
||||
|
||||
[Target Operation]
|
||||
u-boot>t 100000 pcl200.bin
|
||||
u-boot>go 0x100000
|
||||
## Starting application at 0x00100000 ...
|
||||
|
||||
MPC8xx PlanetCore Flash Burner v2.00
|
||||
Copyright 2001 Embedded Planet. All rights reserved.
|
||||
|
||||
Construct Flash Device.....done.
|
||||
|
||||
|
||||
Program MPC8xx PlanetCore Boot Loader v2.00
|
||||
Built Sep 19, 2001 at 14:34:42
|
||||
Image located from FC000000 to FC01B5D1.
|
||||
(Skipping an image, only loading low boot image)
|
||||
|
||||
Low boot board detected, skipping high boot image.
|
||||
Erasing, programming and verifying will start in 20
|
||||
seconds
|
||||
Press P to start immediately or ESC to cancel
|
||||
Press Space or Enter for more options.
|
||||
..............
|
||||
|
||||
Erasing
|
||||
Programming
|
||||
FLASH programmed successfully!
|
||||
Press R to induce a hard reset
|
||||
|
||||
MPC8xx PlanetCore Boot Loader v2.00
|
||||
Copyright 2001 Embedded Planet. All rights reserved.
|
||||
DRAM available size = 64 MB
|
||||
wvCV
|
||||
DRAM OK
|
||||
>
|
||||
|
||||
2. From PlanetCore to U-Boot
|
||||
|
||||
Utilities : PlanetCore FLASH Burner - PCB200.mot
|
||||
|
||||
Use Flash Burner to finish the work:
|
||||
|
||||
First, TFTP the U-Boot image file to RAM; For example,
|
||||
RPXlite_DW.bin to 0x400000
|
||||
Second, TFTP FLASH Burner to RAM; For example,
|
||||
0x100000
|
||||
Third, run the FLASH Burner and Program the U-Boot
|
||||
image into the correct location in FLASH.
|
||||
|
||||
[Target Operation]
|
||||
MPC8xx PlanetCore Boot Loader v2.00
|
||||
Copyright 2001 Embedded Planet. All rights reserved.
|
||||
DRAM available size = 64 MB
|
||||
wvCV
|
||||
DRAM OK
|
||||
>t
|
||||
Load using tftp via Ethernet
|
||||
Enter server IP address <172.16.115.6> :
|
||||
Enter server filename <PCL200.mot> : RPXlite_DW.bin
|
||||
Enter (B)inary or (S)record input mode <S> : B
|
||||
Enter address offset : <00400000 hex> :
|
||||
|
||||
Total bytes = 120096 in 232184 uSecs
|
||||
Loaded addresses 00400000 through 0041D51F.
|
||||
Start address = 00400000
|
||||
>t
|
||||
Load using tftp via Ethernet
|
||||
Enter server IP address <172.16.115.6> :
|
||||
Enter server filename <RPXlite_DW.bin> : PCB200.mot
|
||||
Enter (B)inary or (S)record input mode <B> : S
|
||||
Enter address offset : <00000000 hex> :
|
||||
.512.1024..2048....4096.....
|
||||
Total bytes = 326280 in 2570249 uSecs
|
||||
Loaded addresses 00100000 through 0011BB51.
|
||||
Start address = 00100000
|
||||
>go
|
||||
[Go 00100000]
|
||||
|
||||
MPC8xx PlanetCore Flash Burner v2.00
|
||||
Copyright 2001 Embedded Planet. All rights reserved.
|
||||
|
||||
Construct Flash Device.....done.
|
||||
|
||||
Bad start address
|
||||
Start = 0xFFFFFFFF, target = 0xFFFFFFFF, length =
|
||||
0xFFFFFFFF
|
||||
Forcing Menu Interface
|
||||
|
||||
h[elp] Show commands.
|
||||
c[ode] Show information on code to be loaded.
|
||||
di[splay] Display all flash sections.
|
||||
du[mp] Dump memory. d ? for more info.
|
||||
e[rase] Erase flash sections.
|
||||
f[ill] Fill flash sections.
|
||||
im[age] Toggle load high, low, or both flash
|
||||
images.
|
||||
in[fo] Show flash information.
|
||||
ma[p] Show memory map.
|
||||
mo[dify] Modify memory. m ? for more info.
|
||||
p[rogram] Erase, program, and verify now.
|
||||
reset Restart the loader.
|
||||
s[how] Show flash sections to erase and program.
|
||||
t[est] Test flash sections.
|
||||
q[uit] Quit without programming.
|
||||
#program 400000 ff000000 1D51F
|
||||
doProgram( 400000 ff000000 1D51F )
|
||||
|
||||
Start = 0x00400000, target = 0xFF000000, length =
|
||||
0x0001D51F
|
||||
Erasing sector 0xFF000000, length 0x008000.
|
||||
Erasing sector 0xFF008000, length 0x008000.
|
||||
Erasing sector 0xFF010000, length 0x008000.
|
||||
Erasing sector 0xFF018000, length 0x008000.
|
||||
Programming FF000000 through FF01D51E
|
||||
FLASH programmed successfully!
|
||||
Press R to induce a hard reset
|
||||
|
||||
Forcing Hard Reset by MachineCheck and
|
||||
ResetOnCheckstop...
|
||||
|
||||
U-Boot 1.1.2 (Aug 29 2004 - 15:11:27)
|
||||
|
||||
CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB
|
||||
D-Cache
|
||||
Board: RPXlite_DW
|
||||
DRAM: 64 MB
|
||||
FLASH: 16 MB
|
||||
*** Warning - bad CRC, using default environment
|
||||
|
||||
In: serial
|
||||
Out: serial
|
||||
Err: serial
|
||||
Net: SCC ETHERNET
|
||||
u-boot>
|
||||
|
||||
-------------------------------------------------
|
||||
|
||||
Well, sometimes network function of PlanetCore couldn't work when
|
||||
switching from U-Boot to PlanetCore. For example, you couldn't
|
||||
download a file from HOST PC via TFTP. Don't worry, just restart your
|
||||
HOST PC and everything would work as smooth as clockwork. I don't
|
||||
know the reason WHY:-)
|
||||
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
Merry Christmas and Happy New Year!
|
||||
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
=====
|
||||
Best regards,
|
||||
|
||||
Sam
|
|
@ -1,149 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
|
||||
* U-Boot port on RPXlite board
|
||||
*
|
||||
* DRAM related UPMA register values are modified.
|
||||
* See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc8xx.h>
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
static long int dram_size (long int, long int *, long int);
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#define _NOT_USED_ 0xFFFFCC25
|
||||
|
||||
const uint sdram_table[] = {
|
||||
/*
|
||||
* Single Read. (Offset 00h in UPMA RAM)
|
||||
*/
|
||||
0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
|
||||
0x3FBFCC27, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
|
||||
/*
|
||||
* Burst Read. (Offset 08h in UPMA RAM)
|
||||
*/
|
||||
0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
|
||||
0x3FBFCC27, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
|
||||
/*
|
||||
* Single Write. (Offset 18h in UPMA RAM)
|
||||
*/
|
||||
0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
|
||||
0x3FFFCC27, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
|
||||
/*
|
||||
* Burst Write. (Offset 20h in UPMA RAM)
|
||||
*/
|
||||
0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
|
||||
0x0CFFCC00, 0x33FFCC27, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_,
|
||||
|
||||
/*
|
||||
* Refresh. (Offset 30h in UPMA RAM)
|
||||
*/
|
||||
0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
|
||||
0x3FFFCC27, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
|
||||
/*
|
||||
* Exception. (Offset 3Ch in UPMA RAM)
|
||||
*/
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
|
||||
};
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
puts ("Board: RPXlite\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
phys_size_t initdram (int board_type)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
long int size10;
|
||||
|
||||
upmconfig (UPMA, (uint *) sdram_table,
|
||||
sizeof (sdram_table) / sizeof (uint));
|
||||
|
||||
/* Refresh clock prescalar */
|
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
|
||||
|
||||
memctl->memc_mar = 0x00000000;
|
||||
|
||||
/* Map controller banks 1 to the SDRAM bank */
|
||||
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
|
||||
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
|
||||
|
||||
memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
|
||||
|
||||
udelay (200);
|
||||
|
||||
/* perform SDRAM initializsation sequence */
|
||||
|
||||
memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */
|
||||
udelay (1);
|
||||
|
||||
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
|
||||
|
||||
udelay (1000);
|
||||
|
||||
/* Check Bank 0 Memory Size
|
||||
* try 10 column mode
|
||||
*/
|
||||
|
||||
size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
|
||||
SDRAM_MAX_SIZE);
|
||||
|
||||
return (size10);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Check memory range for valid RAM. A simple memory test determines
|
||||
* the actually available RAM size between addresses `base' and
|
||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
||||
* - short between address lines
|
||||
* - short between data lines
|
||||
*/
|
||||
|
||||
static long int dram_size (long int mamr_value, long int *base,
|
||||
long int maxsize)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
|
||||
memctl->memc_mamr = mamr_value;
|
||||
|
||||
return (get_ram_size (base, maxsize));
|
||||
}
|
|
@ -1,508 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
|
||||
* U-Boot port on RPXlite board
|
||||
*
|
||||
* Some of flash control words are modified. (from 2x16bit device
|
||||
* to 4x8bit device)
|
||||
* RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
|
||||
* are not tested.
|
||||
*
|
||||
* (?) Does an RPXLite board which
|
||||
* does not use AM29LV800 flash memory exist ?
|
||||
* I don't know...
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc8xx.h>
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data);
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
/* volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; */
|
||||
/* volatile memctl8xx_t *memctl = &immap->im_memctl; */
|
||||
unsigned long size_b0 ;
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
/*
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE_DEBUG, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0<<20);
|
||||
}
|
||||
*/
|
||||
/* Remap FLASH according to real size */
|
||||
/*%%%
|
||||
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
|
||||
memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
|
||||
%%%*/
|
||||
/* Re-do sizing to get full correct info */
|
||||
|
||||
size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
|
||||
flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
|
||||
|
||||
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
|
||||
/* monitor protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_SYS_MONITOR_BASE,
|
||||
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* set up sector start address table */
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00010000;
|
||||
info->start[2] = base + 0x00018000;
|
||||
info->start[3] = base + 0x00020000;
|
||||
for (i = 4; i < info->sector_count; i++) {
|
||||
info->start[i] = base + ((i-3) * 0x00040000) ;
|
||||
}
|
||||
} else {
|
||||
/* set sector offsets for top boot block type */
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = base + info->size - 0x00010000;
|
||||
info->start[i--] = base + info->size - 0x00018000;
|
||||
info->start[i--] = base + info->size - 0x00020000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = base + i * 0x00040000;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD: printf ("AMD "); break;
|
||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
|
||||
default: printf ("Unknown Vendor "); break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
|
||||
break;
|
||||
default: printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i=0; i<info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " "
|
||||
);
|
||||
}
|
||||
printf ("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
|
||||
{
|
||||
short i;
|
||||
ulong value;
|
||||
ulong base = (ulong)addr;
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
addr[0xAAA] = 0x00AA00AA ;
|
||||
addr[0x555] = 0x00550055 ;
|
||||
addr[0xAAA] = 0x00900090 ;
|
||||
|
||||
value = addr[0] ;
|
||||
|
||||
switch (value & 0x00FF00FF) {
|
||||
case AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
case FUJ_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_FUJ;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
value = addr[2] ; /* device ID */
|
||||
|
||||
switch (value & 0x00FF00FF) {
|
||||
case (AMD_ID_LV400T & 0x00FF00FF):
|
||||
info->flash_id += FLASH_AM400T;
|
||||
info->sector_count = 11;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
|
||||
case (AMD_ID_LV400B & 0x00FF00FF):
|
||||
info->flash_id += FLASH_AM400B;
|
||||
info->sector_count = 11;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
|
||||
case (AMD_ID_LV800T & 0x00FF00FF):
|
||||
info->flash_id += FLASH_AM800T;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
|
||||
case (AMD_ID_LV800B & 0x00FF00FF):
|
||||
info->flash_id += FLASH_AM800B;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00400000; /*%%% Size doubled by yooth */
|
||||
break; /* => 4 MB */
|
||||
|
||||
case (AMD_ID_LV160T & 0x00FF00FF):
|
||||
info->flash_id += FLASH_AM160T;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 4 MB */
|
||||
|
||||
case (AMD_ID_LV160B & 0x00FF00FF):
|
||||
info->flash_id += FLASH_AM160B;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 4 MB */
|
||||
#if 0 /* enable when device IDs are available */
|
||||
case AMD_ID_LV320T:
|
||||
info->flash_id += FLASH_AM320T;
|
||||
info->sector_count = 67;
|
||||
info->size = 0x00800000;
|
||||
break; /* => 8 MB */
|
||||
|
||||
case AMD_ID_LV320B:
|
||||
info->flash_id += FLASH_AM320B;
|
||||
info->sector_count = 67;
|
||||
info->size = 0x00800000;
|
||||
break; /* => 8 MB */
|
||||
#endif
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* => no or unknown flash */
|
||||
|
||||
}
|
||||
/*%%% sector start address modified */
|
||||
/* set up sector start address table */
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00010000;
|
||||
info->start[2] = base + 0x00018000;
|
||||
info->start[3] = base + 0x00020000;
|
||||
for (i = 4; i < info->sector_count; i++) {
|
||||
info->start[i] = base + ((i-3) * 0x00040000) ;
|
||||
}
|
||||
} else {
|
||||
/* set sector offsets for top boot block type */
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = base + info->size - 0x00010000;
|
||||
info->start[i--] = base + info->size - 0x00018000;
|
||||
info->start[i--] = base + info->size - 0x00020000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = base + i * 0x00040000;
|
||||
}
|
||||
}
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
addr = (volatile unsigned long *)(info->start[i]);
|
||||
info->protect[i] = addr[4] & 1 ;
|
||||
}
|
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH.
|
||||
*/
|
||||
if (info->flash_id != FLASH_UNKNOWN) {
|
||||
addr = (volatile unsigned long *)info->start[0];
|
||||
|
||||
*addr = 0xF0F0F0F0; /* reset bank */
|
||||
}
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
vu_long *addr = (vu_long*)(info->start[0]);
|
||||
int flag, prot, sect, l_sect;
|
||||
ulong start, now, last;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if ((info->flash_id == FLASH_UNKNOWN) ||
|
||||
(info->flash_id > FLASH_AMD_COMP)) {
|
||||
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
||||
info->flash_id);
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0xAAA] = 0xAAAAAAAA;
|
||||
addr[0x555] = 0x55555555;
|
||||
addr[0xAAA] = 0x80808080;
|
||||
addr[0xAAA] = 0xAAAAAAAA;
|
||||
addr[0x555] = 0x55555555;
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr = (vu_long *)(info->start[sect]) ;
|
||||
addr[0] = 0x30303030 ;
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
addr = (vu_long *)(info->start[l_sect]);
|
||||
while ((addr[0] & 0x80808080) != 0x80808080) {
|
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
addr = (vu_long *)info->start[0];
|
||||
addr[0] = 0xF0F0F0F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<4 && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i=0; i<4; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
return (write_word(info, wp, data));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
vu_long *addr = (vu_long *)(info->start[0]);
|
||||
ulong start;
|
||||
int flag;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((vu_long *)dest) & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0xAAA] = 0xAAAAAAAA;
|
||||
addr[0x555] = 0x55555555;
|
||||
addr[0xAAA] = 0xA0A0A0A0;
|
||||
|
||||
*((vu_long *)dest) = data;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
|
@ -1,82 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2010
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.text :
|
||||
{
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*)
|
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
|
||||
|
||||
*(.text*)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
_GOT2_TABLE_ = .;
|
||||
KEEP(*(.got2))
|
||||
KEEP(*(.got))
|
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
|
||||
_FIXUP_TABLE_ = .;
|
||||
KEEP(*(.fixup))
|
||||
}
|
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
|
@ -1,121 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib/vsprintf.o (.text)
|
||||
lib/crc32.o (.text)
|
||||
|
||||
. = env_offset;
|
||||
common/env_embedded.o(.text)
|
||||
|
||||
*(.text)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
|
@ -1,174 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#if defined(CONFIG_NIOS)
|
||||
#include <nios.h>
|
||||
#else
|
||||
#include <asm/io.h>
|
||||
#endif
|
||||
|
||||
#define SECTSZ (64 * 1024)
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
int i;
|
||||
unsigned long addr;
|
||||
flash_info_t *fli = &flash_info[0];
|
||||
|
||||
fli->size = CONFIG_SYS_FLASH_SIZE;
|
||||
fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
|
||||
fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
|
||||
|
||||
addr = CONFIG_SYS_FLASH_BASE;
|
||||
for (i = 0; i < fli->sector_count; ++i) {
|
||||
fli->start[i] = addr;
|
||||
addr += SECTSZ;
|
||||
fli->protect[i] = 1;
|
||||
}
|
||||
|
||||
return (CONFIG_SYS_FLASH_SIZE);
|
||||
}
|
||||
/*--------------------------------------------------------------------*/
|
||||
void flash_print_info (flash_info_t * info)
|
||||
{
|
||||
int i, k;
|
||||
int erased;
|
||||
unsigned long *addr;
|
||||
|
||||
printf (" Size: %ld KB in %d Sectors\n",
|
||||
info->size >> 10, info->sector_count);
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
|
||||
/* Check if whole sector is erased */
|
||||
erased = 1;
|
||||
addr = (unsigned long *) info->start[i];
|
||||
for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) {
|
||||
if ( readl(addr++) != (unsigned long)-1) {
|
||||
erased = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Print the info */
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s%s",
|
||||
info->start[i],
|
||||
erased ? " E" : " ",
|
||||
info->protect[i] ? "RO " : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------------*/
|
||||
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
unsigned char *addr = (unsigned char *) info->start[0];
|
||||
unsigned char *addr2;
|
||||
int prot, sect;
|
||||
ulong start;
|
||||
|
||||
/* Some sanity checking */
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
printf ("- no sectors to erase\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
/* It's ok to erase multiple sectors provided we don't delay more
|
||||
* than 50 usec between cmds ... at which point the erase time-out
|
||||
* occurs. So don't go and put printf() calls in the loop ... it
|
||||
* won't be very helpful ;-)
|
||||
*/
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr2 = (unsigned char *) info->start[sect];
|
||||
writeb (0xaa, addr);
|
||||
writeb (0x55, addr);
|
||||
writeb (0x80, addr);
|
||||
writeb (0xaa, addr);
|
||||
writeb (0x55, addr);
|
||||
writeb (0x30, addr2);
|
||||
/* Now just wait for 0xff & provide some user
|
||||
* feedback while we wait.
|
||||
*/
|
||||
start = get_timer (0);
|
||||
while ( readb (addr2) != 0xff) {
|
||||
udelay (1000 * 1000);
|
||||
putc ('.');
|
||||
if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("timeout\n");
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
printf ("\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
|
||||
vu_char *cmd = (vu_char *) info->start[0];
|
||||
vu_char *dst = (vu_char *) addr;
|
||||
unsigned char b;
|
||||
ulong start;
|
||||
|
||||
while (cnt) {
|
||||
/* Check for sufficient erase */
|
||||
b = *src;
|
||||
if ((readb (dst) & b) != b) {
|
||||
printf ("%02x : %02x\n", readb (dst), b);
|
||||
return (2);
|
||||
}
|
||||
|
||||
writeb (0xaa, cmd);
|
||||
writeb (0x55, cmd);
|
||||
writeb (0xa0, cmd);
|
||||
writeb (b, dst);
|
||||
|
||||
/* Verify write */
|
||||
start = get_timer (0);
|
||||
while (readb (dst) != b) {
|
||||
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
dst++;
|
||||
src++;
|
||||
cnt--;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
|
@ -1,180 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#include <nios.h>
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
|
||||
|
||||
/*--------------------------------------------------------------------*/
|
||||
void flash_print_info (flash_info_t * info)
|
||||
{
|
||||
int i, k;
|
||||
unsigned long size;
|
||||
int erased;
|
||||
volatile unsigned char *flash;
|
||||
|
||||
printf (" Size: %ld KB in %d Sectors\n",
|
||||
info->size >> 10, info->sector_count);
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
|
||||
/* Check if whole sector is erased */
|
||||
if (i != (info->sector_count - 1))
|
||||
size = info->start[i + 1] - info->start[i];
|
||||
else
|
||||
size = info->start[0] + info->size - info->start[i];
|
||||
erased = 1;
|
||||
flash = (volatile unsigned char *) info->start[i];
|
||||
for (k = 0; k < size; k++) {
|
||||
if (*flash++ != 0xff) {
|
||||
erased = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Print the info */
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s%s", info->start[i], erased ? " E" : " ",
|
||||
info->protect[i] ? "RO " : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------------*/
|
||||
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
|
||||
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
|
||||
int prot, sect;
|
||||
unsigned oldpri;
|
||||
ulong start;
|
||||
|
||||
/* Some sanity checking */
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
printf ("- no sectors to erase\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
printf("- Erase: Sect: %i @ 0x%08x\n", sect, info->start[sect]);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* NOTE: disabling interrupts on Nios can be very bad since it
|
||||
* also disables the LO_LIMIT exception. It's better here to
|
||||
* set the interrupt priority to 3 & restore it when we're done.
|
||||
*/
|
||||
oldpri = ipri (3);
|
||||
|
||||
/* It's ok to erase multiple sectors provided we don't delay more
|
||||
* than 50 usec between cmds ... at which point the erase time-out
|
||||
* occurs. So don't go and put printf() calls in the loop ... it
|
||||
* won't be very helpful ;-)
|
||||
*/
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
|
||||
*addr = 0xaa;
|
||||
*addr = 0x55;
|
||||
*addr = 0x80;
|
||||
*addr = 0xaa;
|
||||
*addr = 0x55;
|
||||
*addr2 = 0x30;
|
||||
/* Now just wait for 0xff & provide some user
|
||||
* feedback while we wait. Here we have to grant
|
||||
* timer interrupts. Otherwise get_timer() can't
|
||||
* work right. */
|
||||
ipri(oldpri);
|
||||
start = get_timer (0);
|
||||
while (*addr2 != 0xff) {
|
||||
udelay (1000 * 1000);
|
||||
putc ('.');
|
||||
if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("timeout\n");
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
oldpri = ipri (3); /* disallow non important irqs again */
|
||||
}
|
||||
}
|
||||
|
||||
printf ("\n");
|
||||
|
||||
/* Restore interrupt priority */
|
||||
ipri (oldpri);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
|
||||
vu_char *cmd = (vu_char *) info->start[0];
|
||||
vu_char *dst = (vu_char *) addr;
|
||||
unsigned char b;
|
||||
unsigned oldpri;
|
||||
ulong start;
|
||||
|
||||
while (cnt) {
|
||||
/* Check for sufficient erase */
|
||||
b = *src;
|
||||
if ((*dst & b) != b) {
|
||||
printf ("%02x : %02x\n", *dst, b);
|
||||
return (2);
|
||||
}
|
||||
|
||||
/* Disable interrupts other than window underflow
|
||||
* (interrupt priority 2)
|
||||
*/
|
||||
oldpri = ipri (3);
|
||||
*cmd = 0xaa;
|
||||
*cmd = 0x55;
|
||||
*cmd = 0xa0;
|
||||
*dst = b;
|
||||
|
||||
/* Verify write */
|
||||
start = get_timer (0);
|
||||
while (*dst != b) {
|
||||
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
ipri (oldpri);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
dst++;
|
||||
src++;
|
||||
cnt--;
|
||||
ipri (oldpri);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
|
@ -4,4 +4,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += $(BOARD).o
|
||||
obj-y += bcm28155_ap.o
|
||||
|
|
|
@ -6,5 +6,5 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += $(BOARD).o
|
||||
obj-y += cm_t335.o
|
||||
obj-$(CONFIG_SPL_BUILD) += mux.o spl.o
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -1,240 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2003
|
||||
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <command.h>
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
#define DBG(x...) printf(x)
|
||||
#else
|
||||
#define DBG(x...)
|
||||
#endif /* DEBUG */
|
||||
|
||||
#define MAX_ONES 226
|
||||
|
||||
#ifdef CONFIG_SYS_FPGA_PRG
|
||||
# define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output)*/
|
||||
# define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */
|
||||
# define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */
|
||||
# define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */
|
||||
# define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */
|
||||
#else
|
||||
# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
|
||||
# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
|
||||
# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
|
||||
# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
|
||||
# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
|
||||
#endif
|
||||
|
||||
#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
|
||||
#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
|
||||
#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
|
||||
|
||||
#define SET_FPGA(data) out32(GPIO0_OR, data)
|
||||
|
||||
#define FPGA_WRITE_1 { \
|
||||
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
|
||||
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
|
||||
|
||||
#define FPGA_WRITE_0 { \
|
||||
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
|
||||
SET_FPGA(FPGA_PRG); /* set data to 0 */ \
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
|
||||
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
|
||||
|
||||
#if 0
|
||||
static int fpga_boot (unsigned char *fpgadata, int size)
|
||||
{
|
||||
int i, index, len;
|
||||
int count;
|
||||
|
||||
#ifdef CONFIG_SYS_FPGA_SPARTAN2
|
||||
int j;
|
||||
#else
|
||||
unsigned char b;
|
||||
int bit;
|
||||
#endif
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpgadata[index];
|
||||
DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_FPGA_SPARTAN2
|
||||
/* search for preamble 0xFFFFFFFF */
|
||||
while (1) {
|
||||
if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
|
||||
&& (fpgadata[index + 2] == 0xff)
|
||||
&& (fpgadata[index + 3] == 0xff))
|
||||
break; /* preamble found */
|
||||
else
|
||||
index++;
|
||||
}
|
||||
#else
|
||||
/* search for preamble 0xFF2X */
|
||||
for (index = 0; index < size - 1; index++) {
|
||||
if ((fpgadata[index] == 0xff)
|
||||
&& ((fpgadata[index + 1] & 0xf0) == 0x30))
|
||||
break;
|
||||
}
|
||||
index += 2;
|
||||
#endif
|
||||
|
||||
DBG ("FPGA: configdata starts at position 0x%x\n", index);
|
||||
DBG ("FPGA: length of fpga-data %d\n", size - index);
|
||||
|
||||
/*
|
||||
* Setup port pins for fpga programming
|
||||
*/
|
||||
out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */
|
||||
out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
|
||||
out32 (GPIO0_OR, in32 (GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */
|
||||
|
||||
DBG ("%s, ",
|
||||
((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
|
||||
DBG ("%s\n",
|
||||
((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
|
||||
|
||||
/*
|
||||
* Init fpga by asserting and deasserting PROGRAM*
|
||||
*/
|
||||
SET_FPGA (FPGA_CLK | FPGA_DATA);
|
||||
|
||||
/* Wait for FPGA init line low */
|
||||
count = 0;
|
||||
while (in32 (GPIO0_IR) & FPGA_INIT) {
|
||||
udelay (1000); /* wait 1ms */
|
||||
/* Check for timeout - 100us max, so use 3ms */
|
||||
if (count++ > 3) {
|
||||
DBG ("FPGA: Booting failed!\n");
|
||||
return ERROR_FPGA_PRG_INIT_LOW;
|
||||
}
|
||||
}
|
||||
|
||||
DBG ("%s, ",
|
||||
((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
|
||||
DBG ("%s\n",
|
||||
((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
|
||||
|
||||
/* deassert PROGRAM* */
|
||||
SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA);
|
||||
|
||||
/* Wait for FPGA end of init period . */
|
||||
count = 0;
|
||||
while (!(in32 (GPIO0_IR) & FPGA_INIT)) {
|
||||
udelay (1000); /* wait 1ms */
|
||||
/* Check for timeout */
|
||||
if (count++ > 3) {
|
||||
DBG ("FPGA: Booting failed!\n");
|
||||
return ERROR_FPGA_PRG_INIT_HIGH;
|
||||
}
|
||||
}
|
||||
|
||||
DBG ("%s, ",
|
||||
((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
|
||||
DBG ("%s\n",
|
||||
((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
|
||||
|
||||
DBG ("write configuration data into fpga\n");
|
||||
/* write configuration-data into fpga... */
|
||||
|
||||
#ifdef CONFIG_SYS_FPGA_SPARTAN2
|
||||
/*
|
||||
* Load uncompressed image into fpga
|
||||
*/
|
||||
for (i = index; i < size; i++) {
|
||||
for (j = 0; j < 8; j++) {
|
||||
if ((fpgadata[i] & 0x80) == 0x80) {
|
||||
FPGA_WRITE_1;
|
||||
} else {
|
||||
FPGA_WRITE_0;
|
||||
}
|
||||
fpgadata[i] <<= 1;
|
||||
}
|
||||
}
|
||||
#else /* ! CONFIG_SYS_FPGA_SPARTAN2 */
|
||||
/* send 0xff 0x20 */
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_0;
|
||||
FPGA_WRITE_0;
|
||||
FPGA_WRITE_1;
|
||||
FPGA_WRITE_0;
|
||||
FPGA_WRITE_0;
|
||||
FPGA_WRITE_0;
|
||||
FPGA_WRITE_0;
|
||||
FPGA_WRITE_0;
|
||||
|
||||
/*
|
||||
** Bit_DeCompression
|
||||
** Code 1 .. maxOnes : n '1's followed by '0'
|
||||
** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
|
||||
** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
|
||||
** 255 : '1'
|
||||
*/
|
||||
|
||||
for (i = index; i < size; i++) {
|
||||
b = fpgadata[i];
|
||||
if ((b >= 1) && (b <= MAX_ONES)) {
|
||||
for (bit = 0; bit < b; bit++) {
|
||||
FPGA_WRITE_1;
|
||||
}
|
||||
FPGA_WRITE_0;
|
||||
} else if (b == (MAX_ONES + 1)) {
|
||||
for (bit = 1; bit < b; bit++) {
|
||||
FPGA_WRITE_1;
|
||||
}
|
||||
} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
|
||||
for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
|
||||
FPGA_WRITE_0;
|
||||
}
|
||||
FPGA_WRITE_1;
|
||||
} else if (b == 255) {
|
||||
FPGA_WRITE_1;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_SYS_FPGA_SPARTAN2 */
|
||||
|
||||
DBG ("%s, ",
|
||||
((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
|
||||
DBG ("%s\n",
|
||||
((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
|
||||
|
||||
/*
|
||||
* Check if fpga's DONE signal - correctly booted ?
|
||||
*/
|
||||
|
||||
/* Wait for FPGA end of programming period . */
|
||||
count = 0;
|
||||
while (!(in32 (GPIO0_IR) & FPGA_DONE)) {
|
||||
udelay (1000); /* wait 1ms */
|
||||
/* Check for timeout */
|
||||
if (count++ > 3) {
|
||||
DBG ("FPGA: Booting failed!\n");
|
||||
return ERROR_FPGA_PRG_DONE;
|
||||
}
|
||||
}
|
||||
|
||||
DBG ("FPGA: Booting successful!\n");
|
||||
return 0;
|
||||
}
|
||||
#endif /* 0 */
|
|
@ -1,186 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
#include <pci.h>
|
||||
|
||||
|
||||
u_long pci9054_iobase;
|
||||
|
||||
|
||||
#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */
|
||||
#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Subroutine: pci9054_read_config_dword
|
||||
| Description: Read a PCI configuration register
|
||||
| Inputs:
|
||||
| hose PCI Controller
|
||||
| dev PCI Bus+Device+Function number
|
||||
| offset Configuration register number
|
||||
| value Address of the configuration register value
|
||||
| Return value:
|
||||
| 0 Successful
|
||||
+-----------------------------------------------------------------------------*/
|
||||
int pci9054_read_config_dword(struct pci_controller *hose,
|
||||
pci_dev_t dev, int offset, u32* value)
|
||||
{
|
||||
unsigned long conAdrVal;
|
||||
unsigned long val;
|
||||
|
||||
/* generate coded value for CON_ADR register */
|
||||
conAdrVal = dev | (offset & 0xfc) | 0x80000000;
|
||||
|
||||
/* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */
|
||||
*(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
|
||||
|
||||
/* Note: *pResult comes back as -1 if machine check happened */
|
||||
val = in32r(PCI_PRIMARY_CDR);
|
||||
|
||||
*value = (unsigned long) val;
|
||||
|
||||
out32r(PCI_PRIMARY_CAR, 0);
|
||||
|
||||
if ((*(unsigned long *)0x50000304) & 0x60000000)
|
||||
{
|
||||
/* clear pci master/target abort bits */
|
||||
*(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Subroutine: pci9054_write_config_dword
|
||||
| Description: Write a PCI configuration register.
|
||||
| Inputs:
|
||||
| hose PCI Controller
|
||||
| dev PCI Bus+Device+Function number
|
||||
| offset Configuration register number
|
||||
| Value Configuration register value
|
||||
| Return value:
|
||||
| 0 Successful
|
||||
| Updated for pass2 errata #6. Need to disable interrupts and clear the
|
||||
| PCICFGADR reg after writing the PCICFGDATA reg.
|
||||
+-----------------------------------------------------------------------------*/
|
||||
int pci9054_write_config_dword(struct pci_controller *hose,
|
||||
pci_dev_t dev, int offset, u32 value)
|
||||
{
|
||||
unsigned long conAdrVal;
|
||||
|
||||
conAdrVal = dev | (offset & 0xfc) | 0x80000000;
|
||||
|
||||
*(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
|
||||
|
||||
out32r(PCI_PRIMARY_CDR, value);
|
||||
|
||||
out32r(PCI_PRIMARY_CAR, 0);
|
||||
|
||||
/* clear pci master/target abort bits */
|
||||
*(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_DASA_SIM
|
||||
static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev,
|
||||
struct pci_config_table *_)
|
||||
{
|
||||
unsigned int iobase;
|
||||
unsigned short status = 0;
|
||||
unsigned char timer;
|
||||
|
||||
/*
|
||||
* Configure PLX PCI9054
|
||||
*/
|
||||
pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status);
|
||||
status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
|
||||
pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status);
|
||||
|
||||
/* Check the latency timer for values >= 0x60.
|
||||
*/
|
||||
pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
|
||||
if (timer < 0x60)
|
||||
{
|
||||
pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
|
||||
}
|
||||
|
||||
/* Set I/O base register.
|
||||
*/
|
||||
pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE);
|
||||
pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
|
||||
|
||||
pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
|
||||
|
||||
if (pci9054_iobase == 0xffffffff)
|
||||
{
|
||||
printf("Error: Can not set I/O base register.\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct pci_config_table pci9054_config_table[] = {
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN),
|
||||
pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE,
|
||||
CONFIG_SYS_ETH_IOBASE,
|
||||
PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
|
||||
#ifdef CONFIG_DASA_SIM
|
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN),
|
||||
pci_dasa_sim_config_pci9054 },
|
||||
#endif
|
||||
#endif
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct pci_controller pci9054_hose = {
|
||||
config_table: pci9054_config_table,
|
||||
};
|
||||
|
||||
void pci_init(void)
|
||||
{
|
||||
struct pci_controller *hose = &pci9054_hose;
|
||||
|
||||
/*
|
||||
* Register the hose
|
||||
*/
|
||||
hose->first_busno = 0;
|
||||
hose->last_busno = 0xff;
|
||||
|
||||
/* System memory space */
|
||||
pci_set_region(hose->regions + 0,
|
||||
0x00000000, 0x00000000, 0x01000000,
|
||||
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
||||
|
||||
/* PCI Memory space */
|
||||
pci_set_region(hose->regions + 1,
|
||||
0x00000000, 0xc0000000, 0x10000000,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
pci_set_ops(hose,
|
||||
pci_hose_read_config_byte_via_dword,
|
||||
pci_hose_read_config_word_via_dword,
|
||||
pci9054_read_config_dword,
|
||||
pci_hose_write_config_byte_via_dword,
|
||||
pci_hose_write_config_word_via_dword,
|
||||
pci9054_write_config_dword);
|
||||
|
||||
hose->region_count = 2;
|
||||
|
||||
pci_register_hose(hose);
|
||||
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
}
|
|
@ -1,8 +0,0 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y = adciop.o flash.o ../common/misc.o ../common/pci.o
|
|
@ -1,87 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
#include "adciop.h"
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#define _NOT_USED_ 0xFFFFFFFF
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
/*
|
||||
* Set port pin in escc2 to keep living, and configure user led output
|
||||
*/
|
||||
*(unsigned char *) 0x2000033e = 0x77; /* ESCC2: PCR bit3=pwr on, bit7=led out */
|
||||
*(unsigned char *) 0x2000033c = 0x88; /* ESCC2: PVR pwr on, led off */
|
||||
|
||||
/*
|
||||
* Init pci regs
|
||||
*/
|
||||
*(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */
|
||||
*(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */
|
||||
*(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */
|
||||
*(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */
|
||||
*(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */
|
||||
*(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */
|
||||
*(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
char str[64];
|
||||
int i = getenv_f("serial#", str, sizeof (str));
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
if (!i || strncmp (str, "ADCIOP", 6)) {
|
||||
puts ("### No HW ID - assuming ADCIOP\n");
|
||||
return (1);
|
||||
}
|
||||
|
||||
puts (str);
|
||||
|
||||
putc ('\n');
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
phys_size_t initdram (int board_type)
|
||||
{
|
||||
return (16 * 1024 * 1024);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
int testdram (void)
|
||||
{
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf ("test: 16 MB - ok\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return pci_eth_init(bis);
|
||||
}
|
|
@ -1,28 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* FLASH Memory Map as used by TQ Monitor:
|
||||
*
|
||||
* Start Address Length
|
||||
* +-----------------------+ 0x4000_0000 Start of Flash -----------------
|
||||
* | MON8xx code | 0x4000_0100 Reset Vector
|
||||
* +-----------------------+ 0x400?_????
|
||||
* | (unused) |
|
||||
* +-----------------------+ 0x4001_FF00
|
||||
* | Ethernet Addresses | 0x78
|
||||
* +-----------------------+ 0x4001_FF78
|
||||
* | (Reserved for MON8xx) | 0x44
|
||||
* +-----------------------+ 0x4001_FFBC
|
||||
* | Lock Address | 0x04
|
||||
* +-----------------------+ 0x4001_FFC0 ^
|
||||
* | Hardware Information | 0x40 | MON8xx
|
||||
* +=======================+ 0x4002_0000 (sector border) -----------------
|
||||
* | Autostart Header | | Applications
|
||||
* | ... | v
|
||||
*
|
||||
*****************************************************************************/
|
|
@ -1,97 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/*
|
||||
* include common flash code (for esd boards)
|
||||
*/
|
||||
#include "../common/flash.c"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0, size_b1;
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0<<20);
|
||||
}
|
||||
|
||||
size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
|
||||
|
||||
if (size_b1 > size_b0) {
|
||||
printf ("## ERROR: "
|
||||
"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
|
||||
size_b1, size_b1<<20,
|
||||
size_b0, size_b0<<20
|
||||
);
|
||||
flash_info[0].flash_id = FLASH_UNKNOWN;
|
||||
flash_info[1].flash_id = FLASH_UNKNOWN;
|
||||
flash_info[0].sector_count = -1;
|
||||
flash_info[1].sector_count = -1;
|
||||
flash_info[0].size = 0;
|
||||
flash_info[1].size = 0;
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
/* monitor protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
FLASH_BASE0_PRELIM+size_b0-monitor_flash_len,
|
||||
FLASH_BASE0_PRELIM+size_b0-1,
|
||||
&flash_info[0]);
|
||||
|
||||
if (size_b1) {
|
||||
/* Re-do sizing to get full correct info */
|
||||
size_b1 = flash_get_size((vu_long *)(FLASH_BASE0_PRELIM + size_b0),
|
||||
&flash_info[1]);
|
||||
|
||||
flash_get_offsets (FLASH_BASE0_PRELIM + size_b0, &flash_info[1]);
|
||||
|
||||
/* monitor protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
FLASH_BASE0_PRELIM+size_b0+size_b1-monitor_flash_len,
|
||||
FLASH_BASE0_PRELIM+size_b0+size_b1-1,
|
||||
&flash_info[1]);
|
||||
/* monitor protection OFF by default (one is enough) */
|
||||
flash_protect(FLAG_PROTECT_CLEAR,
|
||||
FLASH_BASE0_PRELIM+size_b0-monitor_flash_len,
|
||||
FLASH_BASE0_PRELIM+size_b0-1,
|
||||
&flash_info[0]);
|
||||
} else {
|
||||
flash_info[1].flash_id = FLASH_UNKNOWN;
|
||||
flash_info[1].sector_count = -1;
|
||||
}
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
flash_info[1].size = size_b1;
|
||||
|
||||
return (size_b0 + size_b1);
|
||||
}
|
|
@ -1,8 +0,0 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y = dasa_sim.o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o
|
|
@ -1,209 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <pci.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define OK 0
|
||||
#define ERROR (-1)
|
||||
|
||||
extern u_long pci9054_iobase;
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
*
|
||||
* Routines for PLX PCI9054 eeprom access
|
||||
*
|
||||
*/
|
||||
|
||||
static unsigned int PciEepromReadLongVPD (int offs)
|
||||
{
|
||||
unsigned int value;
|
||||
unsigned int ret;
|
||||
int count;
|
||||
|
||||
pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
|
||||
(offs << 16) | 0x0003);
|
||||
count = 0;
|
||||
|
||||
for (;;) {
|
||||
udelay (10 * 1000);
|
||||
pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
|
||||
if ((ret & 0x80000000) != 0) {
|
||||
break;
|
||||
} else {
|
||||
count++;
|
||||
if (count > 10) {
|
||||
printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, &value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
static int PciEepromWriteLongVPD (int offs, unsigned int value)
|
||||
{
|
||||
unsigned int ret;
|
||||
int count;
|
||||
|
||||
pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, value);
|
||||
pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
|
||||
(offs << 16) | 0x80000003);
|
||||
count = 0;
|
||||
|
||||
for (;;) {
|
||||
udelay (10 * 1000);
|
||||
pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
|
||||
if ((ret & 0x80000000) == 0) {
|
||||
break;
|
||||
} else {
|
||||
count++;
|
||||
if (count > 10) {
|
||||
printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
static void showPci9054 (void)
|
||||
{
|
||||
int val;
|
||||
int l, i;
|
||||
|
||||
/* read 9054-values */
|
||||
for (l = 0; l < 6; l++) {
|
||||
printf ("%02x: ", l * 0x10);
|
||||
for (i = 0; i < 4; i++) {
|
||||
pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN,
|
||||
l * 16 + i * 4,
|
||||
(unsigned int *)&val);
|
||||
printf ("%08x ", val);
|
||||
}
|
||||
printf ("\n");
|
||||
}
|
||||
printf ("\n");
|
||||
|
||||
for (l = 0; l < 7; l++) {
|
||||
printf ("%02x: ", l * 0x10);
|
||||
for (i = 0; i < 4; i++)
|
||||
printf ("%08x ",
|
||||
PciEepromReadLongVPD ((i + l * 4) * 4));
|
||||
printf ("\n");
|
||||
}
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
|
||||
static void updatePci9054 (void)
|
||||
{
|
||||
/*
|
||||
* Set EEPROM write-protect register to 0
|
||||
*/
|
||||
out_be32 ((void *)(pci9054_iobase + 0x0c),
|
||||
in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
|
||||
|
||||
/* Long Serial EEPROM Load Registers... */
|
||||
PciEepromWriteLongVPD (0x00, 0x905410b5);
|
||||
PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */
|
||||
PciEepromWriteLongVPD (0x08, 0x28140100);
|
||||
|
||||
PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */
|
||||
PciEepromWriteLongVPD (0x10, 0x00000000);
|
||||
|
||||
/* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */
|
||||
PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */
|
||||
PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */
|
||||
|
||||
PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */
|
||||
PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */
|
||||
|
||||
PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */
|
||||
PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */
|
||||
|
||||
PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */
|
||||
|
||||
PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */
|
||||
PciEepromWriteLongVPD (0x34, 0x00000000);
|
||||
PciEepromWriteLongVPD (0x38, 0x00000000);
|
||||
|
||||
PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */
|
||||
PciEepromWriteLongVPD (0x40, 0x00000000);
|
||||
|
||||
/* Extra Long Serial EEPROM Load Registers... */
|
||||
PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */
|
||||
|
||||
/* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */
|
||||
/* Offset to LAS1: Group 1: 0x00040000 */
|
||||
/* Group 2: 0x00080000 */
|
||||
/* Group 3: 0x000c0000 */
|
||||
PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */
|
||||
PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */
|
||||
PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */
|
||||
|
||||
PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */
|
||||
|
||||
printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n");
|
||||
}
|
||||
|
||||
|
||||
static void clearPci9054 (void)
|
||||
{
|
||||
/*
|
||||
* Set EEPROM write-protect register to 0
|
||||
*/
|
||||
out_be32 ((void *)(pci9054_iobase + 0x0c),
|
||||
in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff);
|
||||
|
||||
/* Long Serial EEPROM Load Registers... */
|
||||
PciEepromWriteLongVPD (0x00, 0xffffffff);
|
||||
PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */
|
||||
|
||||
printf ("Finished clearing PLX PCI9054 EEPROM!\n");
|
||||
}
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc,
|
||||
char * const argv[])
|
||||
{
|
||||
if (strcmp (argv[1], "info") == 0) {
|
||||
showPci9054 ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (strcmp (argv[1], "update") == 0) {
|
||||
updatePci9054 ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (strcmp (argv[1], "clear") == 0) {
|
||||
clearPci9054 ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
return cmd_usage(cmdtp);
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
pci9054, 3, 1, do_pci9054,
|
||||
"PLX PCI9054 EEPROM access",
|
||||
"pci9054 info - print EEPROM values\n"
|
||||
"pci9054 update - updates EEPROM with default values"
|
||||
);
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
|
@ -1,198 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
#include "dasa_sim.h"
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#undef FPGA_DEBUG
|
||||
|
||||
#define _NOT_USED_ 0xFFFFFFFF
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* fpga configuration data - generated by bit2inc */
|
||||
static unsigned char fpgadata[] = {
|
||||
#include "fpgadata.c"
|
||||
};
|
||||
|
||||
#define FPGA_PRG_SLEEP 32 /* fpga program sleep-time */
|
||||
#define LOAD_LONG(a) a
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* sysFpgaBoot - Load fpga-image into fpga
|
||||
*
|
||||
*/
|
||||
static int fpgaBoot (void)
|
||||
{
|
||||
int i, j, index, len;
|
||||
unsigned char b;
|
||||
int imageSize;
|
||||
|
||||
imageSize = sizeof (fpgadata);
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpgadata[index];
|
||||
index += len + 3;
|
||||
}
|
||||
|
||||
/* search for preamble 0xFF2X */
|
||||
for (index = 0; index < imageSize - 1; index++) {
|
||||
if ((fpgadata[index] == 0xff)
|
||||
&& ((fpgadata[index + 1] & 0xf0) == 0x20))
|
||||
break;
|
||||
}
|
||||
|
||||
/* enable cs1 instead of user0... */
|
||||
*(unsigned long *) 0x50000084 &= ~0x00000002;
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
printf ("%s\n",
|
||||
((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
|
||||
"NOT DONE" : "DONE");
|
||||
#endif
|
||||
|
||||
/* init fpga by asserting and deasserting PROGRAM* (USER2)... */
|
||||
*(unsigned long *) 0x50000084 &= ~0x00000400;
|
||||
udelay (FPGA_PRG_SLEEP * 1000);
|
||||
|
||||
*(unsigned long *) 0x50000084 |= 0x00000400;
|
||||
udelay (FPGA_PRG_SLEEP * 1000);
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
printf ("%s\n",
|
||||
((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
|
||||
"NOT DONE" : "DONE");
|
||||
#endif
|
||||
|
||||
/* cs1: disable burst, disable ready */
|
||||
*(unsigned long *) 0x50000114 &= ~0x00000300;
|
||||
|
||||
/* cs1: set write timing */
|
||||
*(unsigned long *) 0x50000118 |= 0x00010900;
|
||||
|
||||
/* write configuration-data into fpga... */
|
||||
for (i = index; i < imageSize; i++) {
|
||||
b = fpgadata[i];
|
||||
for (j = 0; j < 8; j++) {
|
||||
*(unsigned long *) 0x30000000 =
|
||||
((b & 0x80) == 0x80)
|
||||
? LOAD_LONG (0x03030101)
|
||||
: LOAD_LONG (0x02020000);
|
||||
b <<= 1;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
printf ("%s\n",
|
||||
((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
|
||||
"NOT DONE" : "DONE");
|
||||
#endif
|
||||
|
||||
/* set cs1 to 32 bit data-width, disable burst, enable ready */
|
||||
*(unsigned long *) 0x50000114 |= 0x00000202;
|
||||
*(unsigned long *) 0x50000114 &= ~0x00000100;
|
||||
|
||||
/* cs1: set iop access to little endian */
|
||||
*(unsigned long *) 0x50000114 &= ~0x00000010;
|
||||
|
||||
/* cs1: set read and write timing */
|
||||
*(unsigned long *) 0x50000118 = 0x00010000;
|
||||
*(unsigned long *) 0x5000011c = 0x00010001;
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
printf ("%s\n",
|
||||
((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
|
||||
"NOT DONE" : "DONE");
|
||||
#endif
|
||||
|
||||
/* wait for 30 ms... */
|
||||
udelay (30 * 1000);
|
||||
/* check if fpga's DONE signal - correctly booted ? */
|
||||
if ((*(unsigned long *) 0x50000084 & 0x00010000) == 0)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
/*
|
||||
* Init pci regs
|
||||
*/
|
||||
*(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */
|
||||
*(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */
|
||||
*(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */
|
||||
*(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */
|
||||
*(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */
|
||||
*(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */
|
||||
*(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
int index;
|
||||
int len;
|
||||
char str[64];
|
||||
int i = getenv_f("serial#", str, sizeof (str));
|
||||
int fpga;
|
||||
unsigned short val;
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
/*
|
||||
* Boot onboard FPGA
|
||||
*/
|
||||
fpga = fpgaBoot ();
|
||||
|
||||
if (!i || strncmp (str, "DASA_SIM", 8)) {
|
||||
puts ("### No HW ID - assuming DASA_SIM");
|
||||
}
|
||||
|
||||
puts (str);
|
||||
|
||||
if (fpga == 0) {
|
||||
val = *(unsigned short *) 0x30000202;
|
||||
printf (" (Id=%d Version=%d Revision=%d)",
|
||||
(val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1);
|
||||
|
||||
puts ("\nFPGA: ");
|
||||
|
||||
/* display infos on fpgaimage */
|
||||
index = 15;
|
||||
for (i = 0; i < 4; i++) {
|
||||
len = fpgadata[index];
|
||||
printf ("%s ", &(fpgadata[index + 1]));
|
||||
index += len + 3;
|
||||
}
|
||||
} else {
|
||||
puts ("\nFPGA: Booting failed!");
|
||||
}
|
||||
|
||||
putc ('\n');
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
phys_size_t initdram (int board_type)
|
||||
{
|
||||
return (16 * 1024 * 1024);
|
||||
}
|
|
@ -1,28 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* FLASH Memory Map as used by TQ Monitor:
|
||||
*
|
||||
* Start Address Length
|
||||
* +-----------------------+ 0x4000_0000 Start of Flash -----------------
|
||||
* | MON8xx code | 0x4000_0100 Reset Vector
|
||||
* +-----------------------+ 0x400?_????
|
||||
* | (unused) |
|
||||
* +-----------------------+ 0x4001_FF00
|
||||
* | Ethernet Addresses | 0x78
|
||||
* +-----------------------+ 0x4001_FF78
|
||||
* | (Reserved for MON8xx) | 0x44
|
||||
* +-----------------------+ 0x4001_FFBC
|
||||
* | Lock Address | 0x04
|
||||
* +-----------------------+ 0x4001_FFC0 ^
|
||||
* | Hardware Information | 0x40 | MON8xx
|
||||
* +=======================+ 0x4002_0000 (sector border) -----------------
|
||||
* | Autostart Header | | Applications
|
||||
* | ... | v
|
||||
*
|
||||
*****************************************************************************/
|
|
@ -1,164 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define EEPROM_CAP 0x50000358
|
||||
#define EEPROM_DATA 0x5000035c
|
||||
|
||||
|
||||
unsigned int eepromReadLong(int offs)
|
||||
{
|
||||
unsigned int value;
|
||||
unsigned short ret;
|
||||
int count;
|
||||
|
||||
out_be16((void *)EEPROM_CAP, offs);
|
||||
|
||||
count = 0;
|
||||
|
||||
for (;;)
|
||||
{
|
||||
count++;
|
||||
ret = in_be16((void *)EEPROM_CAP);
|
||||
|
||||
if ((ret & 0x8000) != 0)
|
||||
break;
|
||||
}
|
||||
|
||||
value = in_be32((void *)EEPROM_DATA);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
unsigned char eepromReadByte(int offs)
|
||||
{
|
||||
unsigned int valueLong;
|
||||
unsigned char *ptr;
|
||||
|
||||
valueLong = eepromReadLong(offs & ~3);
|
||||
ptr = (unsigned char *)&valueLong;
|
||||
|
||||
return ptr[offs & 3];
|
||||
}
|
||||
|
||||
|
||||
void eepromWriteLong(int offs, unsigned int value)
|
||||
{
|
||||
unsigned short ret;
|
||||
int count;
|
||||
|
||||
count = 0;
|
||||
|
||||
out_be32((void *)EEPROM_DATA, value);
|
||||
out_be16((void *)EEPROM_CAP, 0x8000 + offs);
|
||||
|
||||
for (;;)
|
||||
{
|
||||
count++;
|
||||
ret = in_be16((void *)EEPROM_CAP);
|
||||
|
||||
if ((ret & 0x8000) == 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void eepromWriteByte(int offs, unsigned char valueByte)
|
||||
{
|
||||
unsigned int valueLong;
|
||||
unsigned char *ptr;
|
||||
|
||||
valueLong = eepromReadLong(offs & ~3);
|
||||
ptr = (unsigned char *)&valueLong;
|
||||
|
||||
ptr[offs & 3] = valueByte;
|
||||
|
||||
eepromWriteLong(offs & ~3, valueLong);
|
||||
}
|
||||
|
||||
|
||||
void i2c_read (uchar *addr, int alen, uchar *buffer, int len)
|
||||
{
|
||||
int i;
|
||||
int len2, ptr;
|
||||
|
||||
/* printf("\naddr=%x alen=%x buffer=%x len=%x", addr[0], addr[1], *(short *)addr, alen, buffer, len); /###* test-only */
|
||||
|
||||
ptr = *(short *)addr;
|
||||
|
||||
/*
|
||||
* Read till lword boundary
|
||||
*/
|
||||
len2 = 4 - (*(short *)addr & 0x0003);
|
||||
for (i=0; i<len2; i++)
|
||||
{
|
||||
*buffer++ = eepromReadByte(ptr++);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read all lwords
|
||||
*/
|
||||
len2 = (len - len2) >> 2;
|
||||
for (i=0; i<len2; i++)
|
||||
{
|
||||
*(unsigned int *)buffer = eepromReadLong(ptr);
|
||||
buffer += 4;
|
||||
ptr += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read last bytes
|
||||
*/
|
||||
len2 = (*(short *)addr + len) & 0x0003;
|
||||
for (i=0; i<len2; i++)
|
||||
{
|
||||
*buffer++ = eepromReadByte(ptr++);
|
||||
}
|
||||
}
|
||||
|
||||
void i2c_write (uchar *addr, int alen, uchar *buffer, int len)
|
||||
{
|
||||
int i;
|
||||
int len2, ptr;
|
||||
|
||||
/* printf("\naddr=%x alen=%x buffer=%x len=%x", addr[0], addr[1], *(short *)addr, alen, buffer, len); /###* test-only */
|
||||
|
||||
ptr = *(short *)addr;
|
||||
|
||||
/*
|
||||
* Write till lword boundary
|
||||
*/
|
||||
len2 = 4 - (*(short *)addr & 0x0003);
|
||||
for (i=0; i<len2; i++)
|
||||
{
|
||||
eepromWriteByte(ptr++, *buffer++);
|
||||
}
|
||||
|
||||
/*
|
||||
* Write all lwords
|
||||
*/
|
||||
len2 = (len - len2) >> 2;
|
||||
for (i=0; i<len2; i++)
|
||||
{
|
||||
eepromWriteLong(ptr, *(unsigned int *)buffer);
|
||||
buffer += 4;
|
||||
ptr += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* Write last bytes
|
||||
*/
|
||||
len2 = (*(short *)addr + len) & 0x0003;
|
||||
for (i=0; i<len2; i++)
|
||||
{
|
||||
eepromWriteByte(ptr++, *buffer++);
|
||||
}
|
||||
}
|
|
@ -1,58 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/*
|
||||
* include common flash code (for esd boards)
|
||||
*/
|
||||
#include "../common/flash.c"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info);
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0;
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0<<20);
|
||||
}
|
||||
|
||||
/* Setup offsets */
|
||||
flash_get_offsets (-size_b0, &flash_info[0]);
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-monitor_flash_len,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
|
||||
return (size_b0);
|
||||
}
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Reference in a new issue