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ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 2

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This is kind of microseries-within-series indent cleanup.
This patch just tweaks the indentation so it is visible
what is supposed to go where.

It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.

No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut 2015-07-17 03:22:31 +02:00
parent bce24efa1d
commit d2ea49508a
1 changed files with 27 additions and 29 deletions
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56
drivers/ddr/altera/sequencer.c
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@ -2243,8 +2243,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
write_group, d); write_group, d);
} }
for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0; for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0; p++) {
p++) {
/* set a particular dqdqs phase */ /* set a particular dqdqs phase */
scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p); scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
@ -2257,10 +2256,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
* using current DQDQS phase. * using current DQDQS phase.
*/ */
rw_mgr_mem_calibrate_read_load_patterns(0, 1); rw_mgr_mem_calibrate_read_load_patterns(0, 1);
if (!(gbl->phy_debug_mode_flags & if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
(read_group, 1, &bit_chk)) { (read_group, 1, &bit_chk)) {
debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed:", debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed:",
__func__, __LINE__); __func__, __LINE__);
debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n", debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n",
@ -2269,37 +2267,37 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
} }
} }
/* case:56390 */ /* case:56390 */
grp_calibrated = 1; grp_calibrated = 1;
if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
(write_group, read_group, test_bgn)) { (write_group, read_group, test_bgn)) {
/*
* USER Read per-bit deskew can be done on a
* per shadow register basis.
*/
for (rank_bgn = 0, sr = 0;
rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
rank_bgn += NUM_RANKS_PER_SHADOW_REG,
++sr) {
/* /*
* Determine if this set of ranks * USER Read per-bit deskew can be done on a
* should be skipped entirely. * per shadow register basis.
*/ */
if (!param->skip_shadow_regs[sr]) { for (rank_bgn = 0, sr = 0;
rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
rank_bgn += NUM_RANKS_PER_SHADOW_REG,
++sr) {
/* /*
* If doing read after write * Determine if this set of ranks
* calibration, do not update * should be skipped entirely.
* FOM, now - do it then.
*/ */
if (!rw_mgr_mem_calibrate_vfifo_center if (!param->skip_shadow_regs[sr]) {
(rank_bgn, write_group, /*
read_group, test_bgn, 1, 0)) { * If doing read after write
grp_calibrated = 0; * calibration, do not update
failed_substage = * FOM, now - do it then.
CAL_SUBSTAGE_VFIFO_CENTER; */
if (!rw_mgr_mem_calibrate_vfifo_center
(rank_bgn, write_group,
read_group, test_bgn,
1, 0)) {
grp_calibrated = 0;
failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
}
} }
} }
}
} else { } else {
grp_calibrated = 0; grp_calibrated = 0;
failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE; failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;