mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-sh
- Various fixes for bugs found by u-boot test.py
This commit is contained in:
commit
d32519ac8a
9 changed files with 91 additions and 8 deletions
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@ -19,6 +19,10 @@
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};
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};
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&vcc_sdhi0 {
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u-boot,off-on-delay-us = <20000>;
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};
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&sdhi2_pins {
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groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
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power-source = <1800>;
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@ -8,6 +8,14 @@
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#include "r8a7795-salvator-x.dts"
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#include "r8a7795-u-boot.dtsi"
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&vcc_sdhi0 {
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u-boot,off-on-delay-us = <20000>;
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};
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&vcc_sdhi3 {
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u-boot,off-on-delay-us = <20000>;
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};
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&sdhi2_pins {
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groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
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power-source = <1800>;
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@ -19,6 +19,10 @@
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};
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};
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&vcc_sdhi0 {
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u-boot,off-on-delay-us = <20000>;
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};
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&sdhi2_pins {
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groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
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power-source = <1800>;
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@ -8,6 +8,14 @@
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#include "r8a7796-salvator-x.dts"
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#include "r8a7796-u-boot.dtsi"
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&vcc_sdhi0 {
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u-boot,off-on-delay-us = <20000>;
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};
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&vcc_sdhi3 {
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u-boot,off-on-delay-us = <20000>;
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};
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&sdhi2_pins {
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groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
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power-source = <1800>;
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@ -8,6 +8,14 @@
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#include "r8a77965-salvator-x.dts"
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#include "r8a77965-u-boot.dtsi"
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&vcc_sdhi0 {
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u-boot,off-on-delay-us = <20000>;
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};
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&vcc_sdhi3 {
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u-boot,off-on-delay-us = <20000>;
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};
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&sdhi2_pins {
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groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
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power-source = <1800>;
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@ -36,6 +36,7 @@
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gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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u-boot,off-on-delay-us = <20000>;
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};
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vccq_sdhi0: regulator-vccq-sdhi0 {
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@ -60,6 +61,7 @@
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gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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u-boot,off-on-delay-us = <20000>;
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};
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vccq_sdhi1: regulator-vccq-sdhi1 {
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@ -44,13 +44,17 @@ static const struct clk_div_table cpg_sd01_div_table[] = {
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{ 0, 0 },
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};
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static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 div)
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static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 val)
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{
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while ((*table++).val) {
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if ((*table).div == div)
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return div;
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for (;;) {
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if (!(*table).div)
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return 0xff;
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if ((*table).val == val)
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return (*table).div;
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table++;
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}
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return 0xff;
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}
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static int gen2_clk_enable(struct clk *clk)
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@ -117,7 +121,7 @@ static ulong gen2_clk_get_rate(struct clk *clk)
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case CLK_TYPE_FF:
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rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
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debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
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debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n",
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__func__, __LINE__,
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core->parent, core->mult, core->div, rate);
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return rate;
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@ -202,8 +206,50 @@ static ulong gen2_clk_get_rate(struct clk *clk)
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return -ENOENT;
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}
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static int gen2_clk_setup_mmcif_div(struct clk *clk, ulong rate)
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{
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struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
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struct cpg_mssr_info *info = priv->info;
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const struct cpg_core_clk *core;
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struct clk parent, pparent;
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u32 val;
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int ret;
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ret = renesas_clk_get_parent(clk, info, &parent);
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if (ret) {
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debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
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return ret;
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}
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if (renesas_clk_is_mod(&parent))
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return 0;
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ret = renesas_clk_get_core(&parent, info, &core);
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if (ret)
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return ret;
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if (strcmp(core->name, "mmc0") && strcmp(core->name, "mmc1"))
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return 0;
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ret = renesas_clk_get_parent(&parent, info, &pparent);
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if (ret) {
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debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
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return ret;
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}
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val = (gen2_clk_get_rate(&pparent) / rate) - 1;
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debug("%s[%i] MMCIF offset=%x\n", __func__, __LINE__, core->offset);
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writel(val, priv->base + core->offset);
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return 0;
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}
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static ulong gen2_clk_set_rate(struct clk *clk, ulong rate)
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{
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/* Force correct MMC-IF divider configuration if applicable */
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gen2_clk_setup_mmcif_div(clk, rate);
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return gen2_clk_get_rate(clk);
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}
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@ -696,7 +696,7 @@ static int sh_mmcif_dm_probe(struct udevice *dev)
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return ret;
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}
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host->clk = clk_get_rate(&sh_mmcif_clk);
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host->clk = clk_set_rate(&sh_mmcif_clk, 97500000);
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plat->cfg.name = dev->name;
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plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
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@ -783,7 +783,10 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks)
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plat->cfg.f_min = mclk /
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(priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
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plat->cfg.f_max = mclk;
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plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
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if (quirks & TMIO_SD_CAP_16BIT)
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plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */
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else
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plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
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upriv->mmc = &plat->mmc;
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