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ARM: DT: stm32f7: add gpio device tree nodes

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Also created alias for gpios for stm32f7 discovery board. Based on these
aliases, it would be possible to get gpio devices by sequence.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
This commit is contained in:
Vikas Manocha 2017-04-10 15:02:58 -07:00 • committed by Tom Rini
parent 774171020b
commit d33a6a2f06
2 changed files with 123 additions and 0 deletions
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12
arch/arm/dts/stm32f746-disco.dts
View file

@ -65,6 +65,18 @@
aliases { aliases {
serial0 = &usart1; serial0 = &usart1;
spi0 = &qspi; spi0 = &qspi;
/* Aliases for gpios so as to use sequence */
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
}; };
}; };

111
arch/arm/dts/stm32f746.dtsi
View file

@ -114,6 +114,117 @@
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
pins-are-numbered; pins-are-numbered;
gpioa: gpio@40020000 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x0 0x400>;
clocks = <&rcc 0 0>;
st,bank-name = "GPIOA";
u-boot,dm-pre-reloc;
};
gpiob: gpio@40020400 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x400 0x400>;
clocks = <&rcc 0 1>;
st,bank-name = "GPIOB";
u-boot,dm-pre-reloc;
};
gpioc: gpio@40020800 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x800 0x400>;
clocks = <&rcc 0 2>;
st,bank-name = "GPIOC";
u-boot,dm-pre-reloc;
};
gpiod: gpio@40020c00 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0xc00 0x400>;
clocks = <&rcc 0 3>;
st,bank-name = "GPIOD";
u-boot,dm-pre-reloc;
};
gpioe: gpio@40021000 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1000 0x400>;
clocks = <&rcc 0 4>;
st,bank-name = "GPIOE";
u-boot,dm-pre-reloc;
};
gpiof: gpio@40021400 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1400 0x400>;
clocks = <&rcc 0 5>;
st,bank-name = "GPIOF";
u-boot,dm-pre-reloc;
};
gpiog: gpio@40021800 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1800 0x400>;
clocks = <&rcc 0 6>;
st,bank-name = "GPIOG";
u-boot,dm-pre-reloc;
};
gpioh: gpio@40021c00 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1c00 0x400>;
clocks = <&rcc 0 7>;
st,bank-name = "GPIOH";
u-boot,dm-pre-reloc;
};
gpioi: gpio@40022000 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2000 0x400>;
clocks = <&rcc 0 8>;
st,bank-name = "GPIOI";
u-boot,dm-pre-reloc;
};
gpioj: gpio@40022400 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2400 0x400>;
clocks = <&rcc 0 9>;
st,bank-name = "GPIOJ";
u-boot,dm-pre-reloc;
};
gpiok: gpio@40022800 {
gpio-controller;
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2800 0x400>;
clocks = <&rcc 0 10>;
st,bank-name = "GPIOK";
u-boot,dm-pre-reloc;
};
usart1_pins_a: usart1@0 { usart1_pins_a: usart1@0 {
pins1 { pins1 {
pinmux = <STM32F746_PA9_FUNC_USART1_TX>; pinmux = <STM32F746_PA9_FUNC_USART1_TX>;