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xilinx_xiic: Fix transfer initialisation
Prior to starting a new transfer, conditionally wait for bus to not be busy. Reinitialise controller as otherwise operation is not stable. For reference, see linux kernel commit 9656eeebf3f1 ("i2c: Revert i2c: xiic: Do not reset controller before every transfer") hs: Fixed DOS line endings added missing '\n' Fixed git commit description style Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
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@ -266,8 +266,20 @@ static void xiic_reinit(struct xilinx_xiic_priv *priv)
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static int xilinx_xiic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
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{
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struct xilinx_xiic_priv *priv = dev_get_priv(dev);
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int ret = 0;
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ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
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XIIC_SR_BUS_BUSY_MASK, false, 1000, true);
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if (ret == -ETIMEDOUT)
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dev_err(dev, "timeout waiting for bus not busy condition\n");
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if (ret)
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return ret;
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xiic_reinit(priv);
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for (; nmsgs > 0; nmsgs--, msg++) {
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if (msg->flags & I2C_M_RD)
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ret = xilinx_xiic_read_common(dev, msg, nmsgs);
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